JP2006005099A - Semiconductor circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a variation in the current performance of a charge pump circuit. <P>SOLUTION: A boost-up capacity element C1 of a charge pump circuit 110 and a capacity element of an oscillator circuit 123 are formed so that the boost-up capacity element C1 of the charge pump circuit 110 and the capacity film (oxidization insulating film) of the capacity element of an oscillator circuit 123 may become the same substantially. Furthermore, it is preferable that the capacity element C1 and the capacity element C2 are simultaneously formed in the same process. By forming the capacity film of each capacity element in this way, it is made possible to greatly reduce a variation in capacity ratio resulting from a variation in the capacity film of the capacity element C1 and the capacity element C2, and moreover to reduce a variation in the current performance Icp of the pump circuit 110. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor circuit device including a booster circuit, and more particularly to a semiconductor circuit device including a booster circuit including a charge pump circuit and an oscillation circuit that controls the charge pump circuit.

  Nonvolatile semiconductor storage devices such as flash memory can be erased and rewritten electrically, and since data is not lost even when the power is turned off, mobile phone, digital camera, personal computer BIOS storage, etc. It is used for many purposes. In the nonvolatile semiconductor memory device as described above, data stored in the memory cell is read by supplying current to the memory cell and detecting the value of the flowing current.

  In such a nonvolatile memory, a voltage higher than the power supply voltage is required to drive the memory cell. As described above, a charge pump type booster circuit is widely used as a circuit for generating a voltage higher than a power supply voltage (see, for example, Patent Document 1). FIG. 6 is a circuit diagram showing a schematic configuration of a charge pump type booster circuit in the prior art. As shown in FIG. 6, the charge pump type booster circuit 600 includes a charge pump circuit 610 and a control circuit 620 that controls the charge pump circuit 610. The output Vout1 of the charge pump circuit 610 is output to the load 630. The load 630 includes, for example, a memory cell.

  In the charge pump circuit 610, a plurality of circuits comprising a diode-connected NMOS transistor Tr1 and a capacitive element C1 are connected in series between the power supply Vdd and the output. In the example of FIG. 6, two capacitive elements C1 and three NMOS transistors Tr1 are illustrated. By inputting a complementary two-phase clock signal to the capacitive element, each capacitive element C1 is charged using the power supply voltage Vdd and the charge is transferred to the output side, whereby an output voltage higher than the power supply voltage Vdd is obtained. Vout1 can be generated.

  The control circuit 620 controls the charge pump circuit 610 by repeatedly supplying and stopping the clock signal so that the output voltage Vout1 of the charge pump circuit 610 becomes a constant value. The control circuit 620 divides the output voltage of the charge pump circuit 610, the comparator 622 that compares the output of the voltage dividing circuit 621 and the reference voltage, and the oscillation circuit 623 that performs an oscillation operation according to the output of the comparator 622. The driving circuit 624 outputs a complementary clock signal to the capacitive element C1 of the charge pump circuit 610 according to the output from the oscillation circuit 623.

  The circuit operation of the charge pump type booster circuit 600 will be described. At startup, the output voltage Vout1 is zero. The comparator 622 compares the output voltage Vout1 divided by the voltage dividing circuit 621 with the reference voltage Vref, and outputs a comparison signal to the transmission circuit 623. The oscillation circuit 623 outputs a clock signal in accordance with the comparison signal from the comparator 622. The clock signal is input to the drive circuit 624, converted into a complementary two-phase clock signal, and input to the capacitive element of the charge pump circuit 610. The charge pump circuit 610 performs a charge operation according to the clock signal, and boosts the output voltage Vout1.

  When the output voltage Vout1 increases, the output of the voltage dividing circuit 621 becomes larger than the reference voltage Vref, and the comparison signal of the comparator 622 changes. The oscillation circuit 623 stops outputting the clock signal in response to the change in the comparison signal from the comparator 622. The charge pump circuit 610 stops the boosting operation. When the output voltage Vout1 decreases, the control circuit 620 starts supplying the clock signal, and the boosting operation of the charge pump circuit 610 is resumed. Thereafter, the same operation is repeated, and the output voltage Vout1 is kept constant.

  FIG. 7 is a circuit diagram showing a partial configuration of a typical oscillation circuit 623. The circuit configuration of FIG. 7 is disclosed in Non-Patent Document 1, for example. As shown in FIG. 7, in the oscillation circuit 623, the source ground circuit including the NMOS transistor Tr2, the resistance element R connected between the drain of the NMOS transistor Tr2 and the power source Vdd, and the output of the source ground circuit are connected. A circuit composed of the capacitive element C2 is connected in a plurality of stages in series. In the example of FIG. 7, three stages of circuits are connected in series.

JP 2003-242790 A "Analog CMOS integrated circuit" written by Behzad Razavi / translated by Tadahiro Kuroda, Maruzen Co., Ltd., p590

  The frequency f of the oscillation circuit shown in FIG. 7 is inversely proportional to the capacitance value of the capacitive element C2. On the other hand, the current capability Icp of the charge pump circuit 610 shown in FIG. 6 is proportional to the oscillation frequency f of the oscillation circuit 623 and the capacitance value of the capacitive element C1 of the charge pump circuit 610. In the conventional charge pump type booster circuit 600, since the charge pump circuit 610 boosts the power supply voltage, the capacitive element C1 is required to be formed as a high breakdown voltage element. On the other hand, in the oscillation circuit 623, the capacitive element C2 is formed as a low breakdown voltage element in order to reduce the area of the capacitive element C2.

  In the semiconductor circuit device, manufacturing variations cannot be avoided. However, as in the prior art, the capacitance element C1 of the charge pump circuit 610 and the capacitance element C2 of the oscillation circuit 623 are formed as different withstand voltage elements. There is a problem that the current capability Icp of the pump circuit 610 varies. Due to variations in the current capability Icp, it is necessary to design a margin in consideration of this, leading to an increase in the size of the booster circuit 600 and an accompanying increase in power consumption.

  The present invention has been made in the background as described above, and it is an object of the present invention to reduce variations in current capability in a charge pump type booster circuit. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A semiconductor circuit device according to a first aspect of the present invention includes a charge pump circuit including a plurality of capacitive elements for temporarily storing transferred charges, and a clock for each of the plurality of capacitive elements of the charge pump circuit. The capacitive film of the plurality of capacitive elements and the capacitive film of the capacitive component that defines the oscillation frequency of the oscillation circuit have substantially the same thickness. By having this configuration, variation in the current capability of the charge pump circuit can be reduced.

  The oscillation circuit includes a capacitive element that acts as the capacitive component, and the capacitive films of the capacitive elements of the charge pump circuit and the capacitive film of the capacitive element of the oscillation circuit have substantially the same thickness. Can be. Alternatively, the oscillation circuit includes a MOS transistor that acts as the capacitive component, and the gate insulating film of the MOS transistor and the capacitive films of the plurality of capacitive elements of the charge pump circuit have substantially the same thickness. Can be.

  According to a second aspect of the present invention, there is provided a semiconductor circuit device comprising: a charge pump circuit including a plurality of capacitive elements for temporarily storing transferred charges; and a clock for each of the plurality of capacitive elements of the charge pump circuit. An oscillation circuit that outputs a signal, and the capacitive film of the plurality of capacitive elements and the capacitive film of a capacitive component that defines an oscillation frequency of the oscillation circuit are formed in the same process. By having this configuration, variation in the current capability of the charge pump circuit can be reduced.

  The oscillation circuit includes a capacitive element that acts as the capacitive component, and the capacitive films of the capacitive elements of the charge pump circuit and the capacitive film of the capacitive element of the oscillation circuit are formed in the same process. be able to. Alternatively, the oscillation circuit includes a MOS transistor that acts as the capacitive component, and the gate insulating film of the MOS transistor and the capacitive films of the plurality of capacitive elements of the charge pump circuit are formed in the same process. be able to.

  According to the present invention, variation in current capability of the charge pump circuit can be reduced.

  Hereinafter, embodiments to which the present invention can be applied will be described. The following description is to describe the embodiment of the present invention, and the present invention is not limited to the following embodiment. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Moreover, those skilled in the art can easily change, add, and convert each element of the following embodiments within the scope of the present invention. In addition, in each drawing, the same code | symbol is attached | subjected to the same element and the duplication description is abbreviate | omitted as needed for clarification of description.

  FIG. 1 is a diagram showing a schematic configuration of a booster circuit 100 in the present embodiment. The booster circuit 100 is used in, for example, a nonvolatile semiconductor memory device such as a flash memory. The booster circuit 100 includes a charge pump circuit 110 and a charge pump control circuit 120 that controls the charge pump circuit 110. A load 180 is connected to the output of the charge pump circuit 110. The load 180 corresponds to, for example, a memory cell of a flash memory. The charge pump circuit 110 boosts and outputs the power supply voltage Vdd, and the output voltage Vout1 is controlled to be a predetermined constant output in the control of the charge pump control circuit 120.

  The charge pump circuit 110 is connected in series between the power supply Vdd and the output Vout1, and is connected to a plurality of (n + 1 in FIG. 1) NMOS transistors Tr1 for controlling charge transfer and a node between the transistors. And a plurality of capacitive elements C1 for temporarily storing transfer charges. Therefore, in FIG. 1, a total of n capacitive elements C1 are shown. Each NMOS transistor Tr1 is diode-connected, and its gate and drain are short-circuited. The source and drain of the adjacent NMOS transistor Tr1 are connected.

  One end of the capacitive element C1 is connected to a node between the NMOS transistors Tr1, and a control signal from the charge pump control circuit 120 is input to the other end of the capacitive element C1. When a clock signal is input to each of the capacitive elements C1, charges are transferred to the capacitive element on the output side, and the output voltage can be boosted.

  The charge pump control circuit 120 includes a resistance voltage dividing circuit 121, a comparator 122, an oscillation circuit 123, and a drive circuit 124. The resistance voltage dividing circuit 121 is composed of resistors R1 and R2 connected in series, and outputs an output Vout2 from its intermediate node. The comparator 121 compares the output Vout1 of the charge pump circuit 110 divided by the resistance voltage dividing circuit 121 with the reference level Vref, and outputs a comparison signal Vout3 corresponding to the magnitude relationship. The output Vout2 of the resistance voltage dividing circuit 121 is input to the non-inverting input of the comparator 122, and the reference level Vref is input to the inverting input.

  The output of the comparator 122 is connected to the oscillation circuit 123. The oscillation circuit 123 outputs a clock signal or a predetermined fixed potential as Vout4 according to the output Vout3 from the comparator 122. Specifically, the oscillation circuit 123 outputs a clock signal (Vout4) while an L level signal is input, and the oscillation circuit 123 outputs a fixed potential Vout4 while an H level signal is input. Is output. The configuration of the oscillation circuit 123 will be described later. The drive circuit 124 outputs, as control signals, an output Vout5 obtained by inverting the output from the oscillation circuit 123 and Vout6 that is in a complementary relationship with Vout5. Vout5 is input to the odd-numbered capacitive element C1 (2k-1), and Vout6 is input to the even-numbered capacitive element C1 (2k).

  The operation of the booster circuit 100 shown in FIG. 1 will be described. FIG. 2A shows complementary clock signals Vouto5 and Vout6 inputted from the charge pump control circuit 120 to the capacitive element C1. The charge pump circuit 110 boosts and outputs the power supply voltage Vdd by transferring charges from the Vdd side to the output Vout1 side in accordance with a complementary clock signal input to the capacitive element C1. Approximately, the output voltage Vout1 is boosted to (Vdd × (n + 1) −Vth × (n + 1)) where the threshold voltage of the NMOS transistor Tr1 is Vth and the number of transistor stages is (n + 1) as shown in FIG. be able to. The booster circuit 100 controls the output voltage Vout1 so that the reference voltage Vref = Vout1 × R2 / (R1 + R2) (= Vout2).

  The overall operation of the booster circuit 100 will be described. FIG. 2B shows the relationship between the output voltage Vout1 and the comparator output Vout3. The output voltage Vout1 is schematically shown for explaining the circuit operation. At the start of the operation, the output voltage Vout1 is “0”. The output Vout2 of the resistance voltage dividing circuit 121 is also “0”, which is a value smaller than Vref. For this reason, the output Vout3 of the comparator becomes “L”. The oscillation circuit 123 outputs a clock signal, and complementary clock signals Vout5 and Vout6 are input from the drive circuit 124 to the capacitive element C1 of the charge pump circuit 110. While the clock signal is input, the charge pump circuit 110 boosts the output voltage Vout1.

  When the output voltage Vout1 rises and becomes the reference voltage Vref <Vout1 × R2 / (R1 + R2), the output Vout2 of the resistance voltage dividing circuit 121 becomes larger than the reference voltage Vref, so that the output Vout3 of the comparator becomes “H”. When the output Vout3 of the comparator becomes “H”, the oscillation circuit 123 changes Vout4 from the output of the clock signal to the fixed potential output. The drive circuit 124 outputs fixed potentials Vout5 and Vout 6, and the charge pump circuit 110 stops the boosting operation (charging operation).

  When the output potential Vout1 gradually decreases and becomes the reference voltage Vref> Vout1 × R2 / (R1 + R2), the comparator output Vout3 changes from “H” to “L”, and the oscillation circuit 123 starts outputting the clock signal. In response to the input of the clock signal, the charge pump circuit 110 starts the boosting operation. Thereafter, by repeating the above operation, the output voltage Vout1 is maintained at a predetermined voltage value.

  FIG. 3 is a circuit diagram showing a schematic configuration of the oscillation circuit 123 of the present embodiment. As shown in FIG. 3, the oscillation circuit 123 includes a plurality of inverter circuits 301 connected in series. In the example of FIG. 3, four inverter circuits 301 are shown. As the inverter circuit 301, a normal CMOS inverter circuit can be used. The output of each inverter circuit 301 is connected to a resistor element R3 (R31-R34) and a capacitor element C2 (C21-C24). The resistor element R3 is connected in series between the inverter circuits 301, and one end of the capacitor element C2 is connected to the ground in this example.

  The oscillation circuit 123 includes a NAND circuit 320 in the preceding stage of the inverter circuit 301 connected in series. A resistor element R35 and a capacitor element C25 are connected between the output of the NAND circuit 320 and the first-stage inverter circuit 310a. These are connected in the same manner as the resistive element R31-34 and the capacitive element C21-24 between the inverter circuits 301. The output Vout3 of the comparator 122 is input to one input of the NAND circuit 320 via the inverter circuit 330. The other input is the output of the final stage of the circuit composed of the inverter circuit 301, the resistor element R3, and the capacitor element C2 connected in series. The output signal of the oscillation circuit 123 is output from a node between the resistance element R35 and the first stage inverter circuit 301a (input of the first stage inverter circuit 301a).

The oscillation frequency of the oscillation circuit 123 is inversely proportional to the capacitance value of the capacitive element C2 in the oscillation circuit 123. That means
f∝1 / C2
The relationship exists. On the other hand, the current capability Icp of the charge pump circuit 110 is proportional to the frequency f of the oscillation circuit 123, the capacitance value of the push-up capacitive element C1 of the charge pump circuit 110, and the power supply voltage. In other words, Icp∝f * C1 * Vdd
The relationship exists.

From the above two relational expressions, the relationship between the current capability Icp of the charge pump circuit 110, the push-up capacitive element C1 of the charge pump circuit 110, and the capacitive element C2 of the oscillation circuit 123 is
Icp∝Vdd * C1 / C2
It becomes. That is, the current capability Icp of the charge pump circuit 110 is proportional to the capacitance ratio of the boosting capacitive element C1 of the charge pump circuit 110 and the capacitive element C2 of the oscillation circuit 123.

  In this embodiment, the push-up capacitive element C1 of the charge pump circuit 110 is set so that the push-up capacitive element C1 of the charge pump circuit 110 and the capacitive film (oxide insulating film) of the capacitive element C2 of the oscillation circuit 123 are substantially the same. Thus, the capacitive element C2 of the oscillation circuit 123 is formed. More preferably, the capacitive element C1 and the capacitive element C2 are simultaneously formed in the same process. By forming the capacitive film of each capacitive element in this way, it is possible to greatly reduce the variation in the capacitance ratio caused by the variation in the capacitive film between the capacitive element C1 and the capacitive element C2. By reducing the variation in the capacitance ratio, the variation in the current capability Icp of the charge pump circuit 110 is reduced, and a design margin can be secured.

  That is, when the capacitor films having the same thickness are provided, particularly when they are formed by the same process, the variations in the capacitor films of the push-up capacitor element C1 of the charge pump circuit 110 and the capacitor element C2 of the oscillation circuit 123 are approximately the same. Variation. As described above, the current capability Icp of the charge pump circuit 110 is proportional to the capacitance ratio between the capacitive element C1 and the capacitive element C2.

  When the capacitance films C1 and C2 have the same variation in capacitance film, the capacitance ratio is kept substantially constant due to the capacitance film variation. Therefore, even if the capacitance film varies (capacitance value variation), the current capability Icp of the charge pump circuit 110 is kept substantially constant. For this reason, variation in the current capability Icp of the charge pump circuit 110 is greatly reduced, and a design margin can be secured. As a result, the booster circuit can be miniaturized and power consumption can be reduced accordingly.

  Since a high voltage is applied to the push-up capacitive element C1 of the charge pump circuit 110 for boosting, it is necessary to use an element with a high breakdown voltage. A capacitor element with high withstand voltage can be formed by forming a capacitor film thick. Similarly, the capacitor C2 of the oscillation circuit 123 uses an element with a high breakdown voltage. The oscillation circuit 123 does not need to be a high breakdown voltage element. However, in order to reduce the variation of Icp due to the variation of the capacitance film as described above, the capacitance film of the capacitance element C2 of the oscillation circuit 123 is also different from that of the capacitance element C1. They are formed simultaneously with the same thickness, more preferably in the same process.

FIG. 4 is a schematic diagram illustrating a schematic device configuration of the capacitive elements C1 and C2. FIG. 4 shows an example in which a capacitive element is formed on a P-type substrate. As shown in FIG. 4, the capacitive element includes a capacitive oxide film 402 formed on a P-type substrate 401, a metal layer 403 formed on the capacitive oxide film, a P ⁺ diffusion region 404 formed in the P-type substrate, The metal layer 405 is formed on the P ⁺ diffusion region. The metal layers 403 and 405 can be formed of aluminum or copper. By controlling the thickness of the capacitor oxide film 402, the capacitance value of the capacitor can be determined. The high breakdown voltage element includes a thick capacitive oxide film 402. The capacitor oxide film 402 can be formed by a normal semiconductor process such as a thermal oxidation method.

  In the oscillation circuit 123 of FIG. 3, the capacitive element C2 is connected between the inverter circuits 301. However, by using the gate capacitance of the MOS transistor, an oscillation circuit can be formed without using this capacitive element. Is possible. FIG. 5A illustrates a configuration example of the oscillation circuit 510 that does not include a capacitor. By connecting a plurality of inverter circuits 511 in series, an oscillation circuit that does not use a capacitor can be configured. The NAND circuit 320 shown above and the inverter circuit 330 connected to the input of the NAND circuit 320 are connected to the preceding stage of the inverter circuits connected in series. The capacitance component that determines the frequency f of the oscillation circuit 510 can be borne by the gate capacitance of the MOS transistor included in the inverter circuit 511.

FIG. 5B is a schematic diagram showing an outline of a typical NMOS transistor device configuration. FIG. 5B shows an NMOS transistor 550 formed on a P-type substrate. As is well known, the NMOS transistor 550 includes a gate 551 that can be formed of polysilicon, a gate oxide film 553 formed between the gate 551 and the P-type substrate 552, and an N ⁺ diffusion region 554 that serves as a source / drain. 555. In the example of FIG. 5B, the MOFET 550 is separated from other elements by an insulating separation film 556. Note that the MOS transistor manufacturing method is a well-known technique, and a description thereof will be omitted.

  As described above, in the MOS transistor 550, the gate oxide film 553 is formed between the gate electrode 551 and the P-type substrate 552. By forming the gate oxide film 553 thick, a MOS transistor as a high breakdown voltage element can be formed. The gate oxide film 553 can be formed by a normal semiconductor process such as a thermal oxidation method, similarly to the capacitor element.

  The capacitive film of the push-up capacitive element C1 of the charge pump circuit 110 and the gate oxide film 553 of the MOS transistor 550 that forms the transmission circuit 124 are formed with the same thickness. In particular, they can be formed simultaneously in the same process. preferable. As a result, the capacitance ratio between the capacitance component that determines the frequency component of the oscillation circuit 123 and the capacitance element C2 of the charge pump 110 can be kept constant, and the current capability Icp of the charge pump 110 due to manufacturing variations can be maintained. Variations can be reduced. By reducing the variation in the current capability Icp, the margin expected at the time of designing is reduced, and it is possible to have the same current capability with a small booster circuit. As a result, it is possible to reduce power consumption.

  In the above embodiment, the charge transfer of the charge pump circuit 110 is performed by the diode-connected NMOS transistor Tr1, but instead of this, a diode element is used or a switch such as a normal NMOS transistor is used. Devices can also be used to control charge transfer. The oscillation circuit 123 can also be configured using, for example, an inverter circuit composed of an NMOS transistor and a resistance element and a capacitor connected to the output of the inverter circuit as described in the prior art. In this embodiment, a positive booster circuit that boosts the voltage in the positive direction has been described as an example. However, the present invention may be applied to a negative booster circuit that boosts the power supply voltage in the negative direction. Is possible.

It is a figure which shows schematic structure of the booster circuit in this embodiment. FIG. 6 is a timing chart for explaining the operation of the booster circuit in the present embodiment. It is a circuit diagram which shows schematic structure of the oscillation circuit in this embodiment. It is a schematic diagram which shows the device structure of the capacitive element in this embodiment. It is a schematic diagram showing a schematic configuration of an oscillation circuit and a device configuration of a MOS transistor in the present embodiment. It is a figure which shows schematic structure of the booster circuit in a prior art. It is a circuit diagram which shows schematic structure of the oscillation circuit in a prior art.

Explanation of symbols

C1 capacitive element, C2 capacitive element, R resistive element, R1 resistive element, R3 resistive element,
R3 resistance element, Tr1 MOS transistor, Tr2 MOS transistor,
100 booster circuit, 110 charge pump circuit,
120 charge pump control circuit, 121 comparator, 121 resistance voltage dividing circuit,
122 comparator, 123 oscillation circuit, 124 drive circuit, 180 load,
301 inverter circuit, 320 NAND circuit, 330 inverter circuit,
401 P-type substrate, 402 capacitive oxide film, 403 metal layer, 404 P ⁺ diffusion region,
405 metal layer, 510 oscillation circuit, 511 inverter circuit,
550 NMOS transistor, 551 gate electrode, 552 P-type substrate,
553 gate oxide film, 554 N ⁺ diffusion region, 555 N ⁺ diffusion region,
556 insulating separation membrane, 600 charge pump type booster circuit,
610 charge pump circuit, 620 control circuit, 621 voltage dividing circuit,
622 Comparator, 623 Transmitter circuit, 624 Drive circuit, 630 Load

Claims (6)

A charge pump circuit comprising a plurality of capacitive elements for temporarily storing transferred charges;
An oscillation circuit that outputs a clock signal to each of the plurality of capacitive elements of the charge pump circuit,
The capacitive films of the plurality of capacitive elements and the capacitive film of the capacitive component that defines the oscillation frequency of the oscillation circuit have substantially the same thickness.
Semiconductor circuit device. The oscillation circuit includes a capacitive element that acts as the capacitive component,
The capacitive films of the plurality of capacitive elements of the charge pump circuit and the capacitive films of the capacitive elements of the oscillation circuit have substantially the same thickness.
The semiconductor circuit device according to claim 1. The oscillation circuit includes a MOS transistor that acts as the capacitance component,
The gate insulating film of the MOS transistor and the capacitive films of the plurality of capacitive elements of the charge pump circuit have substantially the same thickness.
The semiconductor circuit device according to claim 1. A charge pump circuit comprising a plurality of capacitive elements for temporarily storing transferred charges;
An oscillation circuit that outputs a clock signal to each of the plurality of capacitive elements of the charge pump circuit,
The capacitive films of the plurality of capacitive elements and the capacitive film of the capacitive component defining the oscillation frequency of the oscillation circuit are formed in the same process.
Semiconductor circuit device. The oscillation circuit includes a capacitive element that acts as the capacitive component,
The capacitive films of the plurality of capacitive elements of the charge pump circuit and the capacitive film of the capacitive element of the oscillation circuit are formed in the same process.
The semiconductor circuit device according to claim 4. The oscillation circuit includes a MOS transistor that acts as the capacitance component,
The gate insulating film of the MOS transistor and the capacitive films of the plurality of capacitive elements of the charge pump circuit are formed in the same process.
The semiconductor circuit device according to claim 4.

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