JP2004153332A - Clock generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock generating circuit for suppressing variations of a generated clock by controlling an oscillating frequency of a VCO within a prescribed range when a frequency fluctuation of an input reference clock is great. <P>SOLUTION: A reference clock adjustment circuit 10 compares a phase of a feedback clock subjected to 1/M frequency division with the input reference clock so that the phase of the clock generated by a VCO 50 is the same as the phase of the input reference clock. Then as a result of comparison, when the phase of the input reference clock is led or lagged by a prescribed range or over, an adjusted reference clock resulting from adjusting the input reference clock is outputted to a phase comparator 20. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock generation circuit configured with a phase locked loop (PLL), and more particularly to a clock generation circuit for suppressing an influence on an output clock when a reference clock has a large frequency fluctuation. It is.
[0002]
[Prior art]
A clock generation circuit using a PLL compares a phase of a feedback clock generated by dividing an output clock of a voltage controlled oscillator (VCO) by a predetermined value with a frequency divider and an input reference clock. The transmission frequency of the VCO is controlled based on the comparison result, and the frequency of the output clock is adjusted. That is, the clock generation circuit using the PLL generates the output clock following the reference clock. Therefore, when the frequency fluctuation of the input reference clock is large, the jitter component included in the output clock becomes large. The removal rate of the frequency fluctuation of the input reference clock to the output clock is determined by the transfer function of the PLL. The transfer function is determined by the conversion gain of the VCO, the conversion gain of the phase comparator, the transfer function of the loop filter for removing the high frequency component of the control signal of the phase comparator, and the division ratio of the frequency divider. A large change in the frequency of the clock, for example, a change longer than the cycle of the output clock cannot be eliminated.
[0003]
In order to solve such a problem, for example, a conventional clock generation circuit counts an edge interval of an input reference clock based on a clock generated by a VCO, and determines whether the count value is within a predetermined range. When it is out of the predetermined range, the operation of the phase comparator is stopped so that the VCO is not controlled, and the fluctuation of the output clock is suppressed. (For example, see Patent Document 1).
[0004]
[Patent Document 1]
JP 2001-53600 A
[0005]
[Problems to be solved by the invention]
However, in the above-described conventional technology, when the frequency fluctuation of the input reference clock is large, the operation of the phase comparator is stopped so that the VCO is not controlled, so that the VCO is controlled over a plurality of cycles of the input reference clock. Therefore, the output clock is generated without causing a problem that the jitter component of the output clock increases. Further, the edge of the input reference clock is counted based on the output clock with the increased jitter component, and there is a problem that the accuracy of the determination in the predetermined range is deteriorated.
[0006]
The present invention has been made in view of the above, and an object of the present invention is to provide a clock generation circuit that suppresses fluctuation of a generated clock by controlling the oscillation frequency of a VCO within a predetermined range when the frequency fluctuation of an input reference clock is large. The purpose is.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a feedback clock obtained by dividing an output clock of a voltage controlled oscillator to a predetermined value is generated by a frequency divider, and a phase comparator detects a phase difference between the feedback clock and an input reference clock. In a clock generation circuit using a phase-locked loop that generates a phase error signal for eliminating a leverage phase difference and controls an output clock of the voltage controlled oscillator, when a frequency fluctuation of the input reference clock is larger than a predetermined range. And an adjusting circuit for adjusting the frequency variation within a predetermined range.
[0008]
According to the present invention, the adjustment circuit divides the output clock of the voltage controlled oscillator to a predetermined value and sets the phase difference of the input reference clock to a predetermined value based on the feedback clock generated so as to have the same phase as the input reference clock. Is larger than the range, the fluctuation is adjusted to a predetermined range to control the voltage-controlled oscillator.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of a clock generation circuit according to the present invention will be described in detail with reference to the accompanying drawings.
[0010]
Embodiment 1 FIG.
Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of the clock generation circuit according to the first embodiment of the present invention. The clock generation circuit according to the first embodiment includes a reference clock adjustment circuit 10 (an adjustment circuit referred to in the claims), a phase comparator 20, a charge pump 30, a low-pass filter (LPF) 40, a VCO 50, and a frequency divider 60. Have.
[0011]
The reference clock adjusting circuit 10 compares the feedback clock generated by the frequency divider 60 with the input reference clock, and, if the difference is equal to or more than a predetermined value, outputs the adjusted reference clock obtained by adjusting the input reference clock to the phase comparator 20. Output to If the difference is within a predetermined value, the input reference clock is output to the phase comparator 20 as the adjusted reference clock without adjustment.
[0012]
The phase comparator 20 compares the phase of the adjustment reference clock with the phase of the feedback clock generated by the frequency divider 60, and outputs a phase error signal to the charge pump.
[0013]
The charge pump 30 boosts the phase error signal output from the phase comparator 20 to a level at which the voltage of the VCO 50 can be controlled, and outputs the boosted phase error signal to the LPF 40.
[0014]
The LPF 40 cuts off the high frequency component of the phase error signal boosted by the charge pump 30 and outputs a phase error signal whose high frequency component is cut off to the VCO 50.
[0015]
The VCO 50 performs transmission control based on the phase error signal whose high-frequency component has been cut off by the LPF 40, and generates an output clock obtained by multiplying the input reference clock by M (M> 0, M is an integer). The VCO 50 outputs an output clock to the frequency divider 60 and the reference clock adjustment circuit 10.
[0016]
The frequency divider 60 generates a feedback clock by dividing the output clock generated by the VCO 50 by 1 / M, and outputs the generated feedback clock to the phase comparator 20.
[0017]
An outline of the operation of the clock generation circuit according to the first embodiment will be described with reference to time charts of FIGS. FIG. 2 is a time chart when the frequency fluctuation of the input reference clock is within one cycle of the output clock with respect to the feedback clock. In FIG. 2, the input reference clock lags behind the feedback clock by the difference a. Since the difference a is within one cycle of the output clock, the reference clock adjustment circuit 10 outputs the input reference clock to the phase comparator 20. That is, when the phase difference between the input reference clock and the feedback clock is within one cycle of the output clock, the reference clock adjustment circuit 10 does not perform the adjustment operation and outputs the input reference clock as it is to the phase comparator 20 as the adjustment reference clock. .
[0018]
FIG. 3A is a time chart when the frequency fluctuation of the input reference clock is delayed by one or more output clock cycles with respect to the feedback clock. In FIG. 3A, the input reference clock lags behind the feedback clock by a difference a. Since the difference a is equal to or more than one cycle of the output clock, the reference clock adjustment circuit 10 adjusts the input reference clock. As shown in FIG. 3B, the reference clock adjustment circuit outputs to the phase comparator 20 an adjustment reference clock delayed by a time t corresponding to one cycle of the output clock from the rising edge of the feedback clock.
[0019]
FIG. 4A is a time chart in the case where the frequency fluctuation of the input reference clock leads the output clock by one or more cycles of the output clock. In FIG. 4A, the input reference clock leads the difference a with respect to the feedback clock. Since the difference a is equal to or more than one cycle of the output clock, the reference clock adjustment circuit 10 adjusts the input reference clock. As shown in FIG. 3B, the reference clock adjustment circuit outputs to the phase comparator 20 an adjustment reference clock that is advanced by a time t corresponding to one cycle of the output clock from the rising edge of the feedback clock.
[0020]
As described above, when the frequency fluctuation of the input reference clock is large, the reference clock adjustment circuit 10 outputs to the phase comparator 20 the adjustment reference clock whose fluctuation is suppressed to one cycle of the output clock with respect to the feedback clock.
[0021]
The phase comparator 20 compares the phases of the comparison clock and the feedback clock. As a result, when the phase of the feedback clock is ahead of the phase of the comparison clock, a phase error signal for lowering the oscillation frequency of the VCO 50 is output to the charge pump 30. When the phase of the feedback clock lags behind the phase of the comparison clock, a phase error signal for increasing the oscillation frequency of the VCO 50 is output to the charge pump 30.
[0022]
The charge pump 30 stores the input phase error signal, boosts the voltage to a level at which the voltage of the VCO 50 can be controlled, and outputs it to the LPF 40.
[0023]
The LPF 40 removes high-frequency components of the phase error signal boosted by the charge pump 30 and outputs the signal to the VCO 50.
[0024]
The VCO 50 adjusts the oscillation frequency based on the phase error signal from which the high-frequency component has been removed by the LPF 40, and generates an output clock. The VCO 50 outputs an output clock to the frequency divider 60 and the reference clock adjustment circuit 10.
[0025]
The frequency divider 60 divides the output clock by a predetermined value, that is, a value set to have the same phase as the input reference clock, and generates a feedback clock. Then, a feedback clock is generated in the phase comparator 20.
[0026]
FIG. 5 is a block diagram showing an example of the configuration of the reference clock adjustment circuit 10 shown in FIG. The reference clock adjustment circuit 10 includes an M counter 11, an MJ counter 12, an M + K counter 13, an AND gate AND14, an OR gate OR15, and a selector 16.
[0027]
The M counter 11 counts M VCO clocks, which are output clocks generated by the VCO 50. The M counter 11 has the same function as that of the frequency divider 60, and generates a reference value instead of the feedback clock. Then, the reference value is output to the selector 16. The MJ counter 12 counts MJ VCO clocks (J> 0, J is an integer). The M + K counter 13 counts M + K (K> 0, K is an integer) VCO clocks.
[0028]
The input reference clock and the output of the MJ counter 12 are input to the AND 14. When the phase of the input reference clock is ahead of the reference value by a predetermined value (in this case, the period of J VCO clocks), the AND 14 outputs the adjustment reference clock masking the input reference clock to the selector 16. Also, when the input reference clock is within a predetermined range, the input reference clock is output.
[0029]
The input reference clock and the output of the M + K counter 13 are input to the OR 15. When the phase of the input reference clock lags behind the reference clock by a predetermined value (in this case, the period of K VCO clocks), the OR 15 outputs a value adjustment reference clock to compensate for the delay to the selector 16. I do.
[0030]
The selector 16 selects the output of the AND 14 when the reference value is “L”, and selects the output of the OR 15 when the reference value is “H”.
[0031]
The detailed operation of the reference clock adjustment circuit 10 will be described with reference to the time charts of FIGS. FIG. 6 shows a time chart when the phase of the input reference clock is earlier than the reference value. As shown in FIG. 6, the input reference clock goes to “H” earlier than the reference value. However, the output of the MJ counter 12 is "L" because it is earlier than the reference value by J VCO clocks. Therefore, the output of the AND 14 remains at “L” and does not change. Since the input reference clock has changed to “H”, the OR 15 changes the output to “H”. However, since the reference value is "L", the selector 16 selects the output of the AND 14, and the adjustment reference clock remains "L".
[0032]
The MJ counter 12 counts MJ VCO clocks and sets the output to “H”. When the output of the MJ counter 12 changes to "H", the AND 14 changes the output to "H" because the input reference clock is already "H". Since the reference value is "L", the selector 16 selects the output of the ADN 14, and sets the adjustment reference clock to "H". Thus, even when the phase of the input reference clock is earlier than the reference value, it is possible to output the adjusted reference clock that is suppressed by fluctuations within a predetermined range.
[0033]
FIG. 7 shows a time chart when the phase of the input reference clock is later than the reference value. The MJ counter 12 counts MJ VCO clocks and sets the output to “H”. However, since the input reference clock is "L", the output of the AND 14 remains "L". The M counter 11 counts M VCO clocks and changes the output to “H”. When the output of the M counter 11 changes to “H”, the selector 16 selects the output of the OR 15. However, since the input reference clock and the output of the M + K counter 13 are both "L", the adjustment reference clock remains at "L".
[0034]
The M + K counter 13 counts M + K VCO clocks and sets the output to “H”. When the output of the M + K counter 13 changes to "H", the OR 15 changes the output to "H". Since the reference value is already “H”, the selector 16 selects the output of the OR 15 and sets the reference adjustment clock to “H”. Thereby, even when the phase of the input reference clock becomes slower than the reference value, it is possible to output the adjusted reference clock suppressed by the fluctuation within a predetermined range.
[0035]
As described above, in the first embodiment, the reference clock adjusting circuit 10 adjusts the phases of the feedback clock and the input reference clock obtained by dividing the clock generated by the VCO 50 by 1 / M so as to have the same phase as the input reference clock. Compare. Then, as a result of the comparison, when the phase of the input reference clock is advanced or delayed by more than a predetermined range, the adjusted reference clock obtained by adjusting the input reference clock is output to the phase comparator 20. As a result, even when the frequency fluctuation of the input reference clock is large, the clock frequency generated by the VCO 50 can be controlled using the adjusted reference clock whose fluctuation is suppressed, and the fluctuation of the output clock can be suppressed.
[0036]
Although the phase comparator 20 performs the phase comparison at the rising edge, the phase comparison may be performed at the falling edge or the pulse width.
[0037]
Further, as shown in FIG. 8, the value of the counter of the reference clock adjusting circuit 10 may be set from the outside. That is, the count values of the MJ counter 12 and the M + K counter 13 in FIG. 5 can be set from the outside. If the frequency fluctuation of the input reference clock is large, for example, in the higher frequency (the phase is advanced as compared with the feedback clock), the value of J is set large and the value of K is set small. If the fluctuation is large in the lower frequency (the phase is delayed as compared with the feedback clock), the value of J is set small and the value of K is set large. When the change of the input reference clock changes in a time series, the values of J and K are set large when the change is large, and the values of J and K are set small when the change is small. As described above, by setting the values of J and K from the outside, it is possible to generate an optimal adjustment reference clock closer to the input reference clock, and the VCO 50 is adjusted in accordance with the fluctuation period and occurrence probability of the input reference clock. By controlling, the fluctuation of the output clock can be suppressed.
[0038]
Further, as shown in FIG. 9, whether or not to operate the reference clock adjustment circuit 10 may be set externally. In other words, it is possible to externally set whether the phase comparator 20 uses the input reference clock or the adjustment reference clock as the clock for phase comparison with the feedback clock. This setting may be changed periodically or at an arbitrary timing. For example, when the frequency fluctuation of the input reference clock is a constant cycle, the VCO 50 is controlled using the input reference clock without operating the reference clock adjustment circuit 10 during the period when the frequency fluctuation is small. The reference clock adjusting circuit 10 is operated to control the VCO 50 using the adjusted reference clock whose fluctuation is suppressed. This allows the VCO 50 to be controlled in accordance with the fluctuation period and occurrence probability of the input reference clock, thereby suppressing fluctuations in the output clock.
[0039]
Of course, as shown in FIG. 10, the setting of the count values of the MJ counter 12 and the M + K counter 13 and the ON / OFF setting of whether or not to operate the reference clock adjusting circuit 10 can be simultaneously set. May not be set by an external terminal, but may be a signal of the setting circuit 80 for generating values of J and K and ON / OFF signals. When the frequency of the input reference clock fluctuates periodically, the setting circuit 80 changes the set value every period. Thereby, the reference clock adjusting circuit 10 can be operated in conjunction with the fluctuation of the input reference clock.
[0040]
Embodiment 2 FIG.
Embodiment 2 of the present invention will be described with reference to FIGS. In the second embodiment, the fluctuation of the output clock is suppressed by adjusting the input reference clock to be compared with the feedback clock. In the second embodiment, the fluctuation of the output clock is suppressed by adjusting the phase error signal that controls the VCO 50 that generates the clock.
[0041]
FIG. 11 is a block diagram showing a configuration of the clock generation circuit according to the second embodiment of the present invention. The clock generation circuit shown in FIG. 11 includes a phase error adjustment circuit 70 (an adjustment circuit in claims) between the phase comparator 20 and the charge pump 30. Components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.
[0042]
When the phase error signal output from the phase comparator 20 is a signal that changes the oscillation frequency of the VCO 50 by a predetermined value or more, the phase error adjustment circuit 70 controls the phase error signal so that the change is within a predetermined value. To adjust. The phase error signal includes an UP signal for increasing the oscillation frequency of the VCO 50 and a DOWN signal for decreasing the oscillation frequency of the VCO 50. The phase error adjustment circuit 70 adjusts the UP signal and the DOWN signal to suppress the fluctuation of the output clock of the VCO 50.
[0043]
The VCO 50 operates to increase the oscillation frequency when both the UP signal and the DOWN signal become “H”, and operates so as to decrease the oscillation frequency when both the UP signal and the DOWN signal become “L”.
[0044]
FIG. 12 is a block diagram showing a configuration of the phase error adjustment circuit 70 shown in FIG. The phase error adjusting circuit 70 includes an MJ counter 12, an M + K counter 13, inverters 71 and 72 as inverting circuits, ANDs 73 and 74 as AND gates, and a NAND 75 as a NAND gate.
[0045]
The MJ counter 12 counts MJ (J> 1, J is an integer) VCO clocks. The M + K counter 13 counts M + K (K> 1, K is an integer) VCO clocks.
[0046]
The output of the MJ counter 12 and the output of the M + K counter 13 via the inverter 72 are input to the AND 73. That is, the AND 73 sets the MASK signal to “H” only within a predetermined range of the frequency fluctuation.
[0047]
The AND 74 receives the DOWN signal and the output MASK of the AND 73 and adjusts the DOWN signal. The NAND 75 receives the UP signal via the inverter 71 and the output MASK of the AND 73 to adjust the UP signal.
[0048]
The detailed operation of the phase error adjustment circuit 70 will be described with reference to the time charts of FIGS. FIG. 13 shows a time chart when the DOWN signal is output because the phase of the input reference clock is earlier than the phase of the feedback clock. As shown in FIG. 13, the UP signal changes from “H” to “L”. Thus, one input of the NAND 75 becomes “H”. However, since both the MJ counter 12 and the M + K counter 13 are "L", the MASK signal is "L" and the adjustment UP signal remains "H".
[0049]
The MJ counter 12 counts MJ VCO clocks and sets the output to “H”. Since the M + K counter 13 does not count M + K VCO clocks, “H” has been input to the AND 73 via the inverter 72. The signal is set to “H”. When the MASK signal changes to “H”, the UP signal input via the inverter 71 becomes valid, and the NAND 75 sets the adjustment UP signal to “L”. As a result, the adjustment UP signal becomes “L” and the adjustment DOWN signal becomes “L”, so that the frequency of the VCO 50 is specified to be increased.
[0050]
FIG. 14 shows a time chart when the DOWN signal is output because the phase of the input reference clock is later than the phase of the feedback clock. The MJ counter 12 counts MJ VCO clocks and sets the output to “H”. Since the M + K counter 13 does not count M + K VCO clocks, the output is “L”. Therefore, the MASK signal becomes “H”, the NAND 75 validates the UP signal, and the AND 74 validates the DOWN signal. However, since the DOWN signal is at "L", the adjusted DOWN signal remains at "L".
[0051]
Since the phase of the input reference clock is behind the phase of the feedback clock, when the DOWN signal becomes “H” so as to increase the oscillation frequency of the VCO 50, the AND 74 validates the DOWN signal and changes the adjusted DOWN signal to “H”. "
[0052]
The M + K counter 13 counts M + K VCO clocks and sets the output to “H”. When the output of the M + K counter 13 changes to "H", the AND 73 changes the MASK signal to "L". When the MASK signal changes to “L”, the AND 74 sets the adjustment DOWN signal to “H”. As a result, the adjustment UP signal becomes “H” and the adjustment DOWN signal becomes “L”, and the designation of lowering the oscillation frequency of the VCO 50 is released.
[0053]
As described above, in the second embodiment, the phase error adjustment circuit 70 enables the UP signal and the DOWN signal output from the phase comparator 20 only within a predetermined range, so that the frequency of the input reference clock is Even if the fluctuation is large, the clock frequency generated by the VCO 50 can be controlled by using the adjusted UP signal and the adjusted DOWN signal in which the fluctuation is suppressed, and the fluctuation of the output clock can be suppressed.
[0054]
As shown in FIG. 15, the counter value of the phase error adjustment circuit 70 may be set from the outside. That is, the count values of the MJ counter 12 and the M + K counter 13 in FIG. 11 can be set from the outside. If the frequency fluctuation of the input reference clock is large, for example, in the higher frequency (the phase is advanced as compared with the feedback clock), the value of J is set large and the value of K is set small. If the fluctuation is large in the lower frequency (the phase is delayed as compared with the feedback clock), the value of J is set small and the value of K is set large. When the change of the input reference clock changes in a time series, the values of J and K are set large when the change is large, and the values of J and K are set small when the change is small. As described above, by setting the values of J and K from the outside, it is possible to control the VCO 50 in accordance with the fluctuation cycle and the occurrence probability of the input reference clock, thereby suppressing the fluctuation of the output clock.
[0055]
Further, whether or not to operate the phase error adjustment circuit 70 may be set externally. That is, it is possible to externally set whether to use the UP signal and the DOWN signal generated by the phase comparator 20 as they are or to perform adjustment. This allows the VCO 50 to be controlled in accordance with the fluctuation period and occurrence probability of the input reference clock, thereby suppressing fluctuations in the output clock.
[0056]
Further, the setting of the count values of the MJ counter 12 and the M + K counter 13 and the ON / OFF setting of whether or not to operate the phase error adjustment circuit 70 can be simultaneously set, and these settings can be made by external terminals. Instead, it may be specified from a setting circuit that generates the values of J and K and the ON / OFF signal. When the frequency of the input reference clock fluctuates periodically, the setting circuit changes the set value every period. Thereby, the reference clock adjusting circuit 10 can be operated in conjunction with the fluctuation of the input reference clock.
[0057]
【The invention's effect】
As described above, according to the clock generation circuit of the present invention, the adjustment circuit divides the output clock of the voltage controlled oscillator to a predetermined value and generates the feedback clock generated so as to have the same phase as the input reference clock. When the phase difference of the input reference clock is larger than a predetermined range with respect to the reference, the fluctuation is adjusted to the predetermined range to control the voltage-controlled oscillator. However, fluctuations in the output clock generated by the voltage controlled oscillator can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an example of a configuration of a clock generating circuit according to a first embodiment of the present invention;
FIG. 2 is a time chart for explaining an operation of the clock generating circuit according to the first embodiment of the present invention;
FIG. 3 is a time chart for explaining the operation of the clock generating circuit according to the first embodiment of the present invention;
FIG. 4 is a time chart for explaining the operation of the clock generating circuit according to the first embodiment of the present invention;
FIG. 5 is a block diagram illustrating a configuration of a reference clock adjustment circuit illustrated in FIG. 1;
FIG. 6 is a time chart for explaining the operation of the reference clock adjustment circuit.
FIG. 7 is a time chart for explaining the operation of the reference clock adjustment circuit.
FIG. 8 is a block diagram illustrating an example of a configuration of a clock generation circuit according to a first embodiment of the present invention;
FIG. 9 is a block diagram illustrating an example of a configuration of a clock generation circuit according to the first embodiment of the present invention;
FIG. 10 is a block diagram illustrating an example of a configuration of a clock generation circuit according to a first embodiment of the present invention;
FIG. 11 is a block diagram illustrating an example of a configuration of a clock generation circuit according to a second embodiment of the present invention;
FIG. 12 is a block diagram showing a configuration of a phase error adjustment circuit shown in FIG.
FIG. 13 is a time chart for explaining the operation of the phase error adjustment circuit.
FIG. 14 is a time chart for explaining the operation of the phase error adjustment circuit.
FIG. 15 is a block diagram illustrating an example of a configuration of a clock generation circuit according to a second embodiment of the present invention;
[Explanation of symbols]
10 Reference clock adjustment circuit, 11 M counter, 12 M-J counter, 13 M + K counter, 14, 73, 74 AND, 15 OR, 16 selector, 20 phase comparator, 30 charge pump, 40 LPF, 50 VCO, 60 minutes Frequency divider, 70 phase error adjustment circuit, 71, 72 inverter, 75 NAND, 80 setting circuit.

Claims (8)

A frequency divider generates a feedback clock obtained by dividing the output clock of the voltage controlled oscillator to a predetermined value. In a clock generation circuit using a phase locked loop that generates a phase error signal and controls an output clock of the voltage controlled oscillator,
An adjusting circuit that adjusts the frequency fluctuation within a predetermined range when the frequency fluctuation of the input reference clock is larger than a predetermined range;
A clock generation circuit comprising: The adjustment circuit includes:
When the phase difference between the input reference clock and the feedback clock is within a predetermined range, the input reference clock is output to the phase comparator, and the phase difference between the input reference clock and the feedback clock is out of a predetermined range. 2. The clock generation circuit according to claim 1, wherein in such a case, an adjusted reference clock adjusted so that the phase of the input reference clock falls within a predetermined range is output to a phase comparator. The adjustment circuit includes:
When the asserted state of the phase error signal is within a predetermined range, the phase error signal is output to the voltage-controlled oscillator. 2. The clock generating circuit according to claim 1, wherein the clock generating circuit outputs the signal to a voltage-controlled oscillator after changing to a negated state. The said predetermined range designates the case where the phase of the input reference clock is advanced and the case where the phase of the input reference clock is delayed with respect to the feedback clock, by the number of cycles of the output clock of the voltage controlled oscillator. The clock generation circuit according to any one of the above. 5. The clock generation circuit according to claim 4, wherein the number of periods of the output clock of the voltage controlled oscillator for designating the predetermined range is set externally. 6. The control circuit according to claim 1, wherein when the frequency fluctuation of the input reference clock is larger than a predetermined range, whether or not the frequency fluctuation is adjusted within a predetermined range is switched by setting. The clock generation circuit according to any one of the above. 7. The clock generation circuit according to claim 6, wherein the setting of whether to operate the adjustment circuit is set externally. A setting circuit that periodically changes the setting of the number of clock cycles of the voltage-controlled oscillator that specifies the predetermined range and / or the setting of whether to operate the adjustment circuit;
The clock generation circuit according to claim 4, further comprising:

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