JP2004079813A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor fabricating process for excluding certainly surges entering a protecting MIS transistor with a fundamental structure and a process that are held in common between the protecting MIS transistor and the other MIS transistor. <P>SOLUTION: A mask for forming a high concentration source and drain region (7a, 7b) and then shadows of a gate electrode (4) and side wall (5) are utilized to control an implantation angle, so that high concentration well regions (10a, 10b) are formed by an ion implantation. In processes for forming the high concentration source and drain regions (7a, 7b), as the high concentration well regions (10a, 10b) can be formed, the protecting MIS transistor can be formed compatibly with preventing increase in cost and deterioration in transistor characteristics without increase in lithography processes and in the number of masks. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having a metal-insulator-semiconductor (MIS) transistor, and more particularly to a method for manufacturing a semiconductor device having a protective MIS transistor with improved surge resistance.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a semiconductor integrated circuit, as a countermeasure against a surge input, a MIS transistor connected to an input / output pad (hereinafter abbreviated as a “protection MIS transistor”) receives a surge current when a surge input is applied. There is provided a structure for allowing the air to escape to the ground.
[0003]
5A to 5E are cross-sectional views illustrating a manufacturing process of a semiconductor device having a conventional protective MIS transistor and a normal MIS transistor. Here, a method of manufacturing a semiconductor device having an n-channel type protection MIS transistor connected to an input / output pad and an n-channel type normal MIS transistor not connected to an input / output pad will be described.
[0004]
First, in a step shown in FIG. 5A, a shallow trench isolation (STI) region 102 that divides a protection MIS transistor formation region A100 and a normal MIS transistor formation region A150 on the Si substrate 101 and surrounds each active region. To form Thereafter, a p-type impurity is implanted into the Si substrate 101 by ion implantation to form a p-type substrate region 101a having a well layer, a channel stopper layer, and the like. After that, a thermal oxide film and a polysilicon film are sequentially formed on the substrate, and then the polysilicon film and the thermal oxide film are patterned by lithography and dry etching to form a gate insulating film 103 and a gate electrode 104 on the active region. And are formed.
[0005]
Next, in a step shown in FIG. 5B, a photoresist film 131 having an opening in the protection MIS transistor formation region A100 is formed on the substrate by using a lithography technique. Then, using the photoresist film 131 and the gate electrode 104 as a mask, phosphorus ions (P) as n-type impurities are formed in the Si substrate 101 in the protective MIS transistor formation region A100. ⁺ ) Is implanted to form a lightly doped source region 106a and a lightly doped drain region 106b. Subsequently, using the photoresist mask 131 and the gate electrode 104 as masks, boron ions (B ⁺ ) Is implanted into the Si substrate 101 in the protection MIS transistor formation region A100 to form a pocket region.
[0006]
Next, in a step shown in FIG. 5C, after removing the photoresist film 131, a photoresist film 132 having an opening over the normal MIS transistor formation region A150 is formed by covering the protection MIS transistor formation region A100 on the substrate. Form. Then, using the photoresist film 132 and the gate electrode 104 as a mask, arsenic ions (As ⁺ ) Is performed to form the extension regions 166a and 166b. Subsequently, using the photoresist film 132 and the gate electrode 104 as a mask, boron ions (B) as p-type impurities are formed in the Si substrate 101 in the normal MIS transistor formation region A150. ⁺ ) Is performed to form a pocket region 168.
[0007]
Next, in a step shown in FIG. 5D, after the photoresist film 132 is removed, a silicon oxide film is deposited on the substrate, and the silicon oxide film is etched back by anisotropic dry etching to form a side surface of the gate electrode 104. A sidewall 105 is formed thereon. Thereafter, using the gate electrode 104 and the side wall 105 as a mask, n-type impurities are ion-implanted into the Si substrate 101, and the diffusion depth is higher than the low-concentration source / drain regions 106a and 106b and the extension regions 166a and 166b. Concentration source / drain regions 107a and 107b are formed.
[0008]
Next, in a step shown in FIG. 5E, a photoresist having an opening in a part of the high-concentration source / drain regions 107a and 107b of the protection MIS transistor formation region A100 close to the STI 102 by using a lithography technique. A film 133 is formed. Then, using the photoresist film 133 as a mask, boron ions (B) as p-type impurities are formed in the Si substrate 101 in the protection MIS transistor formation region A100. ⁺ ) Is implanted to form high concentration well regions 110a and 110b.
[0009]
By such a manufacturing method, the high-concentration well regions 110a and 110b are formed in the high-concentration source / drain regions 107a and 107b of the protection MIS transistor formation region A100 under a part near the STI 102. As a result, when a reverse voltage is applied between the drain and the substrate due to surge input or the like, the electric field between the high-concentration well region 110b and the high-concentration drain region 107b increases in the protective MIS transistor, causing drain breakdown. The surge can be quickly released to the ground.
[0010]
[Problems to be solved by the invention]
However, in the conventional manufacturing method, a dedicated photoresist film 133 is required to form the high-concentration well regions 110a and 110b, which greatly increases the lithography process and the like, and complicates the manufacturing process. Therefore, there is a possibility that the manufacturing cost will increase and the MIS transistor characteristics will deteriorate.
[0011]
An object of the present invention is to provide a method for manufacturing a semiconductor device having a protective MIS transistor having a structure capable of reliably releasing a surge without increasing the number of lithography steps in order to solve the conventional problem. And
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a first method of manufacturing a semiconductor device according to the present invention includes a first MIS transistor directly connected to an input / output pad formed in a first MIS transistor formation region on a first conductivity type semiconductor region. Forming a trench-type element isolation region surrounding an active region of the first MIS transistor formation region in the semiconductor region; and (a) forming an active region of the first MIS transistor formation region in the semiconductor region. (B) forming a first gate insulating film and a first gate electrode thereon; and after the step (b), a photoresist film having an opening on the first MIS transistor formation region on the substrate. Forming the first MIS transistor using the photoresist film and the first gate electrode as a mask. (D) performing ion implantation of a second conductivity type impurity into the semiconductor region to form a second conductivity type low concentration source / drain region; and using the photoresist film and the first gate electrode as a mask. Oblique ion implantation of a first conductivity type impurity into the semiconductor region of the first MIS transistor formation region, and a first ion implantation of a first impurity at a position separated from below the end of the first gate electrode in the source / drain region of the first MIS transistor. (E) forming a one conductivity type impurity diffusion region.
[0013]
According to this configuration, the oblique ion implantation for forming the impurity diffusion region uses the same photoresist film as the mask for forming the low concentration source / drain regions as a mask. It is not necessary to form a dedicated photoresist film for forming the substrate. Therefore, since the number of lithography steps does not increase, the complexity of the manufacturing steps can be avoided. In addition, since the impurity diffusion region is formed only in a part of the high-concentration source / drain region on the element isolation region side at a position separated from below the end of the first gate electrode, a reverse voltage is applied between the source and the drain. Is applied, the electric field during this period becomes high, drain breakdown occurs, and the surge can be released to the ground, so that the first MIS transistor having high surge resistance can be formed.
[0014]
The method for manufacturing a first semiconductor device further includes a second MIS transistor that is not directly connected to an input / output pad formed in a second MIS transistor formation region on the first conductivity type semiconductor region, and the step (a). In the step (b), the trench-type element isolation region surrounding the active region of the second MIS transistor formation region is formed in the semiconductor region. In the step (b), a second region is formed on the active region of the second MIS transistor formation region. A gate insulating film and a second gate electrode are formed, and in the step (c), the photoresist film is formed so as to cover the second MIS transistor formation region.
[0015]
Further, in the first method for manufacturing a semiconductor device, the first gate insulating film is formed to be thicker than the second gate insulating film.
[0016]
In the first method of manufacturing a semiconductor device, in the step (e), an implantation angle of the oblique ion implantation of the first conductivity type impurity may be a vertical line to the surface of the semiconductor region and the one side. The angle is equal to or greater than the angle between the upper end of the photoresist film and the straight line connecting the upper end of the first gate electrode on the other side. Thereby, the impurity diffusion region can be selectively formed at a position separated from below the end of the first gate electrode in the source / drain region of the first MIS transistor.
[0017]
Further, in the first method of manufacturing a semiconductor device, in the step (e), an implantation angle of the oblique ion implantation of the first conductivity type impurity is set such that a vertical line to the surface of the semiconductor region and the one side of the impurity are implanted. The angle is smaller than the angle between a straight line connecting the edge of the upper surface of the photoresist film, the active region on the other side, and the boundary between the element isolation region. This makes it possible to selectively form the impurity diffusion region in the active region at a position separated from below the end of the first gate electrode in the source / drain region of the first MIS transistor.
[0018]
According to a second method of manufacturing a semiconductor device of the present invention, there is provided a method of manufacturing a semiconductor device having a first MIS transistor directly connected to an input / output pad formed in a first MIS transistor formation region on a first conductivity type semiconductor region. Forming a trench type element isolation region surrounding the active region of the first MIS transistor formation region in the semiconductor region (a); and forming a first gate insulating region on the active region of the first MIS transistor formation region. (B) forming a film and a first gate electrode; and (c) forming a first insulating sidewall on a side surface of the first gate electrode after the step (b). Forming a photoresist film having an opening on the first MIS transistor formation region on the substrate after the step (c); Using the first film, the first gate electrode, and the first insulating sidewall as a mask, ion-implanting a second conductivity type impurity into the semiconductor region of the first MIS transistor formation region, Forming a second conductive type high concentration source / drain region (e), forming the first MIS transistor by using the photoresist film, the first gate electrode, and the first insulating sidewall as a mask; Oblique ion implantation of a first conductivity type impurity into the semiconductor region of the first region, and a first conductivity type impurity diffusion region at a position separated from below an end of the first gate electrode in a source / drain region of the first MIS transistor. And (f) forming
[0019]
According to this configuration, the oblique ion implantation for forming the impurity diffusion region is performed using the same photoresist film as that for forming the high-concentration source / drain regions as a mask, so that the impurity diffusion as in the conventional manufacturing process is performed. There is no need to form a dedicated photoresist film for forming the region. Therefore, since the number of lithography steps does not increase, the complexity of the manufacturing steps can be avoided. In addition, since the impurity diffusion region is formed only in a part of the high-concentration source / drain region on the element isolation region side at a position separated from below the end of the first gate electrode, a reverse voltage is applied between the source and the drain. Is applied, the electric field during this period becomes high, drain breakdown occurs, and the surge can be released to the ground, so that the first MIS transistor having high surge resistance can be formed.
[0020]
The method for manufacturing a second semiconductor device further includes a second MIS transistor that is not directly connected to an input / output pad formed in a second MIS transistor formation region on the first conductivity type semiconductor region, In the step (b), the trench-type element isolation region surrounding the active region of the second MIS transistor formation region is formed in the semiconductor region. In the step (b), a second region is formed on the active region of the second MIS transistor formation region. Forming a gate insulating film and a second gate electrode, forming a second insulating sidewall on a side surface of the second gate electrode in the step (c), and forming the second insulating sidewall in the step (d); The photoresist film is formed so as to have an opening on the 2MIS transistor formation region, and in the step (e), the photoresist film and the photoresist film are formed. Using the second gate electrode and the second insulating sidewall as a mask, ion implantation of a second conductivity type impurity is performed into the semiconductor region of the second MIS transistor formation region, and a second conductivity type impurity of the second MIS transistor is formed. Forming a high-concentration source / drain region, and in the step (f), performing oblique ion implantation of the first conductivity type impurity using the photoresist film as a mask, thereby forming the semiconductor in the second MIS transistor formation region. It is preferable that the first conductivity type impurity is not implanted into the region.
[0021]
In the second method for manufacturing a semiconductor device, the first gate insulating film is formed to be thicker than the second gate insulating film.
[0022]
In the second method for fabricating a semiconductor device, in the step (f), an angle of the oblique ion implantation of the first conductivity type impurity may be a vertical line to the surface of the semiconductor region and the one side. The angle is equal to or greater than the angle between the upper end of the photoresist film and the straight line connecting the upper end of the first gate electrode on the other side.
[0023]
Further, in the manufacturing method of the second semiconductor device, in the step (f), an angle of the oblique ion implantation of the first conductivity type impurity is set such that an implantation angle of the oblique ion implantation is equal to a vertical line to the surface of the semiconductor region, and The angle is smaller than the angle between a straight line connecting the edge of the upper surface of the photoresist film, the active region on the other side, and the boundary between the element isolation region.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described. FIGS. 1A to 1D and 2A to 2C are cross-sectional views showing the steps of manufacturing the semiconductor device according to the first embodiment of the present invention. In this embodiment, an n-channel protection MIS transistor connected to an input / output pad driven by a 3.3V power supply voltage and an n-channel not connected to an input / output pad driven by a 1.5V power supply voltage A method of manufacturing a semiconductor device having a normal type MIS transistor will be described. Note that the p-channel MIS transistor is formed by basically the same manufacturing method as the n-channel MIS transistor described below in this embodiment, if the conductivity type of the impurity introduced into the diffusion layer is reversed. It is possible.
[0025]
First, in the step shown in FIG. 1A, a shallow trench-type element isolation region made of a silicon oxide film is defined on a Si substrate 1 so as to partition a protection MIS transistor formation region A10 and a normal MIS transistor formation region A15 so as to surround each active region. A region (STI: Shallow Trench Isolation) 2 is formed with a depth of about 300 nm. Then, boron ions (B ⁺ ) (Or boron fluoride ion (BF ²⁺ ) Is implanted three times under three conditions with different dose amounts and different acceleration voltages to form a p-type substrate region 1a.
[0026]
First, the acceleration voltage is about 280 keV and the dose is about 1 × 10 ^Thirteen atms · cm ^-2 Ion implantation is performed under the implantation conditions described above to form a lower well layer 21 for preventing latch-up in a deep portion (a region deeper than the bottom of the STI 2) of the Si substrate 1.
[0027]
Next, the acceleration voltage is about 120 keV and the dose is about 6 × 10 ¹² atms · cm ^-2 By performing ion implantation under the implantation conditions described above, a middle well layer 22 functioning as a channel stopper is formed in the middle portion of the Si substrate 1 in a region which is shallower than the lower well layer 21 and has substantially the same depth as the bottom of the STI 2.
[0028]
Next, the acceleration voltage is about 45 keV and the dose is about 5 × 10 ¹² atms · cm ^-2 The upper well layer 23 for controlling the threshold is formed in a shallow portion of the Si substrate 1 in a channel region in a region shallower than the middle well layer 22 (shallower than the bottom of the STI 2). To form
[0029]
Thus, a p-type substrate region 1a including the lower well layer 21, the middle well layer 22, and the upper well layer 23 is formed.
[0030]
Next, in a step shown in FIG. 1B, a photoresist film 31 is formed on the substrate so as to cover the protection MIS transistor formation region A10 and to have an opening on the normal MIS transistor formation region A15. Thereafter, using this photoresist film 31 as a mask, BF as a p-type impurity is added to the normal MIS transistor formation region A15 of the Si substrate 1. ²⁺ Ion (or B ⁺ Ions) at an acceleration voltage of 45 keV and a dose of about 5 × 10 ¹² atms · cm ^-2 Is performed under the implantation conditions described above to form a high-concentration upper well layer 24 for obtaining a threshold voltage suitable for the operation of a 1.5 V type normal MIS transistor. That is, the upper well layer 23 formed in the step shown in FIG. 1A has an impurity concentration suitable for the threshold voltage of the 3.3 V type protection MIS transistor, and suitable for the threshold voltage of the 1.5 V type normal MIS transistor. In order to obtain an improved impurity concentration, a high concentration upper well layer 24 is formed.
[0031]
Next, in a step shown in FIG. 1C, after removing the photoresist film 31, a silicon oxide film having a thickness of about 6 nm is formed on each of the MIS transistor formation regions A10 and A15. Thereafter, using the photoresist film (not shown) covering the protection MIS transistor formation region A10 as a mask, only the silicon oxide film on the normal MIS transistor formation region A15 is selectively removed by wet etching. Then, after removing the photoresist film, the surface of the Si substrate 1 is thermally oxidized again to form a silicon oxide film having a thickness of about 7 nm in the protection MIS transistor formation region A10 and the normal MIS transistor formation region A15. Forms a silicon oxide film having a thickness of about 2.8 nm.
[0032]
Then, after depositing a polysilicon film having a thickness of about 180 nm on the silicon oxide film, the polysilicon film and the silicon oxide film are patterned by a lithography technique and a dry etching technique to form a gate insulating film 3 (3a, 3b) and a gate. The electrode 4 is formed. However, while the gate insulating film 3a and the gate electrode 4 made of a silicon oxide film having a thickness of about 7 nm are formed in the protection MIS transistor formation area A10, the silicon film having a thickness of about 2.8 nm is formed in the normal MIS transistor formation area A15. A gate insulating film 3b and a gate electrode 4 made of an oxide film are formed. Hereinafter, illustration of the lower well layer 21, the middle well layer 22, the upper well layer 23, and the high concentration upper well layer 24 is omitted.
[0033]
Next, in a step shown in FIG. 1D, a photoresist film 32 covering the normal MIS transistor formation region A15 on the substrate and having an opening on the protection MIS transistor formation region A10 is formed. Then, using the photoresist film 32 and the gate electrode 4 as a mask, phosphorus ions (P) as n-type impurities are formed in the Si substrate 1 in the protection MIS transistor formation region A10. ⁺ ) At an implantation angle of about 25 °, an acceleration voltage of about 30 keV, and a dose of about 1.5 × 10 ^Thirteen atms · cm ^-2 The oblique rotation ion implantation of four steps is performed under the implantation conditions described above to form a low-concentration source region 6a and a low-concentration drain region 6b.
[0034]
Subsequently, by using the photoresist film 32 and the gate electrode 4 as a mask, p-type impurities of B ⁺ Ion (or BF ²⁺ Ions) at an implantation angle of about 25 °, an acceleration voltage of about 25 keV, and a dose of about 3 × 10 ¹² atms · cm ^-2 4 steps of obliquely rotating ion implantation are performed under the implantation conditions described above to form pocket regions 8. At this time, the pocket region 8 is formed in the Si substrate 1 below the gate electrode 4 so as to protrude from the lower end of the low-concentration source / drain regions 6a and 6b on the gate side toward the channel region.
[0035]
Next, in the step shown in FIG. 2A, after removing the photoresist film 32, a photoresist film 33 having an opening over the normal MIS transistor formation region A15 is formed by covering the protection MIS transistor formation region A10 on the substrate. Form. Then, using the photoresist film 33 and the gate electrode 4 as a mask, arsenic ions (As ⁺ ) At an acceleration voltage of about 10 keV and a dose of about 4 × 10 ¹⁴ atms · cm ^-2 The ion implantation is performed under the implantation conditions described above to form the extension regions 66a and 66b. At this time, the extension regions 66a and 66b are formed from the region located below the end of the gate electrode 4 on the Si substrate 1 to the region adjacent to the STI2.
[0036]
Then, using the photoresist film 33 and the gate electrode 4 as a mask, BF as a p-type impurity is formed in the Si substrate 1 in the normal MIS transistor formation region A15. ²⁺ Ion (or B ⁺ Ions) at an implantation angle of about 25 °, an acceleration voltage of about 50 keV, and a dose of about 6 × 10 ¹² atms · cm ^-2 4 steps of obliquely rotating ion implantation are performed under the implantation conditions described above to form pocket regions 68. At this time, the pocket region 68 is formed in the Si substrate 1 below the gate electrode 4 so as to protrude from the lower end of the extension regions 66a and 66b on the gate side toward the channel region.
[0037]
Next, in the step shown in FIG. 2B, after removing the photoresist film 33, a silicon oxide film having a thickness of 80 nm is deposited on the substrate, and the silicon oxide film is etched back by anisotropic dry etching to form the gate electrode 4. Is formed on the side surface of the. Thereafter, a photoresist film 34 having openings in the protective MIS transistor formation region A10 and the normal MIS transistor formation region A15 is formed on the substrate.
[0038]
Then, using the photoresist film 34, the gate electrode 4 and the sidewalls 5 as a mask, ion implantation of n-type impurities is performed on the Si substrate 1 to reduce the concentration of the low-concentration source / drain regions 6a and 6b and the extension regions 66a and 66b. High-concentration source / drain regions 7a and 7b having a large diffusion depth are formed. The high-concentration source / drain regions 7a and 7b are formed by three times of ion implantation under different implantation conditions. First, the acceleration voltage is about 20 keV, and the dose is about 5 × 10 ^Fifteen atms · cm ^-2 Under the injection conditions of As ⁺ After ion implantation, the acceleration voltage is about 50 keV and the dose is about 6 × 10 ^Fifteen atms · cm ^-2 Under the injection conditions of As ⁺ Ions are implanted, and finally, the accelerating voltage is about 50 keV, and the dose is about 5.2 × 10 ^Thirteen atms · cm ^-2 P ⁺ Implant ions. By forming the high-concentration source / drain regions 7a and 7b by three ion implantations in this manner, the N-type impurity concentration in the vicinity of the junction can be formed at a low concentration, thereby reducing the junction capacitance. Can be.
[0039]
Next, in the step shown in FIG. 2C, similarly to the high-concentration source / drain regions 7a and 7b, using the gate electrode 4, the side wall 5, and the photoresist film 34 as a mask, the Si substrate 1 contains p-type impurity B ⁺ Ion (or BF ²⁺ Ions) at an implantation angle of θ (65) °, an acceleration voltage of about 60 keV, and a dose of about 5 × 10 ^Thirteen atms · cm ^-2 Ion implantation is performed under the implantation conditions described above to selectively form the high-concentration well regions 10a and 10b only in a part of the lower part of the high-concentration source / drain regions 7a and 7b on the STI2 side of the protection MIS transistor formation region A10.
[0040]
At this time, the implantation angle of the ion implantation is such that when the oblique implantation is performed from the upper surface of the Si substrate 1 on the side of the high-concentration source region 7a into the Si substrate 1 on the side of the high-concentration drain region 7b, the photoresist film 34, the gate electrode 4, and the side wall 5 is used as a mask, and the angle is set so as to be implanted into only a part of the high-concentration drain region 7b on the STI2 side separated from below the end of the gate electrode 4. Similarly, when the oblique implantation is performed from the upper surface of the Si substrate 1 on the side of the high-concentration drain region 7b into the Si substrate 1 on the side of the high-concentration source region 7a, the photoresist film 34, the gate electrode 4, and the sidewall 5 serve as a mask. The angle is set so as to be injected only into a part of the high-concentration source region 7a on the STI2 side separated from below the end of the gate electrode 4.
[0041]
That is, the implantation angle θ ° is perpendicular to the surface of the Si substrate 1 in the protective MIS transistor formation region A10 and the upper surface end of the photoresist film 34 on one side (for example, on the STI 2 on the high concentration source region 7a side). The upper end of the photoresist film 34 was connected to the upper end of the gate electrode 4 and the sidewall 5 on the other side (for example, the upper end of the gate electrode 4 and the sidewall 5 on the high-concentration drain region 7b side). Set the angle to be equal to or greater than the angle between the straight line. Further, the implantation angle θ ° is different from the vertical line to the surface of the Si substrate 1 in the protective MIS transistor formation region A10 and the upper end of the photoresist film 34 on one side (for example, on the STI 2 on the high concentration source region 7a side). The angle is smaller than the angle between the upper surface edge of the photoresist film 34 and the straight line connecting the boundary between the STI 2 on the other side and the active region (for example, the boundary between the high concentration drain region 7 b and the STI 2). Set the angle. As a result, ions are not implanted into the normal MIS transistor formation region A15 where the width of the active region in the gate length direction is smaller than that of the protection MIS transistor formation region A10, and ions are implanted only in a part of the protection MIS transistor formation region A10. Implantation is performed to form high concentration well regions 10a and 10b.
[0042]
Thereafter, the photoresist film 34 is removed, a heat treatment is performed to activate the impurities implanted in the Si substrate 1, and then an interlayer insulating film (not shown) made of a silicon oxide film is formed on the substrate. Then, by forming the connection hole and the contact and the wiring layer, a semiconductor device having a protective MIS transistor and a normal MIS transistor can be obtained.
[0043]
According to the present embodiment, when ion implantation for forming the high concentration well regions 10a and 10b, a photoresist mask for forming a high concentration well region as in a conventional manufacturing process is not required, so that the manufacturing process Complexity can be avoided. That is, using the photoresist film 34 for forming the high-concentration source / drain regions 7a and 7b as a mask as it is and utilizing the shadow of the gate electrode 4 and the side wall 5, the ion implantation angle is in the range of 30 ° to 80 °. By doing so, the high concentration well regions 10a and 10b can be formed only in a part of the protection MIS transistor formation region A10.
[0044]
In this formation method, the high-concentration well regions 10a and 10b can be formed subsequent to the high-concentration source / drain regions 7a and 7b forming step, so that the manufacturing cost can be increased and the MIS transistor characteristics can be increased without increasing the number of lithography steps and masks. It is possible to form a protective MIS transistor while preventing deterioration. Moreover, since the high concentration well regions 10a and 10b are formed in the protection MIS transistor formation region A10 in a part of the high concentration source / drain regions 7a and 7b on the STI2 side, a reverse voltage is applied between the source and the drain. When the voltage is applied, the electric field during this period increases, causing drain breakdown, and the surge can be released to the ground. Therefore, a protective MIS transistor having high surge resistance can be formed.
[0045]
(Second embodiment)
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. 3A to 3D and 4A to 4C are cross-sectional views illustrating the steps of manufacturing the semiconductor device according to the second embodiment of the present invention. Here, the steps shown in FIGS. 3A to 3C are the same as the steps shown in FIGS. 1A to 1C in the first embodiment, and thus the description thereof will be omitted.
[0046]
Next, in a step shown in FIG. 3D, a photoresist film 32 covering the normal MIS transistor formation region A15 on the substrate and having an opening on the protection MIS transistor formation region A10 is formed. Then, using the photoresist film 32 and the gate electrode 4 as a mask, a P-type impurity as an n-type impurity is formed in the Si substrate 1 in the protection MIS transistor formation region A10. ⁺ The ion implantation angle is about 25 °, the acceleration voltage is about 30 keV, and the dose is about 1.5 × 10 ^Thirteen atms · cm ^-2 The oblique rotation ion implantation of four steps is performed under the implantation conditions described above to form a low-concentration source region 6a and a low-concentration drain region 6b.
[0047]
Subsequently, using the photoresist film 32 and the gate electrode 4 as a mask, BF as a p-type impurity is introduced into the Si substrate 1 in the protection MIS transistor formation region A10. ²⁺ Ion (or B ⁺ Ions) at an implantation angle of about 25 °, an acceleration voltage of about 50 keV, and a dose of about 6 × 10 ¹² atms · cm ^-2 4 steps of obliquely rotating ion implantation are performed under the implantation conditions described above to form pocket regions 8. At this time, the pocket region 8 is formed in the Si substrate 1 below the gate electrode 4 so as to protrude from the lower end of the low-concentration source / drain regions 6a and 6b on the gate side toward the channel region.
[0048]
Next, in the step shown in FIG. 4A, similarly to the formation of the low-concentration source / drain regions 6a and 6b and the pocket region 8, the p-type impurity is contained in the Si substrate 1 using the gate electrode 4 and the photoresist film 32 as a mask. B ⁺ Ion (or BF ²⁺ Ions) at an implantation angle of θ (65) °, an acceleration voltage of about 60 keV, and a dose of about 5 × 10 ^Thirteen atms · cm ^-2 The high-concentration well regions 10a and 10b are selectively formed only in a part of the protection MIS transistor formation region A10 on the STI2 side under the implantation conditions of FIG.
[0049]
At this time, the implantation angle of the ion implantation is such that when the oblique implantation is performed from the upper surface of the Si substrate 1 on the side of the low concentration source region 6a into the Si substrate 1 on the side of the low concentration drain region 6b, the photoresist film 32 and the gate electrode 4 serve as a mask. The angle is set such that it is implanted into only a part of the low-concentration drain region 6b on the STI2 side. Similarly, when the oblique implantation is performed from the upper surface of the Si substrate 1 on the side of the low-concentration drain region 6b into the Si substrate 1 on the side of the low-concentration source region 6a, the photoresist film 32 and the gate electrode 4 serve as a mask to form the low-concentration source region 6a. The angle is set so as to be injected into only a part of the region on the STI2 side. That is, the implantation angle θ ° is different from the vertical line to the surface of the Si substrate 1 in the protective MIS transistor formation region A10 and the upper surface end of the photoresist film 32 on one side (for example, on the STI2 on the low concentration source region 6a side). Equivalent to the angle between the straight line connecting the upper end of the photoresist film 32 and the upper end of the gate electrode 4 on the other side (for example, the upper end of the gate electrode 4 on the low-concentration drain region 6b side). The angle is set so as to be above. Further, the implantation angle θ ° is different from the vertical line to the surface of the Si substrate 1 in the protective MIS transistor formation region A10 and the upper end of the photoresist film 32 on one side (for example, on the STI2 on the low concentration source region 6a side). The angle is smaller than the angle between the upper surface end of the photoresist film 32 and a straight line connecting the other side of the boundary between the STI2 and the active region (for example, the boundary between the low-concentration drain region 6b and the STI2). Set the angle. As a result, ions are implanted only into a part of the protection MIS transistor formation region A10 on the STI2 side, and the high concentration well regions 10a and 10b are formed.
[0050]
Next, in the step shown in FIG. 4B, after removing the photoresist film 32, a photoresist film 33 having an opening over the normal MIS transistor formation region A15 is formed by covering the protection MIS transistor formation region A10 on the substrate. Form. Then, using the photoresist film 33 and the gate electrode 4 as a mask, arsenic ions (As ⁺ ) At an acceleration voltage of about 10 keV and a dose of about 4 × 10 ¹⁴ atms · cm ^-2 The ion implantation is performed under the implantation conditions described above to form the extension regions 66a and 66b. At this time, the extension regions 66a and 66b are formed from the region located below the end of the gate electrode 4 on the Si substrate 1 to the region adjacent to the STI2.
[0051]
Then, using the photoresist film 33 and the gate electrode 4 as a mask, BF as a p-type impurity is formed in the Si substrate 1 in the normal MIS transistor formation region A15. ²⁺ Ion (or B ⁺ Ions) at an implantation angle of about 25 °, an acceleration voltage of about 50 keV, and a dose of about 6 × 10 ¹² atms · cm ^-2 4 steps of obliquely rotating ion implantation are performed under the implantation conditions described above to form pocket regions 68. At this time, the pocket region 68 is formed in the Si substrate 1 below the gate electrode 4 so as to protrude from the lower end of the extension regions 66a and 66b on the gate side toward the channel region.
[0052]
Next, in the step shown in FIG. 4C, after removing the photoresist film 33, a silicon oxide film having a thickness of 80 nm is deposited on the substrate, and the silicon oxide film is etched back by anisotropic dry etching to form the gate electrode 4. Is formed on the side surface of the. Thereafter, a photoresist film 34 having openings in the protective MIS transistor formation region A10 and the normal MIS transistor formation region A15 is formed on the substrate.
[0053]
Then, using the photoresist film 34, the gate electrode 4 and the sidewalls 5 as a mask, n-type impurities are ion-implanted into the Si substrate 1 to form the low-concentration source region 6a, the low-concentration drain region 6b, and the extension regions 66a and 66b. A high-concentration source region 7a and a high-concentration drain region 7b having a deeper diffusion depth are formed. The high-concentration source region 7a and the high-concentration drain region 7b may be formed by three times of ion implantation under different implantation conditions as in the first embodiment.
[0054]
Thereafter, the photoresist film 34 is removed, a heat treatment is performed to activate the impurities implanted in the Si substrate 1, and then an interlayer insulating film (not shown) made of a silicon oxide film is formed on the substrate. Then, by forming the connection hole and the contact and the wiring layer, a semiconductor device having a protective MIS transistor and a normal MIS transistor can be obtained.
[0055]
According to the present embodiment, similarly to the first embodiment, at the time of ion implantation for forming the high-concentration well regions 10a and 10b, a photoresist for forming a high-concentration well region as in a conventional manufacturing process is used. Since a mask is not required, complication of the manufacturing process can be avoided. In addition, since the high concentration well regions 10a and 10b are formed only in a part of the high concentration source / drain regions 7a and 7b on the STI2 side in the protection MIS transistor formation region A10, a reverse voltage is applied between the source and the drain. Is applied, the electric field during this period increases, causing drain breakdown and allowing the surge to escape to the ground, so that a protective MIS transistor having high surge resistance can be formed.
[0056]
【The invention's effect】
As described above, according to the present invention, the source / drain region and the substrate region of the protective MIS transistor connected to the input / output pad can be connected without affecting the transistor characteristics and without increasing the lithography process. The junction withstand voltage is reduced, and the surge entering from the pad can be quickly released to the substrate region, so that the surge resistance can be improved.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a first half of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.
2A to 2C are cross-sectional views illustrating a latter half of a manufacturing process of the semiconductor device according to the first embodiment of the present invention;
3A to 3D are cross-sectional views illustrating a first half of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.
4A to 4C are cross-sectional views illustrating a latter half of a manufacturing process of the semiconductor device according to the second embodiment of the present invention.
5A to 5E are cross-sectional views illustrating a manufacturing process of a conventional semiconductor device.
[Explanation of symbols]
1 Si substrate
1a Substrate area
2 Shallow trench isolation region (STI)
3a, 3b Gate insulating film
4 Gate electrode
5 Sidewall
6a Low concentration source region
6b Low concentration drain region
7a High concentration source region
7b High concentration drain region
8 pocket area
10a High concentration well area
10b High concentration well area
21 Lower well layer
22 Middle well layer
23 Upper well layer
31-34 Photoresist film
66a Extension area
66b extension area
68 pocket area

Claims (10)

A method of manufacturing a semiconductor device having a first MIS transistor directly connected to an input / output pad formed in a first MIS transistor formation region on a first conductivity type semiconductor region,
(A) forming a trench-type element isolation region surrounding the active region of the first MIS transistor formation region in the semiconductor region;
(B) forming a first gate insulating film and a first gate electrode on the active region of the first MIS transistor formation region;
(C) forming a photoresist film having an opening on the first MIS transistor formation region on the substrate after the step (b);
Using the photoresist film and the first gate electrode as a mask, ions of a second conductivity type impurity are implanted into the semiconductor region of the first MIS transistor formation region, and a second conductivity type low concentration source / drain region is formed. Forming (d),
Using the photoresist film and the first gate electrode as a mask, oblique ion implantation of a first conductivity type impurity is performed into the semiconductor region of the first MIS transistor formation region, and the oblique ion implantation of a source / drain region of the first MIS transistor is performed. Forming a first conductivity type impurity diffusion region at a position separated from below the end of the first gate electrode (e). The method for manufacturing a semiconductor device according to claim 1,
A second MIS transistor that is not directly connected to an input / output pad formed in a second MIS transistor formation region on the first conductivity type semiconductor region;
In the step (a), the trench type element isolation region surrounding the active region of the second MIS transistor formation region is formed in the semiconductor region.
In the step (b), a second gate insulating film and a second gate electrode are formed on the active region of the second MIS transistor formation region,
In the step (c), a method of manufacturing a semiconductor device, wherein the photoresist film is formed so as to cover the second MIS transistor formation region. The method for manufacturing a semiconductor device according to claim 2,
A method for manufacturing a semiconductor device, wherein the thickness of the first gate insulating film is larger than the thickness of the second gate insulating film. The method of manufacturing a semiconductor device according to claim 1,
In the step (e), the implantation angle of the oblique ion implantation of the first conductivity type impurity is perpendicular to the surface of the semiconductor region, the upper surface end of the photoresist film on one side, and the first angle on the other side. A method of manufacturing a semiconductor device having an angle equal to or greater than an angle between a straight line connecting the upper end of the gate electrode and the upper end. The method for manufacturing a semiconductor device according to claim 4,
In the step (e), the implantation angle of the oblique ion implantation of the first conductivity type impurity is set such that a vertical line to the surface of the semiconductor region, an upper end of the photoresist film on one side, and an active region on the other side. A method of manufacturing a semiconductor device having an angle smaller than an angle between a straight line connecting the boundary with the element isolation region. A method of manufacturing a semiconductor device having a first MIS transistor directly connected to an input / output pad formed in a first MIS transistor formation region on a first conductivity type semiconductor region,
(A) forming a trench-type element isolation region surrounding the active region of the first MIS transistor formation region in the semiconductor region;
(B) forming a first gate insulating film and a first gate electrode on the active region of the first MIS transistor formation region;
(C) forming a first insulating sidewall on a side surface of the first gate electrode after the step (b);
Forming a photoresist film having an opening on the first MIS transistor formation region on the substrate after the step (c);
Using the photoresist film, the first gate electrode, and the first insulating sidewall as a mask, ion implantation of a second conductivity type impurity is performed into the semiconductor region of the first MIS transistor formation region, and the first MIS is formed. Forming a second conductive type high concentration source / drain region of the transistor (e);
Using the photoresist film, the first gate electrode, and the first insulating sidewall as a mask, oblique ion implantation of a first conductivity type impurity is performed into the semiconductor region of the first MIS transistor formation region, Forming a first conductivity type impurity diffusion region in a source / drain region of a 1MIS transistor at a position separated from below an end of the first gate electrode (f). The method for manufacturing a semiconductor device according to claim 6,
A second MIS transistor that is not directly connected to an input / output pad formed in a second MIS transistor formation region on the first conductivity type semiconductor region;
In the step (a), the trench type element isolation region surrounding the active region of the second MIS transistor formation region is formed in the semiconductor region.
In the step (b), a second gate insulating film and a second gate electrode are formed on the active region of the second MIS transistor formation region,
In the step (c), a second insulating sidewall is formed on a side surface of the second gate electrode,
In the step (d), the photoresist film is formed so as to have an opening on the second MIS transistor formation region,
In the step (e), using the photoresist film, the second gate electrode, and the second insulating sidewall as a mask, ions of a second conductivity type impurity are added to the semiconductor region of the second MIS transistor formation region. Implanting to form a second conductive type high concentration source / drain region of the second MIS transistor;
In the step (f), the oblique ion implantation of the first conductivity type impurity is performed using the photoresist film as a mask, so that the first conductivity type impurity is in the semiconductor region of the second MIS transistor formation region. A method for manufacturing a semiconductor device that is not implanted. The method for manufacturing a semiconductor device according to claim 7,
A method for manufacturing a semiconductor device, wherein the thickness of the first gate insulating film is larger than the thickness of the second gate insulating film. The method for manufacturing a semiconductor device according to claim 6, wherein
In the step (f), the implantation angle of the oblique ion implantation of the first conductivity type impurity is perpendicular to the surface of the semiconductor region, the upper end of the photoresist film on one side, and the first side on the other side. A method of manufacturing a semiconductor device having an angle equal to or greater than an angle between a straight line connecting the upper end of the gate electrode and the upper end. The method of manufacturing a semiconductor device according to claim 9,
In the step (f), the implantation angle of the oblique ion implantation of the first conductivity type impurity is such that a vertical line to the surface of the semiconductor region, an upper end of the photoresist film on one side, and an active region on the other side. A method of manufacturing a semiconductor device having an angle smaller than an angle between a straight line connecting the boundary with the element isolation region.

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