JP2003249467A - Substrate polishing method - Google Patents
Substrate polishing methodInfo
- Publication number
- JP2003249467A JP2003249467A JP2002049110A JP2002049110A JP2003249467A JP 2003249467 A JP2003249467 A JP 2003249467A JP 2002049110 A JP2002049110 A JP 2002049110A JP 2002049110 A JP2002049110 A JP 2002049110A JP 2003249467 A JP2003249467 A JP 2003249467A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- polishing
- carrier
- substrates
- unevenness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
Abstract
(57)【要約】
【課題】 1枚の研磨布で2枚以上の基板を同時に研磨
し、端数の基板を研磨する場合、端数の基板の研磨量を
同じ研磨時間で1バッチ処理時に全ての基板を表面の凹
凸部の段差を有する基板とした場合の研磨量を同一とす
ることによって、端数の基板でも規定の膜厚に合わせ込
む基板の研磨方法を提供する。
【解決手段】 キャリア1に製品基板3、キャリア2に
ダミーの基板4を装着して、キャリア1に製品基板3、
キャリア2に製品基板4を装着した場合の研磨時間で1
バッチ2枚の研磨を行う。ダミーの基板4においては製
品基板の膜質より硬度の高い膜質で凹凸の段差の無い基
板を選択する。ダミーの基板4の代わりにセラミック材
や石英材の加工品を用いても良い。
(57) [Summary] [PROBLEMS] When two or more substrates are simultaneously polished with one polishing cloth and a fractional substrate is polished, the fractional substrate is polished by the same amount of polishing time in one batch processing. By providing the same amount of polishing when the substrate is a substrate having a step with uneven portions on the surface, a method for polishing a substrate can be provided in which even a fractional substrate is adjusted to a specified film thickness. SOLUTION: A product substrate 3 is mounted on a carrier 1 and a dummy substrate 4 is mounted on a carrier 2, and the product substrate 3 is mounted on the carrier 1.
The polishing time when the product substrate 4 is mounted on the carrier 2 is 1
Polish two batches. As the dummy substrate 4, a substrate having a film quality higher than the film quality of the product substrate and having no unevenness is selected. In place of the dummy substrate 4, a processed product of a ceramic material or a quartz material may be used.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体基板や液晶
基板等よりなる基板の表面を平坦化処理するための化学
機械研磨(CMP)を行う基板の研磨方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for polishing a substrate which is subjected to chemical mechanical polishing (CMP) for flattening the surface of a substrate such as a semiconductor substrate or a liquid crystal substrate.
【0002】[0002]
【従来の技術】近年、半導体製造プロセスの高密度化、
微細化に伴い種々の微細加工技術が研究開発されてい
る。その中でも、化学機械研磨(以下CMPという)
は、層間絶縁膜の平坦化を行う必須技術である。2. Description of the Related Art In recent years, the densification of semiconductor manufacturing processes,
Along with the miniaturization, various fine processing techniques have been researched and developed. Among them, chemical mechanical polishing (hereinafter referred to as CMP)
Is an essential technique for planarizing the interlayer insulating film.
【0003】CMPに用いられる基板研磨装置は、図1
1のようなものであって、中心軸の回りに回転する円盤
状のプラテン(定盤)6とプラテン6を中心部で支持す
るプラテン軸7とプラテン6上に貼り付けられた独立気
泡型ポリウレタン樹脂や不織布等からなる研磨布(パッ
ド)5と基板3が装着された円板状のキャリア1とキャ
リア1を中心部で支持するキャリア軸8とコロイダルシ
リカを主成分とする研磨剤(スラリー)11を供給する
ための研磨剤供給装置10とを備え、キャリア1に装着
した基板3の表面を研磨布5に押しつける機械的研磨作
用と、加工中に供給した研磨剤(スラリー)11の化学
的研磨作用により、基板表面の凹凸をなくすよう研磨す
ることを特徴としている。A substrate polishing apparatus used for CMP is shown in FIG.
1, a disk-shaped platen (surface plate) 6 that rotates around a central axis, a platen shaft 7 that supports the platen 6 at the central portion, and a closed-cell polyurethane attached on the platen 6. A polishing cloth (pad) 5 made of resin or non-woven fabric, a disk-shaped carrier 1 on which a substrate 3 is mounted, a carrier shaft 8 for supporting the carrier 1 at its center, and an abrasive (slurry) containing colloidal silica as a main component. And a mechanical polishing action of pressing the surface of the substrate 3 mounted on the carrier 1 against the polishing cloth 5, and a chemical action of the polishing agent (slurry) 11 supplied during processing. The polishing operation is characterized by polishing so as to eliminate the irregularities on the substrate surface.
【0004】更に本発明者が使用する基板研磨装置は他
のキャリア2を有しているため、1枚の研磨布5上でキ
ャリア1、2が同時に2枚の基板3、4を研磨すること
ができる。故に1バッチ2枚処理となり、スループット
を大幅に短縮できる。Further, since the substrate polishing apparatus used by the present inventor has another carrier 2, the carriers 1, 2 can simultaneously polish two substrates 3, 4 on one polishing cloth 5. You can Therefore, one batch is processed with two sheets, and the throughput can be significantly reduced.
【0005】さて、半導体基板の多層配線構造は図12
に示すようにシリコン基板21上にパターン形成した金
属配線22の上に層間絶縁膜23を積層し、その層間絶
縁膜23の凹凸部分24を基板研磨装置で平坦化研磨す
る組み合わせで構成されている。Now, the multilayer wiring structure of the semiconductor substrate is shown in FIG.
As shown in FIG. 3, the interlayer insulating film 23 is laminated on the patterned metal wiring 22 on the silicon substrate 21, and the uneven portion 24 of the interlayer insulating film 23 is flattened and polished by the substrate polishing apparatus. .
【0006】特にCMPによる層間絶縁膜の平坦化加工
において、初期膜厚25から規定の膜厚26に合わせ込
む研磨時間は、事前に金属配線なしの層間絶縁膜を積層
した凹凸なしの基板(以降、下地なしの基板)の研磨レー
ト測定より得られた研磨レートをR、初期膜厚25をH
i、規定の膜厚26をHo、層間膜段差における凹凸部
のパターン密度をKとしてParticularly, in the planarization process of the interlayer insulating film by CMP, the polishing time for adjusting the initial film thickness 25 to the prescribed film thickness 26 is such that the substrate having no unevenness (hereinafter referred to as a substrate without lamination of metal wiring) , R is the polishing rate obtained from the measurement of the polishing rate of the substrate (without substrate), and H is the initial film thickness 25.
i, the prescribed film thickness 26 is Ho, and the pattern density of the uneven portion in the step of the interlayer film is K
【0007】[0007]
【数1】 [Equation 1]
【0008】より導かれる。パターン密度Kは品種及び
配線層によって決定される定数である。It is derived from more. The pattern density K is a constant determined by the type and wiring layer.
【0009】ここで、図13に図11に示す1バッチ2
枚処理の基板研磨装置を用いた場合のロット処理方法を
示している。Here, one batch 2 shown in FIG. 11 is shown in FIG.
The lot processing method when using a substrate polishing apparatus for single wafer processing is shown.
【0010】研磨時間T1はキャリア1で研磨した下地
なしの基板3の研磨レートをR1、キャリア2で研磨し
た処理の下地なしの基板4の研磨レートをR2として、The polishing time T 1 is R 1 as the polishing rate of the baseless substrate 3 which is polished by the carrier 1 , and R 2 is the polishing rate of the substrate 4 which is not processed and is polished by the carrier 2.
【0011】[0011]
【数2】 [Equation 2]
【0012】より導かれ、1バッチ固定の研磨時間T1
で複数枚の基板の研磨を行う。Based on the above, the polishing time T 1 for one batch is fixed.
Then, a plurality of substrates are polished.
【0013】しかし、処理枚数が奇数であるロットを処
理する場合、最終バッチはキャリア1に装着した基板3
の1枚のみ研磨を行うが、1枚の研磨布上でキャリア
1、2で研磨を行った前バッチと同じ研磨時間で処理す
ると、規定の膜厚に合わせ込むことができない。なぜな
ら、基板1枚研磨した場合の研磨布と基板2枚同時に研
磨した場合の研磨布の目詰まりや研磨熱による研磨布の
表面の劣化の度合いが異なるため、研磨レートが異なる
ためである。更に研磨布表面の劣化度合は研磨する基板
の凸部の比率によって単位面積当りの荷重が変化するた
め品種によって異なる。However, when processing a lot having an odd number of processed sheets, the final batch is the substrate 3 mounted on the carrier 1.
However, if the polishing is performed with the same polishing time as that of the previous batch in which the carriers 1 and 2 are used to polish one polishing cloth, it is impossible to adjust the film thickness to a specified value. This is because the polishing rate when polishing one substrate is different from the degree of deterioration of the surface of the polishing cloth due to clogging of the polishing cloth and polishing heat when polishing two substrates at the same time. Further, the degree of deterioration of the surface of the polishing cloth varies depending on the type because the load per unit area changes depending on the ratio of the convex portions of the substrate to be polished.
【0014】そこで、1枚処理を行う場合、キャリア1
のみで下地なしの基板の研磨レート測定を行い、研磨時
間T2を研磨レート測定から得られた研磨レートをR3と
して(数1)に挿入することによってTherefore, when processing one sheet, the carrier 1
By measuring the polishing rate of the substrate without the base with only the polishing time T 2 and inserting the polishing rate obtained from the polishing rate measurement as R 3 in (Equation 1)
【0015】[0015]
【数3】 [Equation 3]
【0016】より求め、得られた研磨時間T2で研磨を
行わなければならなかった。It was necessary to carry out polishing for the obtained polishing time T 2 obtained from the above.
【0017】[0017]
【発明が解決しようとする課題】しかしながら、最終バ
ッチの1枚のみ規定の膜厚に合わせ込む研磨時間を変更
するとなると、ロット処理を分割しなければならない。
又、研磨時間を決定するためにキャリア1とキャリア2
で同時に研磨する下地なしの基板の研磨レートの測定と
キャリア1のみで研磨する下地なしの基板の研磨レート
の測定が必要である為、装置の処理能力に影響を及ぼ
す。However, if the polishing time for changing the thickness of only one of the final batch to the specified film thickness is changed, the lot process must be divided.
Also, carrier 1 and carrier 2 are used to determine the polishing time.
Therefore, it is necessary to measure the polishing rate of the substrate without a base which is simultaneously polished in 1. and the polishing rate of the substrate without a base in which only the carrier 1 is polished, which affects the processing capability of the apparatus.
【0018】そこで、本発明では基板の研磨方法とし
て、1枚の研磨布で2枚以上の基板を同時に研磨し、端
数の基板を研磨する場合、同じ研磨時間で端数の基板の
研磨量を1バッチ処理時に全ての基板を表面の凹凸部の
段差を有する基板とした場合の研磨量と同一にすること
によって、端数の基板でも規定の膜厚に合わせ込む方法
を確立することにある。Therefore, in the present invention, as a method for polishing a substrate, when two or more substrates are simultaneously polished with one polishing cloth and a fractional substrate is polished, the fractional amount of the substrate is polished by 1 in the same polishing time. The purpose is to establish a method for adjusting the film thickness to a specified film even for a fractional substrate by making all substrates the same as the polishing amount in the case of using the substrate having unevenness on the surface during the batch processing.
【0019】[0019]
【課題を解決するための手段】上記課題を解決するため
に、本発明の基板研磨方法は、定盤上に取り付けられた
研磨布を第1の回転速度で回転させ、前記研磨布の表面
上に研磨剤を供給し、基板を第2の回転速度で回転させ
ながら前記研磨布の表面に押圧することにより前記基板
の表面の凹凸部の段差を緩和し、規定の膜厚にする基板
研磨方法で、1バッチ処理時に前記研磨布上で複数の基
板を研磨し、端数の基板においては別の表面の凹凸部の
段差の無い基板と共に研磨する。In order to solve the above-mentioned problems, the substrate polishing method of the present invention comprises rotating a polishing cloth attached on a surface plate at a first rotation speed so that the surface of the polishing cloth is rotated. And a polishing agent is supplied to the substrate and the substrate is rotated at a second rotation speed to press the substrate against the surface of the polishing cloth to alleviate the unevenness of the uneven portion on the surface of the substrate to obtain a prescribed film thickness. Then, a plurality of substrates are polished on the polishing cloth at the time of one batch processing, and in the case of a fractional substrate, it is also polished together with a substrate having no step on the uneven portion of another surface.
【0020】上記基板の研磨方法において、1バッチ処
理時に一方の基板を表面の凹凸部の段差を有する基板、
他方の基板を前記一方の基板の膜より硬度の高い膜を基
板上に堆積し、かつ表面の凹凸部の段差の無い基板を組
み合わせる。In the above method for polishing a substrate, one substrate is treated with a step having uneven portions on the surface during one batch processing,
For the other substrate, a film having a hardness higher than that of the one substrate is deposited on the substrate, and substrates having no unevenness on the surface are combined.
【0021】この方法により、前記一方の基板の研磨量
を同じ研磨時間で1バッチ処理時に全ての基板を表面の
凹凸部の段差を有する基板とした場合の研磨量と同一に
することができる。According to this method, the polishing amount of the one substrate can be made equal to the polishing amount when all the substrates are substrates having steps of uneven portions on the surface during one batch processing in the same polishing time.
【0022】上記基板の研磨方法において、一方の基板
を表面の凹凸部の段差を有する基板、他方の基板を前記
一方の基板の膜質より硬度の高い膜質を有する複数の成
膜を基板上に順次堆積し、かつ表面の凹凸部の段差の無
い基板を組み合わせる。In the above method for polishing a substrate, one substrate is sequentially formed with a step having unevenness on the surface, and the other substrate is sequentially formed with a plurality of films having a film quality higher than that of the one substrate. Substrates that are deposited and have no unevenness on the surface are combined.
【0023】この方法により、前記一方の基板の研磨量
を同じ研磨時間で1バッチ処理時に全ての基板を表面の
凹凸部の段差を有する基板とした場合の研磨量と同一に
することができる。By this method, the polishing amount of the one substrate can be made equal to the polishing amount when all the substrates are substrates having steps of uneven portions on the surface during one batch processing in the same polishing time.
【0024】上記基板の研磨方法において、一方の基板
を表面の凹凸部の段差を有する基板、他方の基板をセラ
ミック材や石英材の加工品で前記凹凸部の段差を有する
基板上の膜よりも硬度の高い材料を組み合わせる。In the above method of polishing a substrate, one of the substrates is a substrate having a step of unevenness on the surface, and the other substrate is a processed product of a ceramic material or a quartz material, and is more preferable than a film on the substrate having the step of the unevenness. Combine materials with high hardness.
【0025】この方法により、前記一方の基板の研磨量
を同じ研磨時間で1バッチ処理時に全ての基板を表面の
凹凸部の段差を有する基板とした場合の研磨量と同一に
することができる。By this method, the polishing amount of the one substrate can be made equal to the polishing amount when all the substrates are substrates having steps of uneven portions on the surface during one batch processing in the same polishing time.
【0026】上記基板の研磨方法において、研磨布の温
度をバッチ毎に制御可能にする機構をもち、一方の基板
を表面の凹凸部の段差を有する基板、他方の基板を前記
一方の基板の膜質と同質の膜質で、かつ表面の凹凸部の
段差の無い基板を組み合わせる場合に研磨布の温度を下
げる。In the above method for polishing a substrate, the substrate has a mechanism for controlling the temperature of the polishing cloth for each batch, and one substrate has a step having unevenness on the surface, and the other substrate has a film quality of the one substrate. The temperature of the polishing cloth is lowered when a substrate having the same film quality as the above and having no unevenness on the surface is combined.
【0027】この方法により、前記一方の基板の研磨量
を同じ研磨時間で1バッチ処理時に全ての基板を表面の
凹凸部の段差を有する基板とした場合の研磨量と同一に
することができる。By this method, the polishing amount of the one substrate can be made equal to the polishing amount when all the substrates are substrates having steps of uneven portions on the surface during one batch processing in the same polishing time.
【0028】[0028]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しつつ、詳細に説明する。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
【0029】(第1の実施形態)図1(A)は、本発明
の第1の実施形態に係るCMPに使用される基板研磨装
置の処理枚数が偶数であるロットの処理方法を示してお
り、研磨布5上でキャリア1、キャリア2が同時に2枚
の基板3、基板4を研磨することができる。(First Embodiment) FIG. 1A shows a processing method for a lot in which the number of processed substrates of a substrate polishing apparatus used for CMP according to the first embodiment of the present invention is an even number. The carrier 1 and the carrier 2 can simultaneously polish the two substrates 3 and 4 on the polishing cloth 5.
【0030】図1(B)は処理枚数が奇数であるロット
の最終バッチの処理方法を示している。FIG. 1B shows a processing method of the final batch of a lot having an odd number of processed sheets.
【0031】ロットは凹凸部の段差有りの基板(以降、
製品基板)であり、基板の被研磨面はP-TEOS(Pla
sma-CVD TEOS)膜であり、本発明においては表面の成膜
状態が一定であり、成膜状態によって研磨レートの変動
が少ないものとする。A lot is a substrate having a step on the uneven portion (hereinafter,
Product substrate), and the surface to be polished of the substrate is P-TEOS (Pla
sma-CVD TEOS) film, and in the present invention, the film formation state on the surface is constant, and the fluctuation of the polishing rate is small depending on the film formation state.
【0032】1バッチ2枚処理の基板研磨装置を用いた
場合のロットの処理方法を説明する。A method of processing lots using a substrate polishing apparatus for processing two wafers in one batch will be described.
【0033】まず、キャリア1、キャリア2を用いて、
事前に金属配線なしの層間絶縁膜を積層した凹凸なしの
基板(以降、下地なしの基板)の研磨レート測定を実施す
る。First, using carrier 1 and carrier 2,
The polishing rate of a substrate without irregularities (hereinafter, a substrate without a base) in which an interlayer insulating film without metal wiring is laminated is measured in advance.
【0034】次に、研磨時間Tを研磨レート測定結果か
ら得られたキャリア1の研磨レートをR1、キャリア2
の研磨レートをR2、ロットの初期膜厚25の平均値を
Hi、規定の膜厚26をHo、層間膜段差24における
凹凸部のパターン密度をKとして、Next, the polishing time T, the polishing rate of the carrier 1 obtained from the polishing rate measurement results are R 1 , the carrier 2 is
Where R 2 is the polishing rate, Hi is the average value of the initial film thickness 25 of the lot, Ho is the prescribed film thickness 26, and K is the pattern density of the irregularities in the interlayer film step 24.
【0035】[0035]
【数4】 [Equation 4]
【0036】より、導く。パターン密度Kは品種及び配
線層によって決定される定数である。From the above, we will guide. The pattern density K is a constant determined by the type and wiring layer.
【0037】処理枚数が偶数であるロットを処理する場
合、(数4)より得られた研磨時間Tを固定して、1バ
ッチ2枚ずつ研磨を行っていく。When processing a lot having an even number of processed sheets, the polishing time T obtained from (Equation 4) is fixed, and polishing is performed two by one batch.
【0038】処理枚数が奇数であるロットを処理する場
合、最終バッチは製品基板1枚となる為、キャリア1に
製品基板、キャリア2にダミーの基板を装着して、前バ
ッチと同じく(数4)より得られた研磨時間Tで1バッ
チ2枚の研磨を行う。When processing a lot having an odd number of processed sheets, the final batch is one product substrate. Therefore, the product substrate is mounted on the carrier 1 and the dummy substrate is mounted on the carrier 2, and the same process as in the previous batch (equation 4) is performed. 2 pieces of 1 batch are polished in the polishing time T obtained from the above.
【0039】ダミーの基板の選定においては製品基板と
同じ段差をもつ基板を用意すればよいが、コスト面から
難しいのは当然であり、下記の実施の形態より、シリコ
ン窒化(SiN)膜でかつ下地なしの基板又はHDP
(High Density Plasma)-SiO2膜でかつ下地なし
の基板を選択している。In selecting the dummy substrate, it is sufficient to prepare a substrate having the same step as the product substrate, but it is naturally difficult from the viewpoint of cost, and according to the following embodiment, a silicon nitride (SiN) film and Substrate without base or HDP
(High Density Plasma) -A substrate with a SiO 2 film and no underlayer is selected.
【0040】本実施の形態におけるキャリア2に使用す
るダミーの基板の種類を図2に示している。本実施の形
態では、実験1としてキャリア1に製品基板、キャリア
2に製品基板を装着して研磨し、実験2としてキャリア
1に製品基板、キャリア2にシリコン基板、実験3とし
てキャリア1に製品基板、キャリア2に製品と同質の膜
質であるP-TEOS(Plasma-CVD TEOS)膜でかつ下地
なしの基板を装着して研磨し、実験4としてキャリア1
に製品基板、キャリア2にシリコン窒化(SiN)膜を
装着して研磨し、実験5としてキャリア1に製品基板、
キャリア2にHDP(High Density Plasma)-SiO
2膜を装着して研磨している。FIG. 2 shows the types of dummy substrates used for the carrier 2 in the present embodiment. In the present embodiment, the product substrate is mounted on the carrier 1 and the product substrate is mounted on the carrier 2 as Experiment 1 and polished, and in Experiment 2, the product substrate is carrier 1, the carrier 2 is silicon substrate, and the carrier 1 is product substrate in Experiment 3. , Carrier 2 is a P-TEOS (Plasma-CVD TEOS) film having the same film quality as the product, and a baseless substrate is mounted and polished.
To the product substrate, carrier 2 with a silicon nitride (SiN) film attached and polished.
Carrier 2 HDP (High Density Plasma) -SiO
Two films are attached and polished.
【0041】図3に実験1の場合のキャリア1で処理し
た製品基板の研磨量を基準にして、各実験のキャリア1
で処理した製品基板の研磨量の比較結果を示している。FIG. 3 shows the carrier 1 of each experiment based on the polishing amount of the product substrate treated with the carrier 1 in the case of experiment 1.
The comparison result of the polishing amount of the product substrate processed in 1. is shown.
【0042】図3の結果からいえば、キャリア1に製品
基板、キャリア2に製品基板を装着して研磨した状態に
近いのは、ダミーの基板として、キャリア2にシリコン
窒化(SiN)膜またはHDP(High Density Plas
ma)-SiO2膜となることが分かる。According to the results shown in FIG. 3, the state in which the product substrate is mounted on the carrier 1 and the product substrate is mounted on the carrier 2 is similar to the polished state. As a dummy substrate, a silicon nitride (SiN) film or HDP is formed on the carrier 2. (High Density Plas
It turns out that it becomes a ma) -SiO 2 film.
【0043】図2に各成膜の物性比較を示しているが、
エッチングレートが低い程、膜質の硬度が高いことを示
し、硬度の高いシリコン窒化(SiN)膜またはHDP
(High Density Plasma)-SiO2膜をダミーの基板
にすることによってキャリア1に製品基板、キャリア2
に製品基板を装着して研磨した状態に近くすることがで
きるとも言える。FIG. 2 shows a comparison of the physical properties of each film formation.
The lower the etching rate, the higher the hardness of the film, and the higher the hardness of the silicon nitride (SiN) film or HDP.
(High Density Plasma) -By using the SiO 2 film as a dummy substrate, the carrier 1 is the product substrate, the carrier 2 is the carrier 2.
It can also be said that the product substrate can be attached to the product to make it close to the polished state.
【0044】ここで、本発明者達は凹凸部の段差のある
基板の処理方法において、研磨布の表面温度と相関して
いることを示唆するものとして、以下のような注目すべ
き事実に気がついた。Here, the inventors of the present invention have noticed the following remarkable facts as a suggestion that they are correlated with the surface temperature of the polishing cloth in the method of treating a substrate having unevenness in steps. It was
【0045】図5は、図4に示すように赤外線温度計を
研磨布の上に配置し、各実験の研磨布の表面温度を非接
触で測定した結果を示しており、横軸に研磨時間、縦軸
に研磨布の表面温度を表している。FIG. 5 shows the results of non-contact measurement of the surface temperature of the polishing cloth of each experiment in which an infrared thermometer was placed on the polishing cloth as shown in FIG. 4, and the horizontal axis indicates the polishing time. The vertical axis represents the surface temperature of the polishing cloth.
【0046】図5より、実験2のキャリア1に製品基
板、キャリア2にシリコン基板を装着して研磨した研磨
布の温度曲線、実験3のキャリア1に製品基板、キャリ
ア2に製品と同質の膜質であるP-TEOS(Plasma-CV
D TEOS)膜を装着して研磨した研磨布の温度曲線は、実
験1のキャリア1に製品基板、キャリア2に製品基板を
装着して研磨した研磨布の温度曲線と比較して、常に高
い。又、実験4のキャリア1に製品基板、キャリア2に
シリコン窒化(SiN)膜を装着して研磨した研磨布の
温度曲線、実験5のキャリア1に製品基板、キャリア2
にHDP(HighDensity Plasma)-SiO2膜を装着し
て研磨した研磨布の温度曲線は実験1のキャリア1に製
品基板、キャリア2に製品基板を装着して研磨した研磨
布の温度曲線とほぼ類似していることが分かる。From FIG. 5, the temperature curve of the polishing cloth obtained by mounting the product substrate on the carrier 1 and the silicon substrate on the carrier 2 in Experiment 2, the product substrate in Carrier 1 in Experiment 3, and the same film quality as the product in Carrier 2 were obtained. P-TEOS (Plasma-CV
The temperature curve of the polishing cloth with the D TEOS) film attached and polished is always higher than the temperature curve of the polishing cloth with the product substrate mounted on the carrier 1 and the product substrate mounted on the carrier 2 in Experiment 1. Further, the temperature curve of the polishing cloth obtained by mounting the product substrate on the carrier 1 of Experiment 4 and the silicon nitride (SiN) film on the carrier 2, and the product substrate and carrier 2 on the carrier 1 of Experiment 5
The temperature curve of the polishing cloth with the HDP (High Density Plasma) -SiO 2 film attached to and polished is almost similar to the temperature curve of the polishing cloth with the product substrate attached to carrier 1 and the product substrate attached to carrier 2 in Experiment 1. You can see that
【0047】このような温度差が生じる理由は基板を2
枚同時に処理した場合において、基板の膜の種類によっ
て研磨布の目詰まりの度合いが異なるためで、研磨布の
温度が高いことは研磨レートが高いことを示している。The reason why such a temperature difference occurs is that the substrate is
This is because the degree of clogging of the polishing cloth varies depending on the type of the film on the substrate when the wafers are processed at the same time, and a high polishing cloth temperature indicates a high polishing rate.
【0048】ゆえに、温度曲線の面からも、キャリア1
に製品基板、キャリア2に製品基板を装着して研磨した
状態に近いのは、キャリア2のダミーの基板として、シ
リコン窒化(SiN)膜またはHDP(High Density
Plasma)-SiO2膜となる。Therefore, in terms of the temperature curve, the carrier 1
The product substrate, and the product substrate mounted on the carrier 2 are closer to the polished state as a dummy substrate of the carrier 2 as a silicon nitride (SiN) film or HDP (High Density).
Plasma) -SiO 2 film.
【0049】本発明の知見として、キャリア1に製品基
板、キャリア2にダミーの基板とした場合の研磨布の表
面温度をキャリア1、2共に、製品基板2枚同時に処理
した場合の研磨布の表面温度と同じになるようにすれ
ば、研磨レートが同じになり、キャリア1に製品基板、
キャリア2にダミーの基板として処理した場合の基板の
研磨量とキャリア1、2共、製品基板2枚同時に処理し
た場合の研磨量とは同じになることが言える。上記知見
に基づけば、製品基板の非研磨面がP−TEOS(Plas
ma-CVD TEOS)膜以外の膜、例えば層間絶縁膜で代表的
なBPSG膜についても同じことが言え、実施の形態と
同じ実験を行えば、容易にダミーの基板は選定できる。As a finding of the present invention, the surface temperature of the polishing cloth when the carrier 1 is a product substrate and the carrier 2 is a dummy substrate is the surface of the polishing cloth when the two carrier substrates 1 and 2 are processed at the same time. If the temperature is the same, the polishing rate will be the same, and the carrier 1 will have the product substrate,
It can be said that the polishing amount of the substrate when the carrier 2 is processed as a dummy substrate is the same as the polishing amount when the two carrier substrates 1 and 2 are simultaneously processed. Based on the above knowledge, the non-polished surface of the product substrate is P-TEOS (Plas
The same can be said for films other than the ma-CVD TEOS) film, for example, a typical BPSG film as an interlayer insulating film, and a dummy substrate can be easily selected by performing the same experiment as the embodiment.
【0050】本発明を適用することで、1バッチで2枚
以上の複数の基板を同時に研磨を行う場合においても、
上記実施形態と同じ効果が得られる。By applying the present invention, even when two or more substrates are simultaneously polished in one batch,
The same effect as the above embodiment can be obtained.
【0051】(第2の実施形態)図5より実験4、実験
5とも、研磨の終了付近で急激な温度上昇が見受けられ
るが、これは膜が無くなり、シリコン基板が表われたこ
とを意味している。よりキャリア1に製品基板、キャリ
ア2に製品基板を装着して研磨した状態に近づける為に
は、研磨時間に応じてシリコン窒化(SiN)膜または
HDP(High Density Plasma)-SiO2膜を多く堆
積する必要がある。しかしながら、CVD装置で膜厚を
多く堆積することはパーティクルの多発を招くため、困
難である。(Second Embodiment) From FIGS. 5A and 5B, in Experiments 4 and 5, a sharp temperature rise was found near the end of polishing, which means that the film disappeared and the silicon substrate appeared. ing. In order to attach the product substrate to the carrier 1 and the product substrate to the carrier 2 and bring them closer to the polished state, a large amount of silicon nitride (SiN) film or HDP (High Density Plasma) -SiO 2 film is deposited according to the polishing time. There is a need to. However, it is difficult to deposit a large amount of film with a CVD apparatus because it causes many particles.
【0052】そこで、第2の実施形態として、製品基板
の研磨時間が150秒以上の場合、実験6として、キャ
リア2に使用するダミーの基板として、シリコン窒化
(SiN)膜200nmの上にHDP(High Density
Plasma)-SiO2膜700nmを堆積するといった異
種の膜厚を組み合わせてみた。Therefore, as the second embodiment, when the polishing time of the product substrate is 150 seconds or more, as Experiment 6, a dummy substrate used for the carrier 2 is formed on the silicon nitride (SiN) film 200 nm with HDP ( High Density
Plasma) -SiO 2 film of 700 nm was deposited in combination with different film thicknesses.
【0053】図6に実験1の場合のキャリア1で処理し
た製品基板の研磨量を基準にして、実験6のキャリア1
で処理した製品基板の研磨量の比較結果を示している。FIG. 6 shows the carrier 1 of the experiment 6 based on the polishing amount of the product substrate treated with the carrier 1 of the experiment 1.
The comparison result of the polishing amount of the product substrate processed in 1. is shown.
【0054】図6より、キャリア1に製品基板、キャリ
ア2にシリコン窒化(SiN)膜とHDP(High Den
sity Plasma)-SiO2膜を組み合わせた基板を装着し
て研磨した場合の製品基板の研磨量は、キャリア1に製
品基板、キャリア2に製品基板を装着して研磨した場合
の研磨量に対し近い値が得られ、研磨布の温度特性曲線
も図7に示すようにほぼ同一の曲線が得られた。キャリ
ア2に使用するダミーの基板として、異種の膜を組み合
わせることによって、研磨時間が長くても、同様な効果
が得られることが分かった。From FIG. 6, carrier 1 is a product substrate, carrier 2 is a silicon nitride (SiN) film and HDP (high density).
The polishing amount of the product substrate when the substrate combined with the sity plasma) -SiO 2 film is mounted and polished is closer to the polishing amount when the product substrate is mounted on the carrier 1 and the product substrate is mounted on the carrier 2 and polished. The values were obtained, and the temperature characteristic curve of the polishing cloth was almost the same as shown in FIG. It was found that the same effect can be obtained by combining different types of films as the dummy substrate used for the carrier 2 even if the polishing time is long.
【0055】(第3の実施形態)本発明はキャリア2に
使用するダミーの基板を、第1、第2の実施形態として
シリコン基板を使用したが、第3の実施形態として石英
材又はセラミック材の加工品でシリコン基板と同じ形状
(直径200mm,厚み725±25mm)を組み合わ
せた。(Third Embodiment) In the present invention, the dummy substrate used for the carrier 2 and the silicon substrate are used in the first and second embodiments, but the quartz material or the ceramic material is used in the third embodiment. The same shape (200 mm in diameter, 725 ± 25 mm in thickness) as the silicon substrate was combined in the processed product.
【0056】本実施の形態では、実験1としてキャリア
1に製品基板、キャリア2に製品基板を装着して研磨
し、実験7としてキャリア1に製品基板、キャリア2に
石英材の加工品を装着して研磨し、実験8としてキャリ
ア1に製品基板、キャリア2にセラミック材の加工品を
装着して研磨している。In this embodiment, in Experiment 1, the product substrate is mounted on the carrier 1 and the product substrate is mounted on the carrier 2 and polished. In Experiment 7, the product substrate is mounted on the carrier 1 and the processed quartz material is mounted on the carrier 2. In Experiment 8, the carrier substrate 1 is mounted with a product substrate, and the carrier 2 is mounted with a ceramic material processed product and polished.
【0057】図8に実験1の場合のキャリア1で処理し
た製品基板の研磨量を基準にして、実験7、実験8のキ
ャリア1で処理した製品基板の研磨量の比較結果を示し
ている。FIG. 8 shows the comparison results of the polishing amounts of the product substrates processed by the carrier 1 in Experiments 7 and 8 with the polishing amount of the product substrate processed by the carrier 1 in Experiment 1 as a reference.
【0058】図8より、キャリア1に製品基板、キャリ
ア2に石英材の加工品を装着して研磨した場合とキャリ
ア1に製品基板、キャリア2にセラミック材の加工品を
装着して研磨した場合の製品基板の研磨量は、キャリア
1に製品基板、キャリア2に製品基板を装着して研磨し
た場合の研磨量に対し近い値が得られることが分かる。From FIG. 8, the case where the product substrate is mounted on the carrier 1, the processed product of quartz material is mounted on the carrier 2, and the carrier substrate is mounted on the carrier 1 and the processed product of ceramic material is mounted on the carrier 2 are polished. It can be seen that the polishing amount of the product substrate is similar to the polishing amount when the product substrate is mounted on the carrier 1 and the product substrate is mounted on the carrier 2.
【0059】キャリア2に使用するダミーの基板の代わ
りとして、石英材又はセラミック材の加工品を組み合わ
せることによって、同様な効果が得られることが分かっ
た。It has been found that a similar effect can be obtained by combining a processed product of a quartz material or a ceramic material as a substitute for the dummy substrate used for the carrier 2.
【0060】しかしながら、石英材の加工品は透過光セ
ンサーを通過してしまうため、透過光センサーの有無に
よって使い分ける必要がある。又、石英材又はセラミッ
クの加工品を使用すれば、再利用が可能のため第1、第
2の実施形態で使用したダミーの基板を削減できる。However, since the processed quartz material passes through the transmitted light sensor, it is necessary to use it properly depending on the presence or absence of the transmitted light sensor. Further, if a processed product of quartz material or ceramic is used, it is possible to reuse the dummy substrate used in the first and second embodiments.
【0061】(第4の実施形態)図9は、本発明の第4
の実施形態に係るCMPに使用される基板研磨装置であ
る。本実施形態に係る基板研磨装置は研磨布5上でキャ
リア1、キャリア2が同時に2枚の基板3、基板4を研
磨することができ、研磨布を貼り付けるプラテン6(定
盤)の温度を変更することによって研磨布の温度をバッ
チ毎に制御する。(Fourth Embodiment) FIG. 9 shows a fourth embodiment of the present invention.
It is a substrate polishing apparatus used for CMP according to the embodiment. The substrate polishing apparatus according to the present embodiment allows the carrier 1 and the carrier 2 to polish two substrates 3 and 4 at the same time on the polishing cloth 5, and the temperature of the platen 6 (platen) to which the polishing cloth is attached is controlled. The temperature of the polishing cloth is controlled for each batch by changing the temperature.
【0062】循環配管14は純水を循環供給するための
配管であり、プラテン6の内部に流路接続されている。
循環配管14には、ポンプ15、チラー16、管内温度
計17がそれぞれ介設されている。ポンプはプラテン6
の内部に向けて、純水を循環配管14を介して送液し、
チラー16は循環配管14を流れる約23℃の純水を例
えば約0℃から約20℃の範囲内まで冷却し、管内温度
計17はチラー16で冷却された純水の温度を測定す
る。The circulation pipe 14 is a pipe for circulating and supplying pure water, and is connected to the inside of the platen 6 by a flow path.
A pump 15, a chiller 16, and a pipe thermometer 17 are provided in the circulation pipe 14, respectively. Pump is platen 6
Pure water is sent through the circulation pipe 14 toward the inside of the
The chiller 16 cools the pure water of about 23 ° C. flowing through the circulation pipe 14 to within the range of, for example, about 0 ° C. to about 20 ° C., and the pipe thermometer 17 measures the temperature of the pure water cooled by the chiller 16.
【0063】基板研磨装置の制御部の内部に組み込まれ
た配管温度の制御部18は、管内温度計17、ポンプ1
5、チラー16と電気的に接続され、管内温度計17に
よる測定に基づく信号を受信し、ポンプ15、チラー1
6に制御信号を送信する。The pipe temperature control unit 18 incorporated in the control unit of the substrate polishing apparatus includes a pipe thermometer 17 and a pump 1.
5, electrically connected to the chiller 16, receives a signal based on the measurement by the in-tube thermometer 17, and pump 15, chiller 1
6. Send control signal to 6.
【0064】次に第4の実施形態の基板研磨装置の研磨
シーケンスを説明する。まず、処理枚数が奇数であるロ
ットの最終バッチの情報を装置に教え込ませる。最終バ
ッチにはキャリア1に製品の基板、キャリア2に製品の
基板の被研磨面と同質の膜質で、かつ下地なしの基板を
装着させる。本実施形態での基板の被研磨面はP−TE
OS(Plasma-CVD TEOS)膜であり、本発明においては
表面の成膜状態が一定であり、成膜状態によって研磨レ
ートの変動が少ないものとする。Next, the polishing sequence of the substrate polishing apparatus of the fourth embodiment will be described. First, the apparatus is taught the information of the final batch of the lot having an odd number of processed sheets. In the final batch, the carrier 1 is loaded with the substrate of the product, and the carrier 2 is loaded with the substrate of the same film quality as the surface to be polished of the substrate of the product and having no base. In the present embodiment, the surface to be polished of the substrate is P-TE.
It is an OS (Plasma-CVD TEOS) film, and in the present invention, the film formation state on the surface is constant, and the fluctuation of the polishing rate is small depending on the film formation state.
【0065】次に研磨が開始されると、ポンプ15を作
動させてプラテン6に向けて純水を循環供給し、チラー
16より循環供給される23℃の純水を20度まで冷却
し、管内温度計17によって測定された結果を基にフィ
ードバック制御を行い、純水の温度を一定に保つことに
よって、プラテン6の温度を一定に保つ。When polishing is next started, the pump 15 is operated to circulate and supply pure water toward the platen 6, and the pure water of 23 ° C. circulated and supplied from the chiller 16 is cooled to 20 ° C. Feedback control is performed based on the result measured by the thermometer 17, and the temperature of the pure water is kept constant, so that the temperature of the platen 6 is kept constant.
【0066】最終バッチの前バッチが終了した際、チラ
ー16の温度を強制的に下げ、管内温度計が安定したの
を確認した後、最終バッチの処理が行われる。図8の結
果より、実験1のキャリア1に製品基板、キャリア2に
製品基板を装着して研磨した研磨布の温度曲線と、実験
2のキャリア1に製品基板、キャリア2に製品と同質の
膜質であるTEOS膜でかつ下地なしの基板研磨布の表
面温度の温度差が4度あることから、チラー16の温度
はプラテン6から研磨布5への熱効率を考慮して20度
より6〜8度下げる必要がある。When the previous batch of the final batch is completed, the temperature of the chiller 16 is forcibly lowered, and after it is confirmed that the in-tube thermometer is stable, the final batch is processed. From the results of FIG. 8, the temperature curve of the polishing cloth obtained by mounting the product substrate on the carrier 1 and the product substrate on the carrier 2 in Experiment 1 and the temperature curve of the polishing cloth on the carrier 1 of Experiment 2 and the same film quality as the product on the carrier 2 of Experiment 2 are shown. Since the temperature difference of the surface temperature of the TEOS film which is a TEOS film and has no base is 4 degrees, the temperature of the chiller 16 is 6 to 8 degrees from 20 degrees in consideration of the thermal efficiency from the platen 6 to the polishing cloth 5. Need to lower.
【0067】図10に第4の実施形態における基板研磨
装置を使用して、25枚連続処理した際のCMP後膜厚
推移を示している。横軸に処理した基板の番号、縦軸に
CMP後の膜厚及び循環配管14の純水の温度を表して
いる。最終バッチで番号25の基板を処理しており、循
環配管の純水の温度を下げて、CMP後の規定の膜厚1
000nm±200nm内に入っていることが分かる。FIG. 10 shows the transition of the film thickness after CMP when 25 substrates were continuously processed by using the substrate polishing apparatus of the fourth embodiment. The abscissa represents the number of the processed substrate, and the ordinate represents the film thickness after CMP and the temperature of pure water in the circulation pipe 14. The substrate of No. 25 is processed in the final batch, and the temperature of the pure water in the circulation pipe is lowered to the specified film thickness after CMP.
It can be seen that it is within 000 nm ± 200 nm.
【0068】研磨布の温度を下げることによって研磨レ
ートを低下させ、キャリア1に製品基板、キャリア2に
製品の基板の被研磨面と同質の膜質で、かつ下地なしの
基板とした場合の製品基板の研磨量をキャリア1、2共
に、製品基板2枚同時に処理した場合の研磨量と同一に
することができる。When the polishing rate is lowered by lowering the temperature of the polishing cloth, the carrier substrate is a product substrate, and the carrier 2 is a substrate having the same film quality as the surface to be polished of the product substrate and no substrate. The polishing amount can be the same as the polishing amount when two carrier substrates 1 and 2 are processed at the same time.
【0069】本発明を適用することで、1バッチで2枚
以上の複数の基板を同時に研磨を行う場合においても、
上記実施形態と同じ効果が得られる。By applying the present invention, even when two or more substrates are simultaneously polished in one batch,
The same effect as the above embodiment can be obtained.
【0070】[0070]
【発明の効果】以上、説明したように本発明によれば、
1枚の研磨布で2枚以上の基板を同時に研磨し、端数の
基板を研磨する場合、一方の基板を凹凸部の段差を有す
る基板、他方の基板を凹凸部の段差の無い基板と共に組
み合わせることによって、同じ研磨時間で、端数の基板
でも規定の膜厚に合わせ込むことが可能である。As described above, according to the present invention,
When polishing two or more substrates at the same time with one polishing cloth and polishing a fractional number of substrates, one substrate should be combined with a substrate having unevenness steps and the other substrate should be combined with a substrate having no unevenness steps. Thus, it is possible to adjust the film thickness to a specified value even with a fractional substrate with the same polishing time.
【0071】凹凸部の段差の無い基板の代わりにセラミ
ック材や石英材の加工品としても、同様な効果が得ら
れ、基板の削減からも有効である。The same effect can be obtained by using a ceramic material or a quartz material as a processed product instead of a substrate having no unevenness in the uneven portion, which is also effective in reducing the number of substrates.
【0072】又、研磨布の温度を下げることによっても
同様な効果が得られる。The same effect can be obtained by lowering the temperature of the polishing cloth.
【図1】本実施形態の処理枚数が奇数であるロットの最
終バッチの処理運用を説明する図FIG. 1 is a diagram illustrating a processing operation of a final batch of a lot having an odd number of processed sheets according to the present embodiment.
【図2】本発明の第1の実施形態におけるダミー基板の
種類を示す図FIG. 2 is a diagram showing types of dummy substrates according to the first embodiment of the present invention.
【図3】本発明の第1の実施形態における片側使用基板
の違いによる製品基板の研磨量の比較を示す図FIG. 3 is a diagram showing a comparison of polishing amounts of product substrates according to the difference in one-side used substrate in the first embodiment of the present invention.
【図4】本発明の第1の実施形態における赤外線温度計
による研磨布の表面温度測定を概略的に示す図FIG. 4 is a diagram schematically showing surface temperature measurement of a polishing cloth by an infrared thermometer according to the first embodiment of the present invention.
【図5】本発明の第1の実施形態における片側使用基板
の違いによる研磨布の表面温度特性を示す図FIG. 5 is a diagram showing the surface temperature characteristics of the polishing pad according to the difference in the substrates used on one side in the first embodiment of the present invention.
【図6】本発明の第2の実施形態における片側使用基板
の違いによる製品基板の研磨量の比較を示す図FIG. 6 is a diagram showing a comparison of the polishing amounts of product substrates according to the difference in the substrates used on one side in the second embodiment of the present invention.
【図7】本発明の第2の実施形態における片側使用基板
の違いによる研磨布の表面温度特性を示す図FIG. 7 is a diagram showing a surface temperature characteristic of a polishing cloth according to a difference in a substrate used on one side according to a second embodiment of the present invention.
【図8】本発明の第3の実施形態における片側使用材料
の違いによる製品基板の研磨量の比較を示す図FIG. 8 is a diagram showing a comparison of polishing amounts of product substrates according to the difference in material used on one side in the third embodiment of the present invention.
【図9】本発明の第4の実施形態における基板研磨装置
の図FIG. 9 is a diagram of a substrate polishing apparatus according to a fourth embodiment of the present invention.
【図10】本発明の第4の実施形態における基板研磨装
置を使用して、25枚処理した際のCMP後膜厚推移を
示す図FIG. 10 is a view showing a film thickness transition after CMP when 25 substrates are processed by using the substrate polishing apparatus according to the fourth embodiment of the present invention.
【図11】CMPに使用される基板研磨装置による基板
の研磨状態を概略的に示す斜視図FIG. 11 is a perspective view schematically showing a polishing state of a substrate by a substrate polishing apparatus used for CMP.
【図12】研磨対象となる膜構造の一例を示す図FIG. 12 is a diagram showing an example of a film structure to be polished.
【図13】従来の処理枚数が奇数であるロットの最終バ
ッチの処理運用を説明する図FIG. 13 is a diagram for explaining the conventional processing operation of the final batch of a lot with an odd number of processed sheets.
1 キャリア 2 キャリア 3 基板 4 基板 5 研磨布(パッド) 6 プラテン(定盤) 7 プラテン軸 8 キャリア軸 9 キャリア軸 10 研磨剤供給装置 11 研磨剤(スラリー) 12 赤外線温度計 13 赤外線温度計の測定箇所 14 循環配管 15 循環ポンプ 16 チラー 17 管内温度計 18 制御部 21 シリコン基板 22 金属配線 23 層間絶縁膜 24 層間膜段差 25 初期膜厚 26 規定の膜厚 1 career 2 career 3 substrates 4 substrates 5 Polishing cloth (pad) 6 Platen (surface plate) 7 Platen shaft 8 carrier axes 9 Carrier axis 10 Abrasive supply device 11 Abrasive (slurry) 12 infrared thermometer 13 Measurement points of infrared thermometer 14 Circulation piping 15 Circulation pump 16 chillers 17 In-pipe thermometer 18 Control unit 21 Silicon substrate 22 Metal wiring 23 Interlayer insulation film 24 Interlayer film step 25 Initial film thickness 26 Specified film thickness
───────────────────────────────────────────────────── フロントページの続き (72)発明者 池ノ内 勝行 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 3C049 AA07 BA02 CA01 CB01 CB03 3C058 AA07 BA02 CB01 CB03 DA17 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Katsuyuki Ikenouchi 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Sangyo Co., Ltd. F term (reference) 3C049 AA07 BA02 CA01 CB01 CB03 3C058 AA07 BA02 CB01 CB03 DA17
Claims (5)
回転速度で回転させ、前記研磨布の表面上に研磨剤を供
給し、基板を第2の回転速度で回転させながら前記研磨
布の表面に押圧することにより前記基板の表面の凹凸部
の段差を緩和し、規定の膜厚にする基板研磨方法であっ
て、1バッチ処理時に前記研磨布上で複数の基板を研磨
し、端数の基板においては別の表面の凹凸部の段差の無
い基板と共に研磨することを特徴とする基板研磨方法。1. A polishing cloth mounted on a surface plate is rotated at a first rotation speed, an abrasive is supplied onto the surface of the polishing cloth, and the substrate is rotated at a second rotation speed to perform the polishing. A method of polishing a substrate by pressing against the surface of a cloth to reduce the unevenness of the uneven portion of the surface of the substrate to a prescribed film thickness, and polishing a plurality of substrates on the polishing cloth during one batch processing, A method of polishing a substrate, characterized in that, in the case of a fractional substrate, the substrate is polished together with another substrate having no unevenness on the uneven surface.
1バッチ処理時に一方の基板を表面の凹凸部の段差を有
する基板、他方の基板を前記一方の基板の膜より硬度の
高い膜を基板上に堆積し、かつ表面の凹凸部の段差の無
い基板を組み合わせることによって、前記一方の基板の
研磨量を同じ研磨時間で1バッチ処理時に全ての基板を
表面の凹凸部の段差を有する基板とした場合の研磨量と
同一にすることを特徴とする基板研磨方法。2. The substrate polishing method according to claim 1, wherein
A substrate having one surface having a step of unevenness on the surface during one batch processing, the other substrate having a film having a hardness higher than that of the one substrate deposited on the substrate and having no unevenness of the surface unevenness The substrate is characterized in that the polishing amount of one of the substrates is the same as the polishing amount when all the substrates are substrates having steps of uneven portions on the surface during one batch processing in the same polishing time. Polishing method.
一方の基板を表面の凹凸部の段差を有する基板、他方の
基板を前記一方の基板の膜質より硬度の高い膜質を有す
る複数の異種の膜を基板上に順次堆積し、かつ表面の凹
凸部の段差の無い基板を組み合わせることによって、前
記一方の基板の研磨量を同じ研磨時間で1バッチ処理時
に全ての基板を表面の凹凸部の段差を有する基板とした
場合の研磨量と同一にすることを特徴とする基板研磨方
法。3. The substrate polishing method according to claim 1, wherein
One substrate is a substrate having a step of unevenness on the surface, the other substrate is sequentially deposited on the substrate a plurality of different types of film having a film quality higher than the film quality of the one substrate, and By combining the substrates having no step, the polishing amount of the one substrate can be made equal to the polishing amount when all the substrates are the substrates having the step of the uneven portion of the surface in one batch processing in the same polishing time. A characteristic substrate polishing method.
一方の基板を表面の凹凸部の段差を有する基板、他方の
基板をセラミック材や石英材の加工品で前記凹凸部の段
差を有する基板上の膜よりも硬度の高い材料を組み合わ
せることによって、前記一方の基板の研磨量を同じ研磨
時間で1バッチ処理時に全ての基板を表面の凹凸部の段
差を有する基板とした場合の研磨量と同一にすることを
特徴とする基板研磨方法。4. The substrate polishing method according to claim 1, wherein
By combining one substrate with a step having unevenness on the surface and the other substrate with a material having a hardness higher than that of a film on the substrate having the unevenness of the unevenness, which is a processed product of a ceramic material or a quartz material, A substrate polishing method, wherein the polishing amount of one substrate is set to be the same as the polishing amount when all substrates are substrates having steps of uneven portions on the surface during one batch processing with the same polishing time.
研磨布の温度をバッチ毎に制御可能にする機構をもち、
一方の基板を表面の凹凸部の段差を有する基板、他方の
基板を前記一方の基板の膜質と同質の膜質で、かつ表面
の凹凸部の段差の無い基板を組み合わせる場合に研磨布
の温度を下げることによって、前記一方の基板の研磨量
を同じ研磨時間で1バッチ処理時に全ての基板を表面の
凹凸部の段差を有する基板とした場合の研磨量と同一に
することを特徴とする基板研磨方法。5. The substrate polishing method according to claim 1, wherein
It has a mechanism to control the temperature of the polishing cloth for each batch.
The temperature of the polishing cloth is lowered when one substrate is combined with a substrate having unevenness on the surface, and the other substrate is combined with a film having the same film quality as that of the one substrate and having no unevenness on the surface unevenness. Accordingly, the polishing amount of the one substrate is made the same as the polishing amount when all the substrates are substrates having steps of uneven portions on the surface during one batch processing in the same polishing time. .
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|---|---|---|---|
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|---|---|---|---|
| JP2002049110A JP4165087B2 (en) | 2002-02-26 | 2002-02-26 | Substrate polishing method |
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| Publication Number | Publication Date |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7331843B2 (en) | 2006-03-07 | 2008-02-19 | Matsushita Electric Industrial Co., Ltd. | Substrate polishing method and method of manufacturing semiconductor device |
| WO2011152958A3 (en) * | 2010-06-03 | 2012-03-08 | Applied Materials, Inc. | Tuning of polishing process in multi-carrier head per platen polishing station |
| CN110640603A (en) * | 2019-09-17 | 2020-01-03 | 上海致领半导体科技发展有限公司 | A ceramic pressure plate of polishing machine with water cooling function |
-
2002
- 2002-02-26 JP JP2002049110A patent/JP4165087B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7331843B2 (en) | 2006-03-07 | 2008-02-19 | Matsushita Electric Industrial Co., Ltd. | Substrate polishing method and method of manufacturing semiconductor device |
| WO2011152958A3 (en) * | 2010-06-03 | 2012-03-08 | Applied Materials, Inc. | Tuning of polishing process in multi-carrier head per platen polishing station |
| CN110640603A (en) * | 2019-09-17 | 2020-01-03 | 上海致领半导体科技发展有限公司 | A ceramic pressure plate of polishing machine with water cooling function |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4165087B2 (en) | 2008-10-15 |
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