JP2003224155A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of superior mounting reliability that is connected by a flip chip connecting method, and a method for manufacturing it. <P>SOLUTION: A multilayer distributing board 1 comprises a plurality of metalized wiring layers 21 and a via hole conductor 22 at least on the surface and/or inside of a ceramic insulating substrate 19. A semiconductor element 7 provided with a connecting electrode 5 is mounted on the principal surface 2 of the multilayer distributing board 1. The metalized wiring layer 21 of the multilayer distributing board 1 is electrically connected to the connecting electrode 5 of the semiconductor element 7. A gap 9 between the multilayer distributing board 1 and the semiconductor element 7 is filled with a filler 11. In this semiconductor device constituted in such a manner that the pulse duty factor of an area of a void 23 in the principal surface 2 of the multilayer distributing board 1 where the filler 11 is applied is at least 8% or more. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor element mounted on the surface of a multilayer wiring board and a method for manufacturing the same, and more particularly to a semiconductor in which the semiconductor element and the multilayer wiring board are connected by a flip chip connection method. The present invention relates to a device and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, the innovation of packaging technology corresponding to the miniaturization and high density of electronic devices has been remarkable, and accordingly, semiconductor devices such as semiconductor devices including a semiconductor device and a multilayer wiring board on which the semiconductor device is mounted have a semiconductor device. Attention has been paid to a technology relating to the connection between the wiring board and the multilayer wiring board. In the semiconductor device, a flip chip connection method has been developed in which a semiconductor element is directly connected face-down to a multi-layer wiring substrate with a brazing material through a connection electrode in order to reduce the size, increase the number of pins, and increase the speed. .

Further, in this flip-chip connection method, in order to enhance the mounting reliability, a filler called underfill is filled in the gap between the semiconductor element and the multilayer wiring board and cured to reinforce it. .

[0004]

However, in such a semiconductor device, since the semiconductor element is formed of silicon (Si), the coefficient of thermal expansion thereof is about 3 × 10 ⁻⁶ /
On the other hand, the multilayer wiring board has a coefficient of thermal expansion of 7 to 15 × 10 ⁻⁶ / ° C. because an inorganic material such as a ceramic material or a glass ceramic material or an organic resin is used as an insulating substrate. The difference in thermal expansion coefficient between the semiconductor element and the multilayer wiring board is large.

As a result, when a semiconductor element is flip-chip connected to the surface of the above-mentioned multilayer wiring board, stress is generated by heat generated by the operation and stop of the semiconductor element. Even if the gap is filled with a filler to reinforce, the thermal stress causes peeling at the interface between the semiconductor element and the multilayer wiring board, thereby impairing the electrical connection state of the connection electrode. There was a problem.

Therefore, an object of the present invention is to provide a semiconductor device which is connected by a flip chip connection method and has excellent mounting reliability, and a manufacturing method thereof.

[0007]

The semiconductor device of the present invention comprises:
A multilayer wiring substrate having a plurality of metallized wiring layers and via-hole conductors on at least the surface and / or inside of the ceramic insulating substrate, and a semiconductor element provided with a connecting electrode is placed on the main surface of the multilayer wiring substrate. In a semiconductor device in which a metallized wiring layer of a wiring board is electrically connected to a connection electrode of the semiconductor element, and a filler is filled in a gap between the multilayer wiring board and the semiconductor element, at least the filler is The area occupancy of voids on the main surface of the applied multilayer wiring board is 8% or more.

According to this structure, the filler filled in the gap between the semiconductor element and the multilayer wiring board can penetrate into the void formed on the surface of the multilayer wiring board to form the anchor, and By setting the area occupation ratio of the voids to the area of the main surface of the multilayer wiring board to be 8% or more, the anchors formed by the filler are increased, and the adhesive strength between the semiconductor element and the multilayer wiring board can be increased.
As a result, it is possible to suppress cracks in the connecting electrode and the filler that are interposed between the semiconductor element and the multilayer wiring board. Thus, even if thermal stress or the like occurs at the interface between the semiconductor element and the multilayer wiring board, peeling can be prevented, the connection state of the connection electrode can be kept stable, and mounting reliability can be improved.

In the above semiconductor device, it is desirable that the average of the maximum diameters of voids is 3 μm or more. Thus, the average maximum diameter of the voids formed on the main surface of the multilayer wiring board is 3
When the thickness is at least μm, a large anchor can be formed on the surface of the multilayer wiring board, so that the adhesive strength between the semiconductor element and the multilayer wiring board can be further increased.

In the above semiconductor device, the surface roughness (Ra) of the portion of the multilayer wiring board excluding the voids is preferably 0.3 μm or more. By setting the surface roughness (Ra) of the multilayer wiring board to 0.3 μm or more together with the voids, the adhesive strength of the filler can be further increased.

In the above semiconductor device, it is desirable that voids having an average maximum diameter of 3 μm or more are formed only in the region of the multilayer wiring substrate to which the filler is applied. By forming a void having an average maximum diameter of 3 μm or more only in the region where the filler is applied, the adhesive strength between the semiconductor element and the multilayer wiring board can be increased, and the surface of the multilayer wiring board By reducing the voids other than the region to which the filler is applied, it is possible to enhance the substrate strength and moisture resistance of the multilayer wiring board and the semiconductor device using the multilayer wiring board, thus further improving the mounting reliability.

In the above semiconductor device, the semiconductor element and the multi-layer
5 × 10 thermal expansion coefficient difference with linear substrate ^-6/ C or above
In both cases, the area of the semiconductor element main surface is A₁, Multilayer wiring board
Area of the surface is A₃And when₁/ A₃≧ 0.02
Is desirable. Form a void on the main surface, as described above.
If it is a semiconductor device that uses a multilayer wiring board made of semiconductor,
The thermal expansion coefficient difference between the body element and the multilayer wiring board is large
Sometimes large strain is likely to occur along with thermal stress
Even with the above structure, mounting reliability can be improved.
It

In the above semiconductor device, the ceramic insulating substrate is preferably made of glass ceramics. Glass-ceramics alleviate the difference in thermal expansion between components and reduce the generated stress, so that high connection reliability can be obtained.

The method of manufacturing a semiconductor device according to the present invention comprises a step of forming a metallized wiring layer on the surface of a ceramic green sheet on which a via-hole conductor is formed, and a plurality of green sheets on which the metallized wiring layer is formed. A step of forming a body, a step of firing the laminated body under a predetermined atmosphere under temperature conditions to form a multilayer wiring board body,
A step of forming a multi-layered wiring board having voids on the surface of the multi-layered wiring board by performing a sandblasting treatment on the surface of the multi-layered wiring board body using alumina abrasive grains having a maximum particle size of 50 μm or less; A step of mounting a semiconductor element having a connecting electrode on the main surface of the multilayer wiring board,
And a step of filling a gap between the semiconductor element and the multilayer wiring board with a filler.

According to such a manufacturing method, in order to form the voids on the surface of the multilayer wiring board by using the sandblasting process, the conditions of the sandblasting process are changed so that the desired maximum diameter and area occupation ratio are obtained. Voids can be easily formed. Further, by using a mask, voids can be easily formed at any place on the multilayer wiring board.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION A face-up type ball grid array (BGA) which is one mode of a semiconductor device of the present invention.
Will be described in detail with reference to the schematic sectional view of FIG.

According to the semiconductor device of the present invention, the semiconductor element 7 having the connecting electrodes 5 arranged in a grid is mounted on the main surface 2 of the multilayer wiring board 1. Further, connection terminals 8 for secondary mounting on a mother board or the like are formed in a grid pattern on the side of the multilayer wiring board 1 opposite to the semiconductor element 7 mounting surface.

The multilayer wiring board 1 and the semiconductor element 7 are also provided.
A filler 11 is filled in the gap 9 between the multilayer wiring board 1 and the peripheral portion of the semiconductor element 7.
A fillet portion 17 is formed so as to spread like a hem over the main surface 2.

The multilayer wiring board 1 is a ceramic insulating board 1.
A metallized wiring layer 21 and a via-hole conductor 22 are formed on at least the main surface 2 of the metal layer 9.

According to the present invention, a plurality of voids 23 are formed on the main surface 2 of the multilayer wiring board 1 on which the semiconductor element 7 is mounted, and the voids 23 are formed with respect to the area of the main surface 2 of the multilayer wiring board 1. It is important that the area occupation rate is 8% or more. An anchor 25 is formed by partially infiltrating the filler 11 into the void 23.

The area occupancy of the voids is preferably 8 to 40% for the reason that the number of anchors 25 by the filler 11 is increased to increase the adhesive strength and the mechanical strength of the multilayer wiring board 1 is improved. Is 10 to 30
%, Especially 10 to 20 to maintain high mechanical strength
% Is more desirable.

The average maximum diameter of the voids 23 is 3 μm.
The average of the maximum diameters is preferably 3 to 50 μm for the reason that the above is preferable, and because the anchoring effect is further ensured and the substrate strength of the multilayer wiring board 1 is maintained high,
Furthermore, it is more desirable that the thickness is 10 to 30 μm.
The average maximum diameter of the voids 23 being 3 μm or more is a value obtained by measuring the maximum diameter of the voids 23 of each multilayer wiring board 1 and calculating the average.

The voids 23 having a maximum diameter of 3 μm or more are formed only in the region to which the filler 11 is applied, so that the adhesive strength with the semiconductor element 7 is increased and the multilayer wiring board 1 is formed. It is desirable to improve the substrate strength and moisture resistance of the.

The maximum depth of the void 23 is preferably 20 μm or less, which also enhances the anchoring effect of the anchor 25 formed by the filler 11 and at the same time maintains the substrate strength of the multilayer wiring substrate 1 at a high level. For reasons, furthermore, it is more desirable that this maximum depth is 5 to 15 μm.

Further, in the multilayer wiring board 1 to which the filler 11 is applied, it is possible to improve the adhesive strength of the filler 11 by increasing the contact area with the filler 11 together with the formation of the voids 23, so that the multilayer wiring board 1 can be improved. Surface roughness of 1 (Ra)
Is preferably 0.3 μm or more, and particularly preferably 0.6 to 1.5 μm.

Further, the difference in thermal expansion coefficient between the semiconductor element 7 and the multilayer wiring board 1 is 5 × 10 ⁻⁶ / ° C. or more, and particularly 7 to 13 ×.
In the case of a semiconductor device having a structure in the range of 10 ⁻⁶ / ° C., in which a large strain is likely to occur along with thermal stress during operation, the area of the main surface of the semiconductor element 7 is A ₁ , the main surface of the multilayer wiring substrate 1 is When the area of 2 is A ₃ , A ₁ / A ₃ ≧
0.02 is preferable, and 0.1 to 0.7 is particularly preferable.
If so, mounting reliability can be further improved.

In the semiconductor device of the present invention, the insulating substrate 19 constituting the multilayer wiring board 1 is made of alumina (Al ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), aluminum nitride (AlN), and glass. It may be any of electrically insulating materials such as ceramics that can be fired at low temperature such as ceramics. However, in order to reduce the difference in thermal expansion between components and reduce the generated stress, the insulating substrate 19 is made of glass ceramics or the like at a low temperature. It is preferably composed of fired ceramics.

In the semiconductor device in which the semiconductor element 7 is mounted on one main surface 2 of the multilayer wiring board 1, the size of the multilayer wiring board 1 is larger than the size of the semiconductor element 7 and the area ratio thereof is large. Therefore, the coefficient of thermal expansion of the semiconductor device is mainly determined by the coefficient of thermal expansion of the insulating substrate 19. Therefore, as the insulating substrate 19, in practice, it is necessary to enhance the mounting reliability when mounted on an external circuit substrate containing an organic resin.
It is desirable that the coefficient of thermal expansion at 40 to 400 ° C. is 8 × 10 ⁻⁶ / ° C. or more, particularly 9 × 10 ⁻⁶ / ° C. or more.

The Young's modulus of the insulating substrate 19 is 200M.
When it is Pa or less, particularly 150 MPa or less, the stress generated during use can be reduced.

The metallized wiring layer 21 formed on at least the surface of the multi-layer wiring board 1 may be made of tungsten (W), molybdenum (M) depending on the material of the insulating substrate 19.
o), copper (Cu), at least one conductor selected from the group of silver (Ag) can be selected and used, and alumina (Al ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), aluminum nitride For a ceramic mainly composed of (AlN), a conductor mainly containing tungsten (W) or molybdenum (Mo) is used, and in the case of a low temperature fired ceramic capable of firing at 1000 ° C. or lower, copper is used. A conductor mainly composed of (Cu) or silver (Ag) can be selected and used.

The semiconductor element 7 is made of silicon (Si), has a coefficient of thermal expansion of about 3 × 10 ⁻⁶ / ° C., and is encapsulated in the multilayer wiring board 1 by a desired thermosetting resin. The semiconductor element 7 installed therein is hermetically sealed by bonding a suitable lid to the main surface 2 of the multilayer wiring board 1.

Gap 9 between semiconductor element 7 and multilayer wiring board 1
The filler 11 to be filled in is preferably composed of an inorganic filler and a thermosetting resin.

As the thermosetting resin contained in the filler 11, for example, phenol resin, urea resin,
At least one selected from the group consisting of melamine resin, epoxy resin, unsaturated polyester resin, diallyl phthalate resin, polyimide resin, silicone resin, and polyurethane resin can be mentioned. Among these, at least one epoxy resin selected from the group of bisphenol epoxy resin, novolac epoxy resin, brominated epoxy resin, and alicyclic epoxy resin is particularly desirable.

As the inorganic filler added to the thermosetting resin in order to reduce the coefficient of thermal expansion of the filler 11,
Spherical particles are preferable, and the filling property in the narrow space of the gap 9 between the semiconductor element 7 and the multilayer wiring board 1 can be improved, and the occurrence of cracks due to defective filling in the filler 11 can be prevented.

Further, the spherical particles exhibit a good packing property when the corners are not substantially present on the surface of the particles because the friction between the particles is small. In particular, the spherical particles have an average aspect ratio (major axis / minor axis) of 1.2 or less, particularly 1.1.
And the average particle diameter depending on the long diameter is 0.3 to 20 μm,
Particularly, 1 to 10 μm is preferable from the viewpoint of filling property. When the average particle size is smaller than 0.3 μm, the viscosity of the filler 11 is low, the filling property is deteriorated, and voids are easily generated.
This is because if the average particle diameter exceeds 20 μm, it is difficult to fill the inorganic filler between the semiconductor element 7 and the multilayer wiring board 1, and it is easy for cracks to occur due to the occurrence of voids and nonuniformity of the filler 11. The inorganic filler used is preferably a crushed or spherical inorganic substance such as quartz glass, alumina, mica, zirconium silicate, lithium silicate and the like.

Further, the content of the inorganic filler in the filler 11 is appropriate to be 30 to 90% by volume, and the amount of the filler 11 is adjusted by adjusting the filler amount in the above range according to the Young's modulus of the resin used. The Young's modulus after curing can be controlled.

The semiconductor device of the present invention is generally mounted on an external circuit board. The external circuit board used here is made of a so-called printed circuit board, and is formed on the surface and / or inside of an insulating plate made of a material containing an organic resin such as glass / epoxy resin, glass / polyimide resin composite material, and aramid fiber. , Au, Al, Ni,
A conductor layer made of a metal such as Sn-Pb is adhered and formed, and the coefficient of thermal expansion is preferably in the range of 12 to 17 × 10 ^-6 / ° C.

Thus, the coefficient of thermal expansion is 12 to 17 × 1.
By using the external circuit board in the range of 0 ⁻⁶ / ° C., when the thermal expansion coefficients of the semiconductor element 7, the multilayer wiring board 1, and the external circuit board are α1, α2, and α5, α1 <α2 < The relationship of α5 can be satisfied, and since the warp shapes of the semiconductor element 7, the multilayer wiring board 1 and the external circuit board can be made close to each other, the mounting reliability of the semiconductor device can be improved.

Next, a method of manufacturing the multilayer wiring board 1 used in the semiconductor device of the present invention will be described with reference to the process chart of FIG.

First, as shown in FIG. 2A, the ceramic green sheet 31 is prepared by adding an organic binder and a plasticizer to a predetermined ceramic composition, and then applying a doctor blade method, a rolling method, a pressing method or the like. About 5 by the molding method
It is formed into a sheet shape of 0 to 500 μm.

Next, as shown in FIG. 2B, a through hole having a diameter of 50 to 200 μm is formed in the ceramic green sheet 31 by using a processing method such as laser, microdrill, punching or the like, and a conductor paste is formed therein. To fill the via hole conductor 35.

Next, as shown in FIG. 2C, a metallized wiring layer 37 is formed on the surface of the ceramic green sheet 31. The metallized wiring layer 37 may be formed by a printing method or the like using a conductor paste containing a metal conductor powder for forming the above-mentioned via-hole conductor 35. In particular, the metallized wiring layer 37 has a width of 75.
μm or less, especially 50 μm or less, and metallized wiring layer 3
It is desirable to use a metal foil for forming fine wiring with a pitch of 7 being 100 μm or less, particularly 75 μm or less.

As for the metallized wiring layer 37 made of such a metal foil, a method of forming a desired circuit by a known photo-etching method or the like after the metal foil is adhered to the surface of the ceramic green sheet 31 is known. However, in such a method, the ceramic green sheet 31 is deteriorated by the etching solution, and thus it is desirable to form it by the transfer method.

Next, as shown in FIG. 2D, a plurality of green sheets 31a to 31c obtained in the same manner are laminated and pressure-bonded to form a laminated body, and the laminated body is further subjected to a predetermined atmosphere. By firing under temperature conditions, the multilayer wiring board element body 39 is formed.

The firing may be ordinary firing, but in order to form the multilayer wiring board element 39 having high dimensional accuracy,
It is also possible to install a constraining sheet having almost no shrinkage at the time of firing on the upper and lower surfaces of the laminated body and perform simultaneous firing. In this case, in the laminated body, the multilayer wiring board element body 39 that is mainly contracted only in the laminating direction is formed.

Next, as shown in FIG. 2E, at least one selected from the group consisting of ultrasonic cleaning, polishing, water jet, chemical blasting, sand blasting, wet blasting, and drive blasting is performed on the multilayer wiring board body 39. Method is used. According to the manufacturing method of the multilayer wiring board 1 of the present invention, in the above processing method, the predetermined void 23 can be efficiently formed on the surface of the multilayer wiring board body 39 by the sandblasting machine 38. By performing such processing, the multilayer wiring board 1 having the desired voids 23 formed on the surface can be easily formed.

The abrasive grains used for the sandblasting treatment are preferably ceramic powders having a hardness enough to roughly grind the surface of the multilayer wiring board body 39. In particular, alumina abrasive grains are preferable in terms of particle size adjustment, purity and price. It is preferably used.

The alumina abrasive grains used here have an average grain size in the range of 50 μm or less, and in particular, in order to form a void having a diameter of 3 μm or more on the surface of the multilayer wiring board body 39, this alumina is used. The average grain size of the abrasive grains is 9 to 20.
μm, preferably 13 to 16 μm.

Further, as the condition of the sandblast treatment, the treatment time, pressure and the like are adjusted. By this sandblasting, the low-softening component such as glass on the surface of the ceramic insulating substrate is selectively shaved to form voids.

Multilayer wiring board 1 produced in this way
The semiconductor element 7 is mounted on the main surface 2 of the above to form a semiconductor device. In the semiconductor element 7, connection electrodes 5 for making electrical connection with the multilayer wiring board 1 are formed in a grid pattern on the main surface thereof, and the connection electrodes 5 are connected to the main surface 2 of the multilayer wiring board 1.
The metallized wiring layer 21 formed on the substrate is brought into contact with the metallized wiring layer 21 to be heated and, if necessary, pressurized to be connected.

Next, the filler 11 is filled in the gap 9 between the semiconductor element 7 thus formed and the multilayer wiring board 1. At this time, the filler 11 also penetrates into the voids 23 formed on the main surface 2 of the multilayer wiring board 1 to form the anchors 25, so that the multilayer wiring board 1 and the semiconductor element 7 are firmly bonded.

[0052]

EXAMPLE A multilayer wiring board used in the semiconductor device of the present invention was manufactured as follows.

Al ₂ O ₃ powder with SiO ₂ , MgO, CaO
3% by mass in total of the composition (A), SiO ₂
78 mass%, Li ₂ O 10 mass%, Al ₂ O ₃ 4 mass%, K ₂ O 4 mass%, P ₂ O ₅ 2 mass%, Na ₂ O 2 mass%.
50% by mass of glass powder having the composition of 50% by mass and mixed with forsterite (50% by mass), the composition (B) is molded into a sheet by the doctor blade method, and then, with respect to the sheet of the composition (A). Is formed by printing or filling a metallized wiring layer and a via-hole conductor using a tungsten paste and a copper paste for the composition (B) sheet, and then 1600 ° C. for the composition (A). The composition (B) was fired at 900 ° C. to produce a multilayer wiring board body, and the main surface, which is the outermost surface of the board, was sandblasted to obtain a grain size of # 10.
Alumina abrasive grains of 00 (maximum diameter 50 μm) were sprayed under the conditions shown in Table 2 to form voids having various void area occupancy rates and their diameters. In addition, the surface roughness (Ra) after the sandblast treatment was measured. Adjustment is possible also by the size of the abrasive grains. Further, the metallized wiring layer on the surface of this multilayer wiring board was plated with Ni.

Then, a ball of high melting point solder (Sn: Pb weight ratio = 10: 90) having a diameter of 0.5 mm is used as a low melting point solder (Sn: Pb weight ratio = 63 :) in the connection terminal on the lower surface of the multilayer wiring board. 37) and the multilayer wiring board was produced. The dimensions of the manufactured multilayer wiring board are 22 mm in length × 14 mm in width × 0.9 mm in thickness.

On the other hand, it is made of Si and has a thermal expansion coefficient of 3 × 10 ⁻⁶ / ° C. at 40 to 400 ° C. and a size of 12 mm in length × 12 mm in width. A flip chip type semiconductor element is prepared, the semiconductor element is mounted on a metallized wiring layer which is a land portion of the multilayer wiring board, and the solder bump is melted by heating to 150 ° C. to melt the semiconductor element into the multilayer wiring board. Implemented in.

Thereafter, a filler consisting of 50% by volume of bisphenol epoxy resin and 50% by volume of spherical alumina powder having an average particle diameter of 5 μm is injected between the semiconductor element and the multilayer wiring substrate by a dispenser, and the multilayer wiring substrate is obtained. After filling inside the void formed on the main surface of
The thermosetting resin was cured by holding it in the dryer for 2 hours to manufacture a semiconductor device. Table 1 shows the results of measuring the coefficient of thermal expansion of the ceramics (A) and (B) at 50 to 400 ° C.

[0057]

[Table 1]

The following evaluation was performed on the above semiconductor device.

The heat cycle test was conducted at -65 ° C. in the atmosphere.
The test sample is held for 30 minutes in a high-temperature bath controlled at 150 ° C and 150 ° C, respectively.
Repeated for 00 cycles. Then, every 100 cycles, the peeling of the interface was confirmed by the appearance inspection by the ultrasonic flaw detector and the microscope, and the number of cycles until the peeling occurs is shown in Table 2.

In the pressure cooker test, 20 samples were prepared for each sample, and these were heated at 121 ° C. under 2 atmospheres.
16 for high temperature, high humidity and high pressure equipment controlled to 100% humidity
I put it in for 8 hours. After that, peeling was confirmed by an appearance inspection of the wiring board and an ultrasonic flaw detector, and the number of samples in which peeling was observed is shown in Table 2.

As for the substrate breaking load, the load at the time of breaking is shown in Table 2 by using an autograph of the three-point bending strength with the groove forming surface of the package wiring board having the void as a tensile surface.

[0062]

[Table 2]

As is clear from the results of Table 2, the difference in thermal expansion coefficient between the insulating substrate and the semiconductor element is 4.4 × 10 ⁻⁶ /
C. Alumina of 0.degree. C. was used to make the void area occupancy rate 20%. In No. 2, the breaking load was large and the number of cycles in the thermal cycle test was 3000.

On the other hand, even if alumina was used, the sample area number of the voids was 5%. In No. 1, the number of cycles in the heat cycle test was as low as 1900.

When glass ceramics having a thermal expansion difference of 7.4.times.10.sup.- ⁶ / .degree. C. with the semiconductor element was used as the insulating substrate, the sample area number of voids was 8% or more. Four
In Nos. 16 to 16, even if a void was formed on the surface of the multilayer wiring board, the breaking load was 7 kgf or more, the number of cycles leading to the breaking in the thermal cycle test was 2000 or more, and the breaking was also small in the pressure cooker test. .

In particular, Sample No. 10 having a void occupation area of 10 to 20%, a maximum void diameter of 10 to 30 μm, and a surface roughness (Ra) of 0.8 to 1.5 μm. 5-7, 12-1
In No. 4, the breaking load was 11 kgf or more, and the number of cycles in the heat cycle test was 2200 or more, and extremely excellent mounting reliability was obtained.

On the other hand, in the sample No. in which the void occupying area was 5%. 3, the number of cycles in the heat cycle test is 1
It stayed at 500 times. Further, peeling was observed in all the samples in the pressure cooker test.

[0068]

As described above, according to the semiconductor device of the present invention, by making the area occupancy of the voids formed on the surface of the multilayer wiring substrate used in the flip chip bonding method 8% or more, the filler The number of anchors formed by the method is increased, and the adhesive strength between the semiconductor element and the multilayer wiring board can be increased. As a result, it is possible to suppress cracks in the connecting electrode and the filler that are interposed between the semiconductor element and the multilayer wiring board.

Further, even if thermal stress or the like occurs at the interface between the semiconductor element and the multilayer wiring board, the filling rate can be prevented from peeling, and thus the connection state of the connection electrode can be kept stable, so that the mounting reliability is improved. Can be improved.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a BGA type semiconductor device of the present invention.

FIG. 2 is a process drawing for explaining the method for manufacturing a multilayer wiring board according to the present invention.

[Explanation of symbols]

1 Multilayer wiring board 2 main surface 5 connection electrodes 7 Semiconductor element 9 gap 11 Filling agent 15 surface 19 Insulation board 21, 37 Metallized wiring layer 22,35 Via hole conductor 23 void

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yasuhide Minmin             Kyocera Co., Ltd. 1-4 Yamashita Town, Kokubun City, Kagoshima Prefecture             Shikisha Research Institute F-term (reference) 5F061 AA01 BA03 CA05

Claims (7)

[Claims] 1. A multilayer wiring board having a plurality of metallized wiring layers and via-hole conductors on at least the surface and / or inside of a ceramic insulating substrate, and a semiconductor element having a connecting electrode on the main surface of the multilayer wiring board. A semiconductor device in which a metallized wiring layer of the multilayer wiring board and the connection electrodes of the semiconductor element are electrically connected, and a gap is filled between the multilayer wiring board and the semiconductor element with a filler. , The area occupancy of voids on the main surface of the multilayer wiring board coated with at least the filler is 8%
A semiconductor device having the above. 2. The semiconductor device according to claim 1, wherein the average of the maximum diameters of the voids is 3 μm or more. 3. The semiconductor device according to claim 1, wherein a surface roughness (Ra) of a portion of the multilayer wiring board excluding the void is 0.3 μm or more. 4. The semiconductor device according to claim 1, wherein voids having a diameter of 3 μm or more are formed only in a region of the multilayer wiring board to which the filler is applied. 5. The thermal expansion coefficient difference between the semiconductor element and the multilayer wiring board is 5 × 10 ⁻⁶ / ° C. or more, the area of the main surface of the semiconductor element is A ₁ , and the area of the main surface of the multilayer wiring board is A ₃ and when the semiconductor device according to any one of claims 1 to 4, characterized in that the a ₁ / a ₃ ≧ 0.02. 6. The semiconductor device according to claim 1, wherein the insulating substrate is made of glass ceramics. 7. A step of forming a metallized wiring layer on the surface of a ceramic green sheet having a via-hole conductor formed thereon, a step of laminating a plurality of green sheets having the metallized wiring layer formed thereon to form a laminate, A step of forming a multilayer wiring board body by firing the laminated body under a temperature condition under a predetermined atmosphere, and using alumina abrasive grains having a maximum particle size of 50 μm or less on the surface of the multilayer wiring board body. A step of forming a multi-layered wiring board having voids formed on the surface of the multi-layered wiring board by performing a sandblasting process, and a step of mounting a semiconductor element having a connecting electrode on the main surface of the multi-layered wiring board. And a step of filling a gap between the semiconductor element and the multilayer wiring board with a filler.