JP2003051427A - Capacitor sheet and method for manufacturing the same, substrate with built-in capacitor, and semiconductor device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] An electrical connection for utilizing a capacitor;
Provided is a capacitor sheet in which the electrical connection between the front and back of the sheet is independent, and the adverse effect of via inductance is eliminated. SOLUTION: A laminate sheet including at least one set of a laminate in which a dielectric layer is sandwiched between a power supply layer electrode and a ground layer electrode, and penetrates the dielectric layer, the power supply layer electrode and the ground layer electrode. A through conductor for front / back connection that is formed in a through hole, is insulated between the power supply layer electrode and the grounding layer electrode inside by an insulating wall, and electrically connects front and back of the laminate sheet; A capacitor sheet is formed in a region where only one of the electrode and the ground layer electrode is arranged, and includes a capacitor through conductor electrically connected to the power supply layer electrode or the ground layer electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor sheet, a method for manufacturing the same, a circuit board, and a semiconductor device,
Particularly, the present invention relates to improvement of a capacitor sheet structure suitable for mounting a semiconductor on a wiring board such as a mother board or a daughter board.

[0002]

2. Description of the Related Art In recent years, digitalization of circuits has progressed in electronic equipment, and the speed of information processing, miniaturization, and multi-functional integration are remarkable. Along with this, circuit boards are required to have high-density wiring accommodation and high-density component mounting in order to cope with the increasing number of semiconductor parts.

In response to the demand for high-density wiring accommodation, a multilayer wiring board having an all-layer IVH structure, a build-up wiring board, and the like have recently been developed and put into practical use. In addition, for higher density of component mounting, BGA of semiconductor package,
With the progress of CSP, it has become possible to reduce the mounting area and significantly reduce the component spacing. Then, in order to further increase the density of component mounting, a technique for forming a bypass capacitor, which is indispensable for semiconductor operation, inside the substrate has been developed.

For example, Japanese Laid-Open Patent Publication No. 5-36857 discloses that
The bypass capacitor formed of the first conductor electrode layer, the second conductor electrode layer, and the dielectric layer sandwiched between these two conductor electrode layers is made of silicon (Si) or aluminum nitride (AlN). ) And the like, and a multilayer wiring layer including a wiring layer and an insulating layer is further laminated thereon. According to it, since the semiconductor chip mounted on the surface of the laminated substrate and the bypass capacitor of the inner layer are connected through the via, unlike the conventional one in which the chip capacitor is surface mounted, the chip is mounted on the surface of the substrate. The area occupied by the capacitor and the wiring area required for connection are unnecessary. Therefore, it is said that the degree of freedom of arrangement and wiring of mounted components is significantly improved, and high-density mounting can be realized.

In recent years, with the increase in the speed and capacity of integrated circuits such as ICs and LSIs, the frequencies of signals used have been increasing. Due to these, switching noise generated in the package in which the integrated circuit is mounted has become a problem as a cause of malfunction.

Conventionally used high-speed, large-capacity LS
The I package uses a multi-layer structure in which power layers and ground layers are alternately formed in order to maintain its electrical characteristics. Further, a large number of chip capacitors are surface-mounted as decoupling capacitors around and around the LSI of the package substrate.

On the other hand, for the purpose of low power consumption, there is a tendency to operate the CPU with a low voltage and a large current, and the power supply becomes insufficient at the time of starting up the CPU, resulting in a problem of operability. In the conventional example, a large-capacity electrolytic capacitor is formed around the LSI in order to stabilize the power supply at the time of rising.

[0008]

As described above, incorporating a capacitor in a substrate is a very effective means for high-density mounting. However, since there is a wiring layer directly below the component mounting surface and the capacitor layer is formed below that, the capacitor is connected via a via that passes through several insulating layers, and the power supply For the purpose of stabilization, there is concern that the inductance of the via may have an adverse effect.

The present invention provides a structure of a capacitor sheet in which the electrical connection for utilizing a capacitor and the electrical connection on the front and back of the sheet are independent, and the adverse effect of the inductance of the via is eliminated, and a manufacturing method thereof. With the goal. Another object is to provide a capacitor-embedded substrate using the capacitor sheet and a semiconductor device.

[0010]

A capacitor sheet of the present invention comprises a laminate sheet including at least one laminate having a dielectric layer sandwiched between a power layer electrode and a ground layer electrode,
The dielectric layer, the power supply layer electrode and the ground layer electrode is formed in a through hole that penetrates, the power supply layer electrode and the ground layer electrode inside is insulated by an insulating wall, Front and back connecting through conductors for electrically connecting the front and back, and the power supply layer electrode, or formed in a region in which only one of the ground layer electrode is arranged, electrically connected to the power supply layer electrode or the ground layer electrode, respectively. And a connected capacitor through conductor.

According to this structure, the electrical connection for utilizing the capacitor and the electrical connection for the front and back of the seat can be made independent. The number of the above-mentioned laminated bodies is usually 2 to
Although it is about 100, it can be 100 or more as required.

The method of manufacturing a capacitor sheet according to the present invention is
A method of manufacturing a capacitor sheet having the above structure,
The step of forming the front and back connecting through conductors, the step of forming a large diameter through hole in the laminate sheet, the step of filling the large diameter through hole with an insulator, the insulator is filled A step of forming a small diameter through hole in the through hole,
Providing a through conductor in the small diameter through hole.

The capacitor-embedded substrate of the present invention is a capacitor-embedded substrate in which the capacitor sheets having the above-mentioned structure are laminated, and the front and back connecting through conductors are provided between the printed wiring boards laminated on both sides of the capacitor sheet. And the power supply layer electrode and the ground layer electrode of the capacitor sheet are connected by the capacitor through conductor.

According to the above construction, it is possible to increase the capacity of power supply by using the multilayer laminated capacitor. Further, by arranging the multilayer capacitor by dividing it into a predetermined capacity, it is possible to cope with various functions. Furthermore, since it is possible to embed a capacitor in any layer, it is possible to form the capacitor layer in the layer immediately below the mounted component, in other words, in the outermost surface layer of the board, so via connection for connecting to the capacitor is possible. Can be the shortest. As a result, the influence of the inductance of the via can be suppressed to the minimum, and the power supply can be stabilized more effectively. Further, by providing a via that passes through the capacitor layer and is connected to the lower layer thereof, it becomes possible to perform wiring connection with a high degree of freedom in the inner layer, so that the design becomes simple.

The semiconductor device of the present invention comprises: a resin multilayer substrate having a signal wiring layer formed on the surface and inside thereof; a capacitor sheet having the above-mentioned structure installed and connected in the resin multilayer substrate; And a semiconductor chip mounted by flip-chip mounting. Alternatively, the semiconductor chip carrier may be mounted on the resin multilayer substrate instead of the semiconductor chip.

Further, the semiconductor device of the present invention includes a resin multilayer substrate having a signal wiring layer formed on the surface and inside thereof, a capacitor sheet having the above-mentioned configuration installed and connected on the resin multilayer substrate, and the capacitor sheet. And a semiconductor chip flip-chip mounted thereon. Alternatively, instead of the semiconductor chip, a semiconductor chip carrier mounted on the capacitor sheet may be provided.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. Examples of the capacitor sheet that can be used in the present invention include a laminated capacitor made of ceramic green sheets, a laminated capacitor made of film lamination, and a laminated capacitor made by a vacuum process such as sputtering or CVD.

(Embodiment 1) FIG. 1 is a sectional view showing a structure of a capacitor sheet according to Embodiment 1 of the present invention. This capacitor sheet is formed by laminating a dielectric layer 1 and a laminate of counter electrodes 2a and 2b in multiple layers. One of the counter electrodes 2a and 2b is used as a power layer electrode and the other is used as a ground layer electrode.

Through holes are formed to penetrate the dielectric layer 1 and the counter electrodes 2a and 2b in order to electrically connect the front and back of the multilayer laminate. The through hole is provided with a through-hole conductor 4 which is insulated from the opposing electrodes 2a and 2b inside by the insulating wall 3. The through-hole conductor 4 is formed by metal plating. Further, in order to electrically connect the plurality of counter electrodes 2a or 2b to each other, a through hole penetrating the dielectric layer 1 and the counter electrode 2a or 2b is formed in a region where the counter electrodes 2a and 2b are not opposed to each other. Has been formed.
The through hole is provided with a through through-hole conductor 4a or 4b.

With the above structure, a capacitor can be used by using the through through-hole conductors 4a and 4b, and the through through-hole conductor 4 can pass an electric signal on the front and back sides independently of the capacitor. it can.

(Second Embodiment) FIG. 2 is a sectional view showing the structure of a capacitor sheet according to a second embodiment of the present invention. The basic structure is similar to that of the capacitor sheet of FIG.

In order to electrically connect the front and back of the multi-layered laminate, the internal counter electrodes 2a and 2 are provided in through holes formed through the dielectric layer 1 and the counter electrodes 2a and 2b.
A through-through-hole conductor 4 is provided, which is insulated from the surface b by an insulating wall 3. In the present embodiment, the structure for electrically connecting a plurality of counter electrodes 2a or 2b is different from that of the first embodiment. That is, in the region where the counter electrodes 2a and 2b do not face each other, the through-via conductor 5a or 5b is provided in the through hole formed through the dielectric layer 1 and the counter electrode 2a or 2b. The through via conductors 5a and 5b are formed of a conductive paste.

With the above structure, the through via conductors 5a and 5
The capacitor can be used by using b, and the through through-hole conductor 4 can pass the electric signals on the front and back sides independently of the capacitor.

(Third Embodiment) FIG. 3 is a sectional view showing a structure of a capacitor sheet according to a third embodiment of the present invention. The basic structure is similar to that of the capacitor sheet of FIG.

The present embodiment differs from the first embodiment in the structure for electrically connecting the front and back surfaces of the multilayer laminate. That is, the through-via conductor 5 insulated from the internal counter electrodes 2a and 2b by the insulating wall 3 is provided in the through hole formed through the dielectric layer 1 and the counter electrodes 2a and 2b. . Further, in order to electrically connect the plurality of counter electrodes 2a or 2b to each other, it is formed by penetrating the dielectric layer 1 and the counter electrode 2a or 2b in a region where the counter electrodes 2a and 2b are not opposed to each other. A through-hole through-hole conductor 4a or 4b is provided in the through-hole.

With the above structure, a capacitor can be utilized by using the through-hole conductors 4a and 4b, and the through-via conductor 5 can pass an electric signal on the front and back sides independently of the capacitor. .

(Fourth Embodiment) FIG. 4 is a sectional view showing a structure of a capacitor sheet according to a fourth embodiment of the present invention. The basic structure is similar to that of the capacitor sheet of FIG. In the present embodiment, all the structures for electrical connection are formed by through via conductors.

In order to electrically connect the front and back of the multi-layer laminate, the internal counter electrodes 2a and 2 are formed in through holes formed through the dielectric layer 1 and the counter electrodes 2a and 2b.
A through via conductor 5 is provided which is insulated from the surface b by the insulating wall 3. In addition, a plurality of counter electrodes 2a or 2b
Counter electrodes 2a and 2b for electrically connecting
Through regions formed in the areas not facing each other through the dielectric layer 1 and the counter electrode 2a or 2b are provided with through via conductors 5a or 5b.

With the above structure, the through via conductors 5a and 5
The capacitor can be used by using b, and the through via conductor 5 allows an electric signal on the front and back sides to pass independently of the capacitor.

FIG. 5 shows through via conductors 5, 5a, and 5
The example of planar arrangement of b is shown.

(Fifth Embodiment) Next, a method of manufacturing a capacitor sheet according to a fifth embodiment of the present invention will be described with reference to FIG.
Will be described with reference to.

First, as shown in FIG. 6A, the dielectric layer 1, the counter electrode 2a, and the counter electrode 2 are formed by using a known technique.
A laminated capacitor sheet in which b is laminated is produced. Next, as shown in FIG. 6B, a through hole 10 is formed in a necessary portion where the counter electrode 2a and the counter electrode 2b face each other. Drilling or laser processing can be used as the hole processing method in this case.

Next, as shown in FIG. 6C, the through holes 10 are filled with the insulating paste 11. The insulator paste 11 may include an inorganic filler having an insulating property. When the insulating paste 11 contains a thermosetting resin, it is subjected to a curing treatment and then proceeds to the next step.

Next, as shown in FIG. 6D, a film having the adhesive layer 13 formed on the release film 12 is laminated on both surfaces of the capacitor sheet of FIG. 6C. In this case, as shown in the figure, the capacitor sheet is laminated such that the adhesive layer 13 contacts the surface of the capacitor sheet. The laminating method can be performed by a known technique such as laminating or pressing.

Next, as shown in FIG. 6E, the insulator paste 11
Then, a through hole 14 having a diameter smaller than that is formed. Thereby, a structure in which the through hole 14 is arranged in the insulating wall 3 is formed. As the hole processing method in this case, drilling or laser processing can be used. The through holes 14 are preferably concentric with the insulating paste 11.

Next, as shown in FIG. 6F, the through holes 14 are filled with the conductor paste 5. As a filling method, the conductive paste 5 is directly printed on the release film 12 by using a screen printer to fill the conductive paste 5. At this time, the resin component in the conductor paste 5 in the through holes 14 is absorbed by vacuum suction from the side opposite to the printed surface through a porous sheet such as Japanese paper, thereby increasing the ratio of the conductor component. ,
The conductor component can be filled more densely. In this step, the release film 12 plays a role of a printing mask and a role of preventing contamination of the surface of the adhesive layer 13.

Next, as shown in FIG. 6G, the release film 1
2 is peeled from both sides of the capacitor sheet. Then, FIG.
As shown in H, the metal foil 15 is superposed on both sides of the capacitor sheet and heated and pressed. The heating and pressing is performed by, for example, a vacuum press. By this heating and pressing, the adhesive layer 13
Then, the conductor paste 5 is thermally cured to form a capacitor sheet to which the metal foil 15 is bonded, as shown in FIG. 6I.

Next, as shown in FIG. 6J, a through hole 16 is formed in a portion where only one of the counter electrode 2a and the counter electrode 2b is arranged. Further, as shown in FIG. 6K, the through-hole 16 is plated with a conductor to form the through-hole conductor 4.
a and 4b are formed. Finally, as shown in FIG. 6L, the metal foils 15 on both sides are patterned by a photolithographic etching method.

(Embodiment 6) FIGS. 7A to 7C are process sectional views showing a method of manufacturing a capacitor sheet according to Embodiment 6 of the present invention.

First, as shown in FIG. 7A, the dielectric layer 1, the counter electrode 2a, and the counter electrode 2 are formed by using a known technique.
A laminated capacitor sheet in which b is laminated is produced. Next, as shown in FIG. 7B, a through hole 10 is formed in a necessary portion where the counter electrode 2a and the counter electrode 2b face each other. Drilling or laser processing can be used as the hole processing method in this case.

Next, as shown in FIG. 7C, the through holes 10 are filled with the insulating paste 11. The insulator paste 11 may include an inorganic filler having an insulating property. When the insulating paste 11 contains a thermosetting resin, after the curing treatment, a film in which the adhesive layer 13 is formed on the release film 12 is formed on both surfaces of the capacitor sheet of FIG. 7C as shown in FIG. 7D. Stack. In this case, as shown in the figure, the capacitor sheet is laminated such that the adhesive layer 13 contacts the surface of the capacitor sheet.
The laminating method can be performed by a known technique such as laminating or pressing.

Next, as shown in FIG. 7E, the insulator paste 11
Then, a through hole 14 having a diameter smaller than that is formed. Thereby, a structure in which the through hole 14 is arranged in the insulating wall 3 is formed. Further, the through hole 16 is also formed in a portion where only one of the counter electrode 2a and the counter electrode 2b is arranged. As the hole processing method in this case, drilling or laser processing can be used. The through holes 14 are preferably concentric with the insulating paste 11.

Next, as shown in FIG. 7F, the through holes 14 and 16 are filled with the conductive paste 5. As a filling method, the conductive paste 5 is directly printed on the release film 12 by using a screen printer to fill the conductive paste 5. At this time, the resin component in the conductor paste 5 in the through holes 14 and 16 is absorbed by vacuum suction from the side opposite to the printed surface through a porous sheet such as Japanese paper to increase the ratio of the conductor component. Thus, the conductor component can be more densely filled. In this step, the release film 12 plays a role of a printing mask and a role of preventing contamination of the surface of the adhesive layer 13.

Next, as shown in FIG. 7G, the release film 1
2 is peeled from both sides of the capacitor sheet. Then FIG.
As shown in H, the metal foil 15 is superposed on both sides of the capacitor sheet and heated and pressed. The heating and pressing is performed by, for example, a vacuum press. By this heating and pressing, the adhesive layer 13
And the conductor paste 5 is heat-cured to form a capacitor sheet to which the metal foil 15 is adhered, as shown in FIG. 7I.

Finally, as shown in FIG. 7J, the metal foils 15 on both sides are patterned by photolithography.

(Seventh Embodiment) FIG. 8 is a sectional view of a multilayer substrate according to a seventh embodiment. This multilayer substrate incorporates the capacitor sheet of the present invention. In FIG.
101 indicates a capacitor sheet. Conduction between the upper and lower sides of the substrate is ensured by the through through electrodes 102. On the other hand, the built-in capacitor can be used by using the electrodes 103a and 103b.

(Embodiment 8) FIG. 9 is a cross-sectional view of a multilayer substrate according to Embodiment 8. This multilayer substrate incorporates a large number of capacitor sheets 101 and 104. Inside the substrate, the capacitor sheet 101 of any size can be built in any layer. Further, it is also possible to use a sheet obtained by dividing the inside of the sheet in advance like the capacitor sheet 104.

(Ninth Embodiment) FIG. 10 shows a ninth embodiment.
3 is a cross-sectional view showing the semiconductor device in FIG. This semiconductor device is obtained by mounting a semiconductor on the capacitor-embedded substrate of the present invention.

In FIG. 10, reference numeral 200 denotes a multi-layer substrate containing a capacitor sheet. On the surface of the multi-layer substrate 200, the semiconductor chip 201 is connected to the flip chip connection 202.
Connected by. In this case, the implementation method is
Known mounting techniques such as solder connection can be used. In addition, an underfill 203 can be provided if necessary.

(Tenth Embodiment) FIG. 11 is a sectional view showing a semiconductor device according to a tenth embodiment. In this semiconductor device, a carrier substrate 204, on which a semiconductor chip 201 is primarily mounted in advance, is secondarily mounted on the surface of a multilayer substrate 200 having a built-in capacitor sheet. The semiconductor chip 201 is connected to the surface of the carrier substrate 204 by flip chip connection 202. As a mounting method in this case, a known mounting technique such as solder connection can be used.

(Eleventh Embodiment) FIG. 12 is a sectional view showing a semiconductor device according to the eleventh embodiment. This semiconductor device is substantially the same as that of the ninth embodiment, except that the semiconductor chip is flip-chip mounted on the capacitor sheet.

(Twelfth Embodiment) FIG. 13 is a sectional view showing a semiconductor device according to a twelfth embodiment. This semiconductor device is almost the same as that of the tenth embodiment except that it is equipped with a semiconductor chip carrier mounted on a capacitor sheet.

[0053]

According to the present invention, in the multilayer laminated capacitor sheet, the front and back electrical through-connection structures and the capacitor electrodes can be independently utilized. Therefore, the capacitor layer can be formed immediately below the mounted component, in other words, the outermost layer of the substrate. Therefore, the via connection for connecting to the capacitor can be minimized, and the influence of the inductance of the via can be suppressed to the minimum. As a result, the power supply can be stabilized more effectively.

Further, by providing a via that passes through the capacitor layer and is connected to the layer below the capacitor layer, wiring connection with a high degree of freedom becomes possible, and therefore the design becomes simple.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a capacitor sheet according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a structure of a capacitor sheet according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a structure of a capacitor sheet according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a structure of a capacitor sheet according to a fourth embodiment of the present invention.

FIG. 5 is a perspective view showing a structure of a capacitor sheet of the present invention.

FIG. 6 is a process sectional view showing the method of manufacturing the capacitor sheet in the fifth embodiment of the present invention.

FIG. 7 is a process cross-sectional view showing the method of manufacturing a capacitor sheet in the sixth embodiment of the present invention.

FIG. 8 is a sectional view showing a substrate with a built-in capacitor sheet according to a seventh embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a capacitor sheet built-in substrate according to an eighth embodiment of the present invention.

FIG. 10 is a sectional view showing a semiconductor device according to a ninth embodiment of the present invention.

FIG. 11 is a sectional view showing a semiconductor device according to a tenth embodiment of the present invention.

FIG. 12 is a sectional view showing a semiconductor device according to an eleventh embodiment of the present invention.

FIG. 13 is a sectional view showing a semiconductor device according to a twelfth embodiment of the present invention.

[Explanation of symbols]

1 Dielectric layer 2 Counter electrode 3 insulating walls 4 Through-hole conductor 5 Through via conductor 10 through holes 11 Insulator paste 12 Release film 13 Adhesive layer 14 through holes 15 Metal foil 16 through holes 101 Capacitor sheet 102 Through electrode 103 electrodes 104 Capacitor sheet 200 multi-layer board 201 semiconductor chip 202 flip chip connection 203 Underfill 204 carrier substrate

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Daizo Ando             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 5E082 BC14 CC03 JJ03 JJ15 JJ21                 5E346 AA42 BB03 BB04 CC08 DD02                       DD22 EE24 FF04 FF45 HH04                       HH05 HH06 HH25

Claims (14)

[Claims] 1. A laminate sheet including at least one laminate in which a dielectric layer is sandwiched between a power layer electrode and a ground layer electrode; and a dielectric layer, the power layer electrode, and the ground layer electrode. A through-hole conductor for front and back connection, which is formed in a through hole, is electrically insulated from the power supply layer electrode and the ground layer electrode inside by an insulating wall, and electrically connects the front and back of the laminate sheet; A layer electrode, or a grounding layer electrode, and a through conductor for a capacitor, which is formed in a region where only one of the grounding layer electrode is arranged and is electrically connected to the power supply layer electrode or the grounding layer electrode, respectively. Capacitor sheet. 2. The capacitor sheet according to claim 1, wherein the front and back connecting through conductor and the capacitor through conductor are each formed of metal plating or conductive paste. 3. The method for manufacturing a capacitor sheet according to claim 1, wherein the step of forming the through conductor for connecting the front and back sides includes the step of forming a through hole having a large diameter in the laminate sheet, A step of filling a large diameter through hole with an insulator, and a step of forming a small diameter through hole in the through hole filled with the insulator,
And a step of providing a through conductor in the small-diameter through hole. 4. The method of manufacturing a capacitor sheet according to claim 3, wherein the step of providing the through conductor is performed by applying metal plating to an inner wall of the small diameter through hole. 5. The method of manufacturing a capacitor sheet according to claim 3, wherein the step of providing the through conductor is performed by connecting the through hole having the small diameter with a conductive paste. 6. The method of manufacturing a capacitor sheet according to claim 3, wherein the insulator filling the large-diameter through hole formed in the laminate sheet is a thermosetting resin. 7. The method of manufacturing a capacitor sheet according to claim 6, wherein the insulator filled in the large-diameter through hole formed in the laminated sheet contains an inorganic filler. 8. A capacitor-embedded substrate in which the capacitor sheet according to claim 1 is laminated, wherein printed wiring boards laminated on both surfaces of the capacitor sheet are electrically connected by the through conductor for connecting the front and back sides. And a capacitor-embedded substrate, wherein the capacitor sheet is connected to the power source layer electrode and the ground layer electrode of the capacitor sheet. 9. The capacitor sheet is incorporated in a plurality of layers in the same layer or in two or more layers.
The substrate with a built-in capacitor described in. 10. The substrate with a built-in capacitor according to claim 8, wherein the front-back connection through conductor and the capacitor through conductor are each formed of metal plating or conductive paste. 11. A resin multilayer substrate having a signal wiring layer formed on the surface and inside thereof, a capacitor sheet according to claim 1 installed and connected in the resin multilayer substrate, and a flip on the resin multilayer substrate. A semiconductor device comprising a chip-mounted semiconductor chip. 12. A resin multi-layer substrate having a signal wiring layer formed on the surface and inside thereof, the capacitor sheet according to claim 1 installed and connected in the resin multi-layer substrate, and mounted on the resin multi-layer substrate. And a semiconductor chip carrier that has been manufactured. 13. A resin multilayer substrate having a signal wiring layer formed on the surface and inside thereof, the capacitor sheet according to claim 1 installed and connected on the resin multilayer substrate, and a flip chip on the capacitor sheet. A semiconductor device comprising: a mounted semiconductor chip. 14. A resin multilayer board having a signal wiring layer formed on the surface and inside thereof, the capacitor sheet according to claim 1 installed and connected on the resin multilayer board, and mounted on the capacitor sheet. And a semiconductor chip carrier.