JP2003031649A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To bury an element isolation groove having a high aspect ratio, a wiring layer, and an electrode without generating a void. SOLUTION: When embedding a groove 5 having a high aspect ratio formed in a semiconductor substrate 1 with a silicon oxide film 6, the HDP-C is so thin that the frontage is not blocked by an overhang 7.
After the film is formed by VD, the overhang 7 on the side wall is selectively removed by isotropic etching to widen the frontage.
By embedding the silicon oxide film 8 again by HDP-CVD, the embedding can be performed without causing the generation of voids.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a groove formed on a surface portion of a semiconductor substrate,
Alternatively, the present invention relates to a method of embedding an insulating film between film patterns such as wiring layers and electrodes formed on a substrate.

[0002]

2. Description of the Related Art With the miniaturization and high density of semiconductor devices,
Excellent embedding characteristics for embedding a high aspect ratio step shape in the step of embedding trenches formed for element isolation or recesses between wiring layers or electrodes formed as a conductive film pattern on the substrate with an insulating film Has been done.

In response to such a demand, plasma CVD has recently begun to be used in which a bias voltage is applied to a substrate to draw ions toward the substrate to form a silicon oxide type insulating film. For example, element isolation (STI; Shallow Trench Trench Isolation) in which trenches for element isolation are filled with an insulating film
, High density plasma (HDP)
A technique for filling a trench for element isolation with a non-doped silicon oxide film (SiO ₂ ) using asma) CVD (chemical vapor deposition) is being put to practical use.

FIG. 3 shows a conventional method of filling a groove for element isolation step by step. As shown in FIG. 3A, a silicon oxide film 102 is formed on the surface of the semiconductor substrate 101 by a thermal oxidation method.

As shown in FIG. 3B, the silicon nitride film 10
3 is deposited. This silicon nitride film 103 is patterned to obtain a mask for forming grooves.

As shown in FIG. 3C, the silicon nitride film 10
RIE (Reactive
Etching such as Ion Etching) is performed to form the groove 105. A silicon oxide film 104 is formed on the side wall and bottom surface of the groove 105 by a thermal oxidation method.

As shown in FIG. 3D, a silicon oxide film 106 is deposited by the HDP-CVD method so as to fill the groove 105.

However, in the process of depositing the silicon oxide film 106, since deposition and sputtering occur simultaneously, the silicon oxide film 106 deposited on the side wall above the step is sputtered, as indicated by arrow A.
Redeposit on the opposite sidewall as indicated by arrow B. The silicon oxide film 106 thus deposited forms an overhang 107.

Then, if the film formation is continued as it is, the redeposition of the silicon oxide film 106 by sputtering increases the overhang, and as shown in FIG. 3E, the frontage is closed and the void 108 is generated. Will be done.

As shown in FIG. 3 (f), CMP (Chemical M
The surface is planarized by the echanical Polishing method, and the planarization process is stopped using the silicon nitride film 103 as a stopper.

As shown in FIG. 3G, the silicon nitride film 103 is removed by etching.

As shown in FIG. 3H, the silicon oxide film 106 protruding above the surface of the semiconductor substrate 101 is removed by etching.

The silicon oxide film 1 thus obtained
The surface of 06 has void 1 as shown in FIG.
There will be 08.

In particular, when the groove for element isolation formed on the surface portion of the substrate and the recess between the wiring layers on the substrate or between the electrodes become narrower and deeper due to the recent miniaturization, sputtering is performed. As a result, the deposition rate of the silicon oxide film that re-deposits on the side wall and grows is faster than the deposition rate of the silicon oxide film that grows on the bottom surface of the recess. in this way,
There is a problem that voids are more likely to occur in the concave portion having a high aspect ratio.

[0015]

As described above, conventionally, when the recesses such as the inside of the groove having a high aspect ratio, the wiring layers, and the electrodes are filled with the insulating film, the overhang of the insulating film is increased and voids are generated. There was a problem that it easily occurred.

In view of the above circumstances, the present invention provides a method of manufacturing a semiconductor device, which can contribute to an improvement in yield by filling the inside of a groove, a wiring layer, a recess between electrodes, etc. without causing a void. The purpose is to do.

[0017]

According to a method of manufacturing a semiconductor device of the present invention, a groove provided in a semiconductor substrate or a concave portion on a substrate surface having an uneven portion formed by a film pattern formed on the semiconductor substrate is insulated. A method of burying a film, comprising: a first deposition step of depositing the insulating film so as to fill the recess to an intermediate stage; an etching step of removing an overhang formed by the insulating film by etching; After the step, a second deposition step of further depositing the insulating film so as to fill the recess is provided.

In the etching step, the etching rate of the insulating film formed on the side surface of the recess may be substantially equal to the etching rate of the insulating film formed on the bottom surface of the recess.

Further, in the etching step, the aspect ratio of the concave portion in which the insulating film is filled is reduced by etching to be equal to or less than the aspect ratio in the concave portion before the insulating film is filled in the first deposition step. This etching can be stopped at a stage.

Alternatively, in the etching step, it is desirable to stop the etching when the insulating film formed on the side surface of the recess remains.

In the first deposition step, it is desirable to stop the deposition of the insulating film at a stage where the overhang formed by depositing the insulating film does not block the frontage.

In the first and second deposition steps, a silicon oxide film may be deposited by high density plasma chemical vapor deposition. In the etching step, isotropic etching may be used.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

As in the conventional method described with reference to FIGS. 3A to 3C, a groove is formed on the surface portion of the semiconductor substrate 1. That is, the silicon oxide film 2 and the silicon nitride film 3 are sequentially formed on the surface of the semiconductor substrate 1, and the silicon nitride film 3 is formed.
Is patterned to obtain a mask for forming a groove. RIE is performed on the semiconductor substrate 1 using the silicon nitride film 3 as a mask.
Etching is performed to form the groove 5. A silicon oxide film 4 is formed on the side wall and bottom surface of the groove 5.

Then, the HDP-C is formed so as to fill the groove 5.
The silicon oxide film 6 is deposited by the VD method. However, as described above, the overhang 7 is formed in the process of depositing the silicon oxide film 6. If the film formation is continued as it is, the redeposition of the silicon oxide film 6 by sputtering will increase the overhang, and the frontage will be closed to generate a void.

Therefore, the film formation is temporarily stopped before the frontage is closed. After this, RIE or CDE (chemic
The overhang 7 on the side wall is removed by al downflow etching or the like to widen the frontage and reduce the aspect ratio of the groove 5. When RIE is used here, since the normal RIE is anisotropic etching, the sidewalls are not removed so much and the silicon oxide film 6 on the bottom surface of the trench 5 is largely removed. That is, compared with the aspect ratio b1 / a1 in the stage before etching shown in FIG. 2A, the aspect ratio b3 / a3 after etching shown in FIG. 2B is hardly reduced. . Therefore, if a silicon oxide film is deposited thereafter, voids are likely to occur because the frontage is narrow and the shape with a high aspect ratio is not improved.

Therefore, RI approaching isotropic etching is used.
By using E or CDE which is isotropic etching, the etching rate on the side wall is substantially equal to the etching rate on the bottom surface of the groove, and the frontage is wide and the aspect ratio is low as shown in FIG. 1 (b). The shape is obtained. That is, as compared with the aspect ratio b1 / a1 in the stage before etching shown in FIG. 1A, the aspect ratio b2 / a after etching shown in FIG.
a2 is reduced, and the shape is improved to be easily embedded. R
In order to bring the IE closer to the isotropic etching, it is conceivable to make the pressure higher than that of the normal RIE as one method. For example, when the normal RIE is about 10 mTorr or less, it is possible to increase the pressure to 50 to 100 mTorr.

Here, in order to prevent damage to the semiconductor substrate 1 on both the side wall and the bottom surface of the trench 5, the silicon oxide film 6 formed inside the trench 5 is removed and the substrate surface is not exposed. It is necessary to stop the etching at the stage.

On the other hand, the aspect ratio b2 / a2 of at least the aspect ratio b0 / a0 of the groove 5 before the deposition of the silicon oxide film 6 shown in FIG. 1A is performed.
It becomes the following, and it is desirable to stop the etching after the shape of the groove 5 is sufficiently improved.

After this, as shown in FIG. 1 (c), H
By forming the silicon oxide film 8 for the second time by the DP-CVD method, it becomes possible to prevent the occurrence of voids and to embed them.

The subsequent steps are shown in FIGS.
As described using (h), the surface is planarized by the CMP method or the like, the planarization process is stopped using the silicon nitride film 3 as a stopper, the silicon nitride film 3 is removed by etching, and the surface of the semiconductor substrate 1 is further removed. The silicon oxide films 6 and 8 protruding above are removed by etching.

As described above, according to the present embodiment, when the inside of the high aspect ratio groove is filled with the undoped silicon oxide film, the HDP-CV does not cover the frontage with an overhang.
After forming the film by D method, the overhang is selectively removed by etching by RIE or CDE method to widen the frontage.
After that, by forming the film again by the HDP-CVD method, it is possible to fill the groove without causing the generation of voids,
It can contribute to the improvement of the yield.

The above-described embodiment is an example and does not limit the present invention. For example, in the above embodiment, the case where the groove formed in the surface portion of the semiconductor substrate is filled has been described as an example. However, not limited to this,
The present invention can be similarly applied to the case of filling the recesses between the wiring layers formed as the conductive film pattern on the semiconductor substrate or between the electrodes with the interlayer insulating film. The present invention is very effective in embedding an insulating film in a recess having an aspect ratio. Further, in the above-described embodiment, a non-doped (non-doped) silicon oxide film is used as the insulating film that fills the groove.

[0034]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the groove formed in the surface portion of the substrate or the recess formed between the wiring layer and the electrode formed on the substrate is insulated. When embedding with a film, when the first film formation is temporarily stopped and the overhang of the side wall is selectively removed by etching to widen the frontage and then film formation is performed again, the recess has a high aspect ratio. In addition, it is possible to embed without causing the generation of voids, which can contribute to the improvement of yield.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention step by step.

FIG. 2 is a vertical cross-sectional view showing a change in shape when anisotropic etching is performed on a silicon oxide film formed by the first film forming process.

FIG. 3 is a vertical cross-sectional view showing a conventional method of manufacturing a semiconductor device step by step.

[Explanation of symbols]

1 Semiconductor substrate 2,4 Silicon oxide film 3 Silicon nitride film 5 grooves 6,8 Silicon oxide film 7 Overhang

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor, Kaneko Shigehiko             8th Shinsugita Town, Isogo Ward, Yokohama City, Kanagawa Prefecture             Ceremony company Toshiba Yokohama office F-term (reference) 5F032 AA35 AA44 AA45 AA70 DA04                       DA25 DA26 DA78                 5F033 QQ09 QQ11 QQ13 QQ18 RR04                       SS15 XX00 XX02                 5F058 BA02 BA20 BD01 BD04 BE04                       BF07 BF61 BH12 BJ06

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor device in which an insulating film is embedded in a groove provided in a semiconductor substrate or a concave portion of a substrate surface having an uneven portion formed by a film pattern formed on the semiconductor substrate on the surface thereof. The first deposition step of depositing the insulating film so as to fill up to the step, an etching step of removing the overhang formed by the insulating film by etching, and the step of further filling the recess after the etching step. A second deposition step of depositing an insulating film, and a method of manufacturing a semiconductor device, comprising: 2. In the etching step, a rate of etching the insulating film formed on a side surface of the recess is substantially equal to a rate of etching the insulating film formed on a bottom surface of the recess. The method of manufacturing a semiconductor device according to claim 1. 3. In the etching step, the aspect ratio of the recess filled with the insulating film is reduced by etching to be equal to or less than the aspect ratio of the recess before the insulating film is filled in the first deposition step. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the etching is stopped at a stage. 4. The manufacturing of a semiconductor device according to claim 1, wherein in the etching step, the etching is stopped when the insulating film formed on the side surface of the recess remains. Method. 5. The first deposition step, wherein the deposition of the insulating film is stopped at a stage where the overhang formed by depositing the insulating film does not block the frontage. A method for manufacturing a semiconductor device according to any one of 1. 6. The semiconductor device according to claim 1, wherein in the first and second deposition steps, a silicon oxide film is deposited by a high density plasma chemical vapor deposition method. Manufacturing method. 7. The method of manufacturing a semiconductor device according to claim 1, wherein isotropic etching is used in the etching step.