JP2002009161A - Semiconductor device and dummy pattern arrangement method - Google Patents

Abstract

(57) [Problem] To improve flatness of a semiconductor device. A semiconductor device according to the present invention includes a semiconductor substrate (1).
And a first A / A dummy pattern 5a and a second A / A dummy pattern 5b having a smaller pitch than the first A / A dummy pattern 5a in an element isolation region of the semiconductor substrate 1. The arrangement of the first and second A / A dummy patterns 5a and 5b is performed in another step. The semiconductor device of the present invention
In another aspect, the semiconductor device has a dummy pattern arranged according to the occupation ratio of the element pattern in the mesh region that divides the region on the semiconductor substrate into a plurality.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a dummy pattern for reducing a step caused by the density of a pattern during manufacturing, and a method of arranging the dummy pattern.

[0002]

2. Description of the Related Art Conventionally, CMP (Chemical Mechanical)
al Polishing) process, a dummy pattern is formed in the element isolation region in order to suppress the problem of flatness deterioration occurring in the isolation insulating film in the element isolation region due to the density of the pattern in the element formation region that should be formed. Semiconductor devices to be arranged are known.

For example, Japanese Patent Application Laid-Open No. Hei 8-213396 discloses an example of a dummy pattern in a wiring layer, and Japanese Patent Application Laid-Open No. Hei 9-181159 discloses an STI (Shallow Trench Isolate) for separating element formation region patterns.
on), that is, an example of a dummy pattern when using shallow trench isolation is disclosed.

In a semiconductor device used in recent years, all elements are separated by STI in order to simplify the manufacturing process. Therefore, as shown in FIG. 18, the element isolation region 103 is a very large region.

As shown in FIG. 18, trenches 103a and 103b are formed in an element isolation region 103 of a semiconductor substrate 101, and an insulating film 102 is deposited so as to cover the trenches 103a and 103b. Thereafter, planarization is performed by performing CMP or etch back.

At this time, as shown in FIG. 19, the surface of isolation insulating film 102a formed in wide trench 103a is separated from isolation insulating film 1 formed in narrow trench 103b.
The surface is greatly depressed as compared with the surface of No. 02b.

As means for suppressing this large depression, as shown in FIG. 20, after forming a dummy pattern 105 in a wide trench 103a, an insulating film 102 is deposited and
There is a method of executing MP or the like.

According to this method, as shown in FIG.
The surface of the isolation insulating film 102a remaining in the wide trench 103a after performing the CMP or the like does not largely depress. Therefore, as compared to the case shown in FIG.
The flatness of the surface of the isolation insulating film 102a formed in 3a is improved. That is, the flatness of the semiconductor device can be improved.

[0009]

In order to further improve the flatness and dimensional controllability of the semiconductor device, it is effective to reduce the pitch (width) of the dummy pattern 105. Thus, the dummy patterns 105 can be comprehensively arranged on the entire semiconductor device, and the flatness of the semiconductor device can be improved while the dimensional controllability is improved.

However, the conventional dummy pattern 10
No. 5 is automatically arranged by CAD (Calculation Automatic Design) processing, and the pitch of the dummy pattern 105 is constant, so it is difficult to arrange the dummy pattern 105 with a small pitch comprehensively over the entire semiconductor device. Was.

This is because the pitch of the dummy pattern 105 is reduced and the dummy pattern 1 is exhaustively covered over the entire semiconductor device.
This is because the arrangement of 05 causes not only an increase in the CAD processing time but also an increase in the CAD processing capacity, which may make it impossible to perform the processing.

There are also the following problems. That is, when the dummy patterns 105 are uniformly arranged over the entire semiconductor device, the dummy patterns 105 are also arranged in the regions where the patterns were originally dense, and a sufficient flatness improving effect cannot be obtained. there were.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to improve the flatness of a semiconductor device and to shorten the CAD processing time for arranging dummy patterns. Another object is to reduce the CAD processing capacity.

[0014]

According to one aspect, a semiconductor device according to the present invention includes an element pattern formed on a semiconductor substrate and a first element disposed on the same layer as the element pattern.
A dummy pattern and a second dummy pattern arranged on the same layer as the element pattern and having a different pitch from the first dummy pattern are provided. Here, the same layer refers to, for example, a layer or a portion existing at substantially the same height position on the semiconductor substrate or the semiconductor substrate as the adjacent dummy patterns 5a and 5b in FIG.
The element pattern refers to a pattern constituting an element, and is a concept including an active region pattern, a wiring pattern, and the like as described later.

By providing the first and second dummy patterns having different pitches as described above, for example, the first dummy pattern having a relatively large pitch is arranged in a wide area in the element isolation region, and the first dummy pattern is formed in a relatively narrow area. Can arrange the second dummy patterns having a relatively small pitch. Thus, the dummy patterns can be comprehensively arranged on the entire semiconductor device. Further, for example, by arranging the first and second dummy patterns in descending order of the pitch, it is possible to substantially reduce the processing area for arranging the dummy pattern of the small pitch, and to place the dummy pattern of the small pitch in the entire area. Compared with the arrangement, the CAD processing time and the CAD processing capacity can be reduced.

The above-mentioned element pattern includes an element formation area pattern (active area pattern) separated and formed by an element isolation area on a semiconductor substrate. In this case, the first and second dummy patterns are arranged in the element isolation region.

Further, the element pattern includes a wiring pattern formed on a semiconductor substrate. In this case, the first and second dummy patterns are arranged around the wiring pattern.

In any of the above cases, dummy patterns can be comprehensively arranged on the entire semiconductor device.

In another aspect, a semiconductor device according to the present invention includes a plurality of mesh regions (divided regions) on a semiconductor substrate.
And an element pattern located in the mesh area, and a dummy pattern arranged in the mesh area so as to have an occupancy according to the occupancy of the element pattern, which is the area of the element pattern with respect to the area of the mesh area.

By arranging the dummy patterns in accordance with the occupation ratio of the element patterns in the mesh region which divides the region on the semiconductor substrate into a plurality of regions, the dummy patterns are arranged in each mesh region in accordance with the density of the element patterns. Can be appropriately arranged. Thereby, the dummy pattern can be arranged comprehensively over the entire semiconductor device, and the variation in the ratio of the convex portions between the respective mesh regions can be reduced. As a result, the flatness of the semiconductor device can be improved. . In addition, by arranging dummy patterns of an appropriate size according to the density of element patterns, it is possible to reduce the CAD processing time and the CAD processing capacity.

The dummy pattern preferably includes first and second dummy patterns having different pitches. Thereby, the flatness of the semiconductor device can be further improved.

In any case, the arrangement of the first dummy pattern and the arrangement of the second dummy pattern are preferably performed in different steps. Further, when the semiconductor device has a first region where the first dummy pattern is arranged and a second region where the second dummy pattern is arranged, the first region
It is preferable that the placement of the first dummy pattern in the region and the placement of the second dummy pattern in the second region are performed in different steps. Further, it is preferable to arrange the dummy patterns in order from the larger pitch.

By arranging dummy patterns having different pitches in different steps, it is possible to reduce the CAD processing time and the CAD processing capacity.

In one aspect, a dummy pattern arranging method according to the present invention includes a first dummy pattern having a relatively large pitch and a second dummy pattern having a relatively small pitch arranged on the same layer. An arrangement method of a dummy pattern in a semiconductor device, wherein the arrangement of a first dummy pattern and the arrangement of a second dummy pattern are performed in different steps.

As a result, the CAD processing time and the CAD processing capacity can be reduced as described above.

First and second dummy patterns are arranged in the element isolation region of the semiconductor device, and the element isolation region is formed by the first and second dummy patterns.
It is divided into a first area where the dummy pattern is arranged and a second area where the second dummy pattern is arranged. in this case,
After arranging the first dummy pattern in the first area, it is preferable to arrange the second dummy pattern in the second area.

Further, the first and second dummy patterns are arranged around the wiring pattern of the semiconductor device, and the area between the wiring patterns is defined by the first area where the first dummy pattern is arranged and the second dummy pattern. And a second area to be processed. In this case, it is preferable to arrange the second dummy pattern in the second area after the first dummy pattern is arranged in the first area.

By dividing the formation regions of the first and second dummy patterns in this manner, the processing of the second region may be performed when the second dummy patterns are arranged. Thereby, the CAD processing area can be reduced, and the CAD processing area can be reduced.
This can contribute to a reduction in processing time and a reduction in CAD processing capacity.

The first dummy pattern has a first upper layer dummy pattern and a first lower layer dummy pattern, and the second dummy pattern has a second upper layer dummy pattern and a second lower layer dummy pattern. In this case, the arrangement data of the first and second lower-layer dummy patterns is used as the arrangement data of the first and second upper-layer dummy patterns.

As described above, the use of the layout data of the lower dummy pattern can also reduce the CAD processing time and reduce
This can contribute to a reduction in AD processing capacity.

In another aspect, the dummy pattern arrangement method according to the present invention includes the following steps. The semiconductor chip area is divided into a plurality of mesh areas. Based on the first occupancy, which is the area of the element pattern located in the mesh area with respect to the area of the mesh area, a second occupancy, which is the area of the dummy pattern arranged in the mesh area with respect to the area of the mesh area, is determined. The dummy pattern is arranged in the mesh area so that the occupancy of the dummy pattern in the mesh area becomes the second occupancy.

By arranging the dummy pattern based on the first occupation ratio of the element pattern in the mesh region as described above, the variation in the ratio of the convex portions between the mesh regions can be reduced, and the flatness of the semiconductor device can be reduced. Can be improved. Further, by arranging a dummy pattern of an appropriate size based on the first occupation ratio,
The CAD processing time and the CAD processing capacity can be reduced.

The step of arranging the dummy pattern includes a step of adjusting the size of the dummy pattern so that the occupancy of the dummy pattern in the mesh area becomes the second occupancy. This makes it possible to optimize the size of the dummy pattern, shorten the CAD processing time, and reduce
D processing capacity can be reduced.

The step of determining the second occupancy may include a step of obtaining the first occupancy and then performing a Fourier transform to obtain an occupancy distribution over the entire semiconductor chip area. In this case, the arranging step of the dummy pattern includes arranging the dummy pattern according to the occupancy distribution.

The step of determining the second occupancy is
After obtaining the first occupancy rate for each mesh area, the method may include a step of obtaining an average occupancy rate by averaging the occupancy rates of the plurality of mesh areas. In this case, the step of arranging the dummy pattern includes the step of arranging the dummy pattern according to the average occupancy.

By determining the second occupancy as described above, it is possible to more effectively select and arrange dummy patterns.

It is preferable that the larger the first occupancy is, the smaller the second occupancy is. Thereby, it is possible to reduce the variation in the ratio of the convex portions between the mesh regions.

The step of determining the second occupancy preferably includes the step of adding the first occupancy in the lower layer to obtain a second occupancy. Here, “addition” means determining the second occupancy in consideration of the first occupancy, and not only when the first occupancy of the lower layer is simply added, but also
The case where the second coefficient is multiplied by a predetermined coefficient obtained from the first coefficient of the lower layer is also included.

As described above, considering the step of the lower layer, the second
By determining the occupancy, the step in the semiconductor device can be reduced even when dense portions or sparse portions of the pattern are stacked.

In any of the above aspects, the first dummy pattern is arranged in the first cell area, the second dummy pattern is arranged in the second cell area, and the pitch of the first cell area is changed to the second cell area. The pitch may be larger than the pitch. In this case, the occupancy of the second dummy pattern in the second cell region is set higher than the occupancy of the first dummy pattern in the first cell region.

Thus, the second dummy pattern can be arranged in a small area where the first dummy pattern cannot be arranged, and the variation in the ratio of the convex portions between the mesh areas can be further reduced.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

(First Embodiment) First, a design flow of a semiconductor device according to a first embodiment will be described with reference to FIGS.

As shown in FIG. 1, a plurality of cell regions 6 partitioned by an orthogonal grid are arranged in an area 60, and a dummy pattern 5 is arranged in the cell area 6. FIG.
2 shows an enlarged view of the region 7 in FIG.

As shown in FIG. 2, each dummy pattern 5 inside the cell area 6 has a rectangular shape that can be formed by two vertices on the CAD data. This minimizes the amount of data on CAD,
The occupancy of the dummy pattern in the area 60 can be easily controlled. The configuration inside the cell region 6 is as follows.
It may be composed of a plurality of rectangles as shown in FIGS.

Next, a CAD flow for arranging the element formation region pattern 4, the well 8, the gate electrode 12, and the like in the region 60 having a plurality of cell regions 6 in which the dummy patterns 5 are arranged is shown in FIG. This will be described with reference to FIG.
Note that the steps of forming the aluminum wiring layer and the like are omitted.

First, as a flow 1, a cell region 6 having a dummy pattern 5 is arranged on a grid having a pitch A over the entire region (CAD chip) 60 constituting a semiconductor device.

Thereafter, as shown in FIG. 7, well 8 (p-well or n-well), element formation region pattern 4 and gate electrode 12 are arranged in region 60.

Next, as a flow 2, as shown in FIG. 8, the cell region 6 intersecting with the element forming region pattern 4 is deleted. At this time, a desired oversize is applied to the element formation region pattern 4. That is, the cell region 6 is deleted assuming a slightly larger element formation region pattern 4. As a result, the separation characteristics between the element forming region pattern 4 and the dummy pattern 5 can be sufficiently maintained.

Next, as a flow 3, as shown in FIG. 9, the cell region 6 intersecting the boundary of the well 8 is deleted. At this time, the cell region 6 that intersects the figure obtained by subtracting the undersized figure from the desired oversized figure for the well 8 is deleted. That is, the cell region 6 that intersects with the region located between the inside of the region slightly larger than the boundary line of the actual well 8 and the outside of the region slightly smaller than the actual well 8 is deleted. Thereby,
The separation characteristics at the boundary of the well 8 can be maintained.

Further, as a flow 4, as shown in FIG. 10, the cell region 6 intersecting with the region where the gate electrode 12 is formed is deleted. At this time, a desired oversize is applied to a region where the gate electrode 12 is to be formed, and the cell region 6 is removed. Thereby, a margin for misalignment or the like, that is, a margin for overlay error can be secured.

By providing the flow 4, the effect of the dummy pattern can be obtained without increasing the wiring capacitance of the gate electrode 12 and increasing the area of the reliability of the gate insulating film.

Next, the cell region 6 having the dummy pattern 5
Are arranged on the grid at a pitch B smaller than the pitch A. Then, the area where the cell area 6 remains (the first area) is added to the forbidden layer, and the cell area 6a intersecting with the cell area 6 is deleted. Thus, the cell region 6 having the small pitch B is provided only in the region (second region) 9.
a will remain.

Thereafter, the above flows 2 to 4 are performed for the cell region 6a, and as shown in FIG. 11, the cell region 6a having a small pitch is formed in the region 9 where the cell region 6 is not formed.
Place. That is, the small pitch dummy pattern 5
Are arranged in the area 9 (flow 5). Through the above flow, multiple cell areas (dummy patterns) with different pitches
Can be sequentially arranged in another step.

The cell regions 6 and 6a remaining after the above flows 1 to 5 are merged with the element formation region pattern 4. That is, by performing an OR process, the cell regions 6 and 6a and the element formation region pattern 4 are regarded as a planar integral shape. Then, an opening pattern is formed on the same mask (reticle) (flow 6).

Using this mask, an element formation region pattern 4 and a dummy pattern 5 on the same layer as the element formation region pattern 4 are formed on a semiconductor substrate. In the same manner, the gate electrode 12
Then, a dummy pattern 5 having the same layer as the dummy pattern 5 is formed.

The above flows 2 to 4 are in no particular order, and the flows 3 and 4 can be omitted by a process. In addition, the process of deleting each of the dummy patterns 5 may be performed by processing the regions for forming the element forming region pattern 4, the well 8, and the gate electrode 12 to a desired size, and then merging and performing the batch processing.
In addition, the above-described concept of the flow is also applicable when arranging dummy patterns having three or more types of pitches.

According to the above design flow, dummy patterns 5 having various pitches from a large pitch to a fine pitch can be formed at appropriate positions. This makes it possible to form the dummy pattern 5 having an optimum pitch according to the size of the element isolation region. As a result, a dummy pattern can be formed over the entire semiconductor device, and the flatness of the semiconductor device can be further improved.

Further, by arranging the cell regions 6 with the larger pitch in order, the region where the cell region 6a with the smaller pitch is arranged can be limited to only the region 9 where the cell region 6 with the larger pitch is not arranged. . That is, the dummy pattern with the small pitch is arranged only in the region 9 where the dummy pattern with the large pitch is not arranged. This makes it possible to reduce the CAD processing area for arranging small-pitch dummy patterns, and to reduce the CAD processing time and memory usage compared to the case where small-pitch dummy patterns are arranged in all areas. Becomes possible.

As a result, it is possible to automatically arrange a plurality of types of dummy patterns 5 having different pitches, and it becomes easier to form a mask for manufacturing a semiconductor device.

(Embodiment 2) Next, an example of a semiconductor device according to the present invention will be described with reference to FIGS.

As shown in FIGS. 12 and 13, the semiconductor device according to the present embodiment has an element forming region pattern 4, first and second active regions (A / A:
Active Area) Dummy patterns 5a and 5b, trenches formed in element isolation regions, isolation insulating films 2a embedded in the trenches, gate insulating films 11, gate electrodes 1
2 and first and second gate dummy patterns 13a and 13b having different pitches.

First and second A / A dummy patterns 5
“a” and “5b” are provided on the same layer as the element formation region pattern 4. In the embodiment shown in FIG. 12 and FIG.
The pitch L1 of the / A dummy pattern 5a is larger than the pitch L2 of the second A / A dummy pattern 5b.

First and second A / A dummy patterns 5
In order to form a and 5b, openings for the first and second A / A dummy patterns 5a and 5b are provided in a mask for forming the element formation region pattern 4 according to the above-described flow. Using this mask, the first and second A / A dummy patterns 5a and 5b are formed simultaneously with the formation of the element formation region pattern 4.

First and second gate dummy patterns 13
a and 13 b are provided on the same layer as the gate electrode 12. As shown in FIGS. 12 and 13, the pitch L1 of the first gate dummy pattern 13a is larger than the pitch L2 of the second gate dummy pattern 13b.

First and second gate dummy patterns 13
To form the gate electrodes 12a and 13b, the first and second masks for forming the gate electrode 12 in accordance with the above-described flow are used.
Openings for the gate dummy patterns 13a and 13b are provided.

Then, using this mask, the first and second gate dummy patterns 13a and 13b are formed on the gate insulating film 11 simultaneously with the formation of the gate electrode 12.
The first and second gate dummy patterns 13a, 13
b is the first and second A / A dummy patterns 5a, 5b
Formed immediately above.

By forming the first and second gate dummy patterns 13a and 13b and the gate electrode 12 at the same time, the etching of the conductive layer for forming the gate electrode 12 is performed only in the portion where the gate electrode 12 is to be formed. Instead, it is performed substantially uniformly over the entire surface of the semiconductor substrate. Thereby, the distribution of the etching gas and the like becomes substantially uniform over the entire surface of the semiconductor substrate, and the dimensional controllability by etching the gate electrode 12 is improved.

The first and second A / A dummy patterns 5a and 5b as lower layers and the first and second A / A dummy patterns as upper layers are formed.
Since the gate dummy patterns 13a and 13b are the same pattern, the first and second A / A dummy patterns 5a and 5b are used to utilize the pattern data of the first and second A / A dummy patterns 5a and 5b.
Gate dummy patterns 13a and 13b can be obtained.

That is, the pattern data of the first and second A / A dummy patterns 5a and 5b and the pattern data of the gate electrode 12 can be merged to form a pattern on the same mask. Thereby, the dimensional controllability in the gate electrode forming step can be improved without increasing the load of the CAD process.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIGS.

In the fourth embodiment, as shown in FIG. 14, the entire surface of a CAD chip (semiconductor chip area) is divided into a plurality of mesh areas 14 having a length or width of, for example, about 10 to 1000 μm. The occupation ratio of the element formation region pattern (A / A pattern) 4 is obtained for each of the cases. The element occupation area pattern occupancy is calculated by (element formation area pattern area in each mesh area) / (area of each mesh area).

Here, the occupancy will be described in more detail with reference to FIGS. Specifically, A
The A / A occupancy of the / A dummy pattern will be described.
FIGS. 15 and 16 are schematic cross-sectional views of the semiconductor device in which the buried insulating film 16 is formed after the formation of the trench 15.

FIG. 15 shows an example in which a TEOS oxide film is deposited conformally to irregularities, for example, like a TEOS oxide film deposited in a plasma CVD apparatus, and FIG.
Etching and deposition are repeated like an oxide film deposited by DP-CVD, and the buried insulating film
6 shows an example in which 6 is extended.

15 and 16, t is the depth of the trench 15, d is the deposited film thickness of the buried insulating film 16, and x is A
The sizing amount of A / A convex portion with respect to A / A, and n indicates a coefficient with respect to the height for determining the A / A convex portion.

In the case of polishing and flattening by CMP, if the occupation ratio of the convex portion is different in a wide range, there is a problem that the polishing rate is changed due to the difference in surface pressure of the CMP polishing cloth, and an absolute step is left. Specifically, when the occupation ratios of the protrusions differ by 20% or more, significant steps are recognized.

Therefore, the convex portion occupancy is defined as follows. First, in the example in which the buried insulating film 16 is conformally deposited as shown in FIG. 15, x is represented by x = t × cos (si
n ^-1 (n)), in the example in which the buried insulating film 16 extends at an oblique angle of 45 degrees as shown in FIG. 16, x is represented by x = t × n.

The value of n depends on the polishing rate.
Since it is around 5, it is close to 0.5. At this time, each A
The ratio of the area of the A / A convex portion sized by x to / A divided by the area of the entire cell is calculated as the occupancy of the convex portion (A / A
A pattern occupancy).

After the A / A pattern occupancy is determined for each mesh area 14 as described above (flow 1), flows 2 to 5 similar to flows 1 to 4 of the first embodiment are performed. The cell region 6 remaining after the flows 2 to 5 and the element formation region pattern 4 are merged to form a pattern on the same mask (flow 6).

Next, the cell area 6 in each mesh area 14
Is oversized (enlarged) or undersized (reduced) according to Table 1 below. As a result, the occupancy of the A / A dummy pattern in each mesh area 14 is set to a desired value (flow 7).

[0081]

[Table 1]

As shown in Table 1, when the occupation ratio of the element formation region pattern 4 in each mesh region 14 is low, the cell region 6 having a high occupation ratio of the dummy pattern is arranged. If the occupancy is high, the cell region 6 having a low dummy pattern occupancy is arranged.

The above processing is performed by using the cell region 6 having a smaller pitch than the cell region 6 and a smaller pitch B (pitch A> pitch B).
This is performed for a, and a pattern is formed on the same mask. At this time, the dummy pattern occupancy in the cell region 6a is higher than the dummy pattern occupancy in the cell region 6.

As described above, by arranging the A / A dummy pattern having a desired occupancy according to the occupancy of each element forming region pattern (element pattern) 4, the A / A dummy pattern is covered over the entire semiconductor device. And the semiconductor device can be flattened.

The above flows 3 to 5 do not matter in any order, and flows 4 and 5 can be omitted. In addition, the deletion processing of each A / A dummy pattern may be performed by merging the element forming area pattern 4, the boundary of the well area 8, and the gate electrode 12 after desired sizing processing, and performing a batch processing. Also, the flows 1 and 7 may be performed in the order of the flows 1 and 7 after the flow 2 and are not limited to the order described above.

(Embodiment 4) Next, Embodiment 4 of the present invention will be described. In the third embodiment, A /
Although the arrangement of the dummy pattern in A has been described,
The idea of the third embodiment can be applied to a case where a dummy pattern is arranged around a wiring pattern such as a metal wiring.

First, as in the case of the third embodiment, CAD
The chip is divided into a plurality of mesh regions 14, and the pattern occupancy of the metal wiring pattern is determined for each of the mesh regions 14. The metal wiring pattern occupancy is determined by (area of metal wiring pattern in each mesh area 14) / (area of each mesh area 14) (flow 1).

Next, cell areas 6 having metal wiring dummy patterns are arranged in an array on the orthogonal pitch A grid on the entire surface of the CAD chip (flow 2). Then, the cell region 6 intersecting with the metal wiring pattern is deleted (flow 3). At this time, by applying a desired oversize to the metal wiring pattern, the separation between the metal wiring pattern and the metal wiring dummy pattern can be maintained.

The cell region 6 remaining after the above flow and the metal wiring pattern are merged to form a pattern on the same mask (flow 4).

Next, in the same manner as in the third embodiment, the cell regions 6 having the metal wiring dummy patterns having a desired occupancy are arranged in each mesh region 14 according to Table 2 below (flow 5).

[0091]

[Table 2]

The above flows 1 to 5 are performed for the cell region 6a having the pitch B (pitch A> pitch B), and a pattern is formed on the same mask (flow 6). At this time,
The metal wiring dummy pattern occupancy in the cell region 6a is set higher than the metal wiring dummy pattern occupancy in the cell region 6.

As described above, by arranging the metal wiring dummy patterns having the desired occupancy according to the occupancy of the metal wiring patterns (element patterns), the metal wiring dummy patterns can be comprehensively arranged over the entire semiconductor device. Thus, the semiconductor device can be planarized. The concept of the present embodiment can be applied to wiring patterns other than the metal wiring pattern.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described. In the fifth embodiment, the pattern occupancy of an element pattern such as an A / A pattern or a metal wiring pattern is obtained for each mesh region 14 in the third and fourth embodiments, and then the Fourier transform is performed to occupy the entire chip. Find the distribution.

Then, according to the occupancy distribution, a sizing process such as the flow 7 in the third embodiment or the flow 5 in the fourth embodiment is performed. This makes it possible to more effectively select and arrange the dummy patterns.

(Embodiment 6) Next, Embodiment 6 of the present invention will be described. In the sixth embodiment, the pattern occupancy of an element pattern such as an A / A pattern or a metal wiring pattern is determined for each mesh region 14 in the third and fourth embodiments. The mesh area 14 and the surrounding area n (for example, 2 or more and 1
A value obtained by averaging the occupancy of the mesh regions 14 (an integer of 0 or less) is obtained.

Then, according to the average occupancy, a sizing process such as the flow 7 in the third embodiment or the flow 5 in the fourth embodiment is performed. This makes it possible to more effectively select and arrange the dummy patterns.

(Seventh Embodiment) Next, a seventh embodiment of the present invention will be described. In the multilayer wiring process, wirings are stacked, so that a step in a lower layer is superimposed. Therefore, when regions with dense wiring or regions with sparse wiring are stacked, a serious step is generated.

Therefore, in the seventh embodiment, the occupancy rate of the element pattern in each mesh area 14 is obtained in the fourth to sixth embodiments, and the occupancy rate of the lower layer wiring under each mesh area 14 is calculated. Is added, and this value is set as the occupation ratio of each mesh area 14.

At the time of the addition, the occupancy of each mesh area 14 is multiplied by the following coefficient a. The coefficient a is determined by the remaining step of the lower layer wiring (step after flattening in the previous process) / the step of the wiring layer (thickness of the normal wiring layer).

Each mesh area 14 multiplied by the above coefficient a
According to the occupancy of the sizing process, the sizing process as in the flow 7 of the third embodiment or the flow 5 of the fourth embodiment is performed. This makes it possible to more effectively select and arrange the dummy patterns.

Embodiment 8 Next, Embodiment 8 of the present invention will be described. In the eighth embodiment, dummy patterns are arranged without obtaining the occupation ratio as described above.

The flow of the present embodiment is basically the same as the flows 1 to 6 of the first embodiment. However, in the present embodiment, the conditions for arranging the cell regions 6a having a small pitch are determined. It is more specifically defined than in the first embodiment.

That is, as shown in FIG. 17, the first dummy pattern 20 which is the n-th dummy pattern
The size of (rectangular or square) is dx1 × dy
The second dummy pattern 21 (which may be a rectangle or a square), which is a dummy pattern arranged at the (n + 1) th time, is set to 1.
Is the size of dx2 × dy2, the pitch of the first cell region 18 which is the cell region arranged at the n-th time is px1 × py1,
Second cell area 1 which is the cell area arranged at the (n + 1) th time
9 is px2 × py2, the A / A oversize when deleting the first cell area 18 is x1, and the second cell area 19 is
If the A / A oversize amount at the time of deletion is x2,
The first and second dummy patterns 20, 21 under the following conditions
Place.

The conditions are px1> px2, py1> py
2, px1-dx1-2 × x2 <dx2, py1-dy
1-2 × x2 <dy2, (dx1 × dy1) / (px1
× py1) <(dx2 × dy2) / (px2 × py2)
It is.

The area where the dummy pattern is not arranged at the n-th time is the area where the pattern is originally dense, or the pattern is sparse but arranged discretely and the dummy pattern size and the oversize amount at the time of deletion are large. Is a region where the occupation rate of the dummy pattern is low.

Therefore, by arranging the dummy patterns of the (n + 1) th and subsequent times under the above-described conditions, the dummy patterns can be arranged in a region where the occupancy of the dummy pattern is low as in the latter case. The pattern occupancy can be increased.

As described above, when arranging the dummy pattern in several stages, the cell region having a high occupancy should be arranged at a place where the dummy pattern is not occupied in the previous stage and having a low occupancy. Thus, the A / A dummy pattern can be comprehensively arranged over the entire semiconductor device, and the semiconductor device can be flattened. Further, the CAD processing time can be reduced.

(Embodiment 9) The arrangement of the dummy pattern 5 in A / A has been described in Embodiment 8 above, but the idea of Embodiment 8 can be applied to a wiring pattern forming step of metal wiring or the like.

The metal wiring dummy patterns are arranged in an array on the grid of orthogonal pitch A on the entire surface of the CAD chip (flow 1), and the metal wiring dummy cells intersecting the metal wiring patterns are deleted (flow 2). At this time, a desired oversize is applied to the metal wiring pattern to ensure separation between the metal wiring pattern and the metal wiring dummy pattern.

The metal wiring dummy cells remaining after the above flow and the desired metal wiring pattern are merged to form a pattern on the same mask (flow 3).

The above flows 1 to 3 are performed for the narrow pitch cell region 6a having the metal wiring dummy pattern having a smaller area, and a pattern is formed on the same mask (flow 4). At this time, metal wiring dummy patterns are arranged under the same conditions as in the eighth embodiment.

As a result, similar to the eighth embodiment, the metal wiring dummy pattern can be comprehensively arranged on the entire semiconductor device, and the semiconductor device can be flattened. Further, the CAD processing time can be reduced.

The features of each of the above embodiments can be appropriately combined. The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0115]

As described above, according to the present invention,
Since the dummy patterns can be arranged over the entire semiconductor device, the flatness of the semiconductor device can be improved. Further, since the CAD processing time for arranging the dummy patterns can be reduced and the CAD processing capacity can be reduced, a plurality of types of dummy patterns having different pitches can be automatically arranged.

[Brief description of the drawings]

FIG. 1 is a diagram showing a state in which a cell region having a dummy pattern is regularly arranged on an orthogonal grid in the semiconductor device of the first embodiment;

FIG. 2 is an enlarged view of a region 7 in FIG.

FIG. 3 is a diagram showing an example in which a plurality of rectangular dummy patterns are arranged in a cell region.

FIG. 4 is a diagram showing another example in which a plurality of rectangular dummy patterns are arranged in a cell region.

FIG. 5 is a diagram showing another example in which a plurality of rectangular dummy patterns are arranged in a cell region.

FIG. 6 is a diagram showing another example in which a plurality of rectangular dummy patterns are arranged in a cell region.

FIG. 7 is a diagram schematically showing a CAD flow 1 according to the first embodiment.

FIG. 8 is a diagram schematically showing a CAD flow 2 according to the first embodiment.

FIG. 9 is a diagram schematically showing a CAD flow 3 according to the first embodiment.

FIG. 10 is a diagram schematically showing a CAD flow 4 according to the first embodiment.

FIG. 11 is a diagram schematically showing a CAD flow 5 according to the first embodiment.

FIG. 12 is a plan view of a semiconductor device having a dummy pattern according to a second embodiment of the present invention.

FIG. 13 is a cross-sectional view of the semiconductor device shown in FIG.
It is a line sectional view.

FIG. 14 is a diagram schematically showing a CAD flow 1 according to the third embodiment.

FIG. 15 is a diagram for explaining a convex portion occupation ratio of the present invention.

FIG. 16 is a diagram for explaining the convex portion occupancy of the present invention.

FIGS. 17A and 17B are diagrams for explaining a characteristic flow in the eighth embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a state where an insulating film for forming an isolation insulating film is formed in a conventional semiconductor device having no dummy pattern.

FIG. 19 is a diagram showing a state in which an isolation insulating film is formed by CMP in a conventional semiconductor device having no dummy pattern.

FIG. 20 is a cross-sectional view showing a state in which an insulating film for forming an isolation insulating film is formed in a conventional semiconductor device having a dummy pattern.

FIG. 21 is a diagram showing a state in which an isolation insulating film is formed by CMP in a conventional semiconductor device having a dummy pattern.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate, 2 insulating film, 2a isolation insulating film, 3
Element isolation region, 4 element formation region pattern, 5 dummy pattern, 5a first A / A dummy pattern, 5b second A / A dummy pattern, 6, 6a cell region, 7,
9, 60 regions, 8 wells, 11 gate insulating film, 1
2 gate electrode, 13a first gate dummy pattern,
13b Second gate dummy pattern, 14 mesh region, 15 trench, 16 buried insulating film, 17 active region, 18 first cell region, 19 second cell region, 20
First dummy pattern, 21 Second dummy pattern.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court ゛ (Reference) H01L 21/822 (72) Inventor Tsuyoshi Kitani 2-3-2 Marunouchi 2-chome, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation (72) Inventor Motoshige Igarashi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation F-term (reference) 5B046 AA08 BA05 5F032 AA34 AA44 AA77 AA84 BA02 BA05 CA16 DA00 DA78 DA80 5F033 HH00 UU03 VV02 XX01 5F038 CA02 CA17 CA18 CD10 EZ20 5F064 BB35 CC09 DD01 DD10 DD13 DD14 DD24 DD50 EE22 EE56 HH06

Claims (17)

[Claims] An element pattern formed on a semiconductor substrate; a first dummy pattern arranged on the same layer as the element pattern; a pitch different from the first dummy pattern arranged on the same layer as the element pattern. A second dummy pattern of
A semiconductor device comprising: 2. The device pattern according to claim 2, wherein the element pattern includes an element formation region pattern formed on the semiconductor substrate by an element isolation region, and the first and second dummy patterns are arranged in the element isolation region. 2. The semiconductor device according to 1. 3. The semiconductor according to claim 1, wherein the element pattern includes a wiring pattern formed on the semiconductor substrate, and wherein the first and second dummy patterns are arranged around the wiring pattern. apparatus. 4. A plurality of mesh regions on a semiconductor substrate, an element pattern located in the mesh region, and an occupancy according to an occupancy of the element pattern, which is an area of the element pattern with respect to an area of the mesh region. A dummy pattern arranged in the mesh region so that 5. The semiconductor device according to claim 4, wherein said dummy pattern includes first and second dummy patterns having different pitches. 6. A method for arranging a dummy pattern in a semiconductor device comprising a first dummy pattern having a relatively large pitch and a second dummy pattern having a relatively small pitch arranged in the same layer, A method of arranging dummy patterns, wherein the arrangement of one dummy pattern and the arrangement of the second dummy pattern are performed in different steps. 7. The semiconductor device according to claim 1, wherein the first and second dummy patterns are arranged in an element isolation region of the semiconductor device, wherein the element isolation region includes a first region in which the first dummy pattern is arranged, and a second dummy pattern. And a second region in which the second dummy pattern is arranged in the first region, and then the second dummy pattern is arranged in the second region. Placement method. 8. The semiconductor device according to claim 1, wherein the first and second dummy patterns are arranged around a wiring pattern of the semiconductor device, wherein the area around the wiring pattern is a first area in which the first dummy pattern is arranged; 7. A second area in which a second dummy pattern is arranged, wherein the second dummy pattern is arranged in the second area after the first dummy pattern is arranged in the first area. 8. How to place dummy patterns. 9. The first dummy pattern includes a first upper layer dummy pattern and a first lower layer dummy pattern, and the second dummy pattern includes a second upper layer dummy pattern and a second lower layer dummy pattern. 9. The arrangement of the dummy pattern according to claim 6, wherein the arrangement data of the first and second lower-layer dummy patterns is diverted as the arrangement data of the first and second upper-layer dummy patterns. Method. 10. The first dummy pattern is disposed in a first cell region, the second dummy pattern is disposed in a second cell region, and the pitch of the first cell region is the pitch of the second cell region. 10. The occupancy of the second dummy pattern in the second cell region is higher than that of the first dummy pattern in the first cell region. The method of arranging the dummy pattern described in Crab 11. A step of dividing a semiconductor chip region into a plurality of mesh regions; and a step of dividing the mesh region based on a first occupation ratio, which is an area of an element pattern located in the mesh region with respect to an area of the mesh region. Determining a second occupancy that is an area of the dummy pattern to be arranged in the mesh area with respect to an area; Arranging the dummy pattern in an area. 12. The method according to claim 11, wherein the step of arranging the dummy pattern includes the step of adjusting the size of the dummy pattern such that the occupancy of the dummy pattern in the mesh area becomes the second occupancy. How to place the described dummy pattern. 13. The step of determining the second occupancy includes the step of obtaining the first occupancy, and then performing a Fourier transform to obtain an occupancy distribution of the entire semiconductor chip area. The method of arranging a dummy pattern according to claim 11, wherein the step includes arranging the dummy pattern according to the occupancy distribution. 14. The step of determining the second occupancy rate comprises the steps of: obtaining the first occupancy rate for each of the mesh areas; and calculating an average occupancy rate of the occupancy rates of the plurality of mesh areas. 13. The dummy pattern arranging method according to claim 11, wherein the arranging step of the dummy pattern includes arranging the dummy pattern according to the average occupancy. 15. The dummy pattern arranging method according to claim 11, wherein the second occupancy is reduced as the one occupancy is increased. 16. The method according to claim 11, wherein the step of determining the second occupancy includes the step of adding the first occupancy in a lower layer to obtain the second occupancy. How to place dummy patterns. 17. The semiconductor device according to claim 17, wherein the first dummy pattern is disposed in a first cell region, the second dummy pattern is disposed in a second cell region, and the pitch of the first cell region is equal to that of the second cell region. The occupancy of the second dummy pattern in the second cell region is larger than the pitch, and is higher than the occupancy of the first dummy pattern in the first cell region.
7. The method for arranging dummy patterns according to any one of 6.