JP2001142703A - Microcomputer and method for controlling conditional branch instruction fetch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer and a conditional branch instruction fetch control method which prevent deterioration in execution performance caused by the time loss of the microcomputer due to a branch instruction by predicting the branch instruction destination of a conditional branch instruction and controlling a next instruction code in instruction fetch operation after the branch instruction code. SOLUTION: The addresses of branch instructions which were executed in the past and a history counter are recorded in a branch information RAM 13 and when a branch instruction is detected at instruction fetch time, a predicted branch-destination address is set in a program fetch counter 8 by the branch information RAM 13 and a large/small decision circuit 17. Consequently, when the branch prediction coincides and when an unconditional branch instruction is executed, the microcomputer continuously operates without making the instruction code in an instruction queue 3 by the branch instruction ineffective.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer technology, and more particularly to a microcomputer using a branch instruction by predicting a branch instruction destination of a conditional branch instruction and controlling the next instruction code by an instruction fetch operation after the branch instruction code. The present invention relates to a microcomputer and a conditional branch instruction fetch control method for preventing a decrease in execution performance caused by a computer time loss.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram of a microcomputer 504 of the first prior art. In the microcomputer 504 of the first related art shown in FIG. 9, an instruction code is read (instruction fetch) from the program storage memory 500 and stored in the instruction queue 501. While the instruction decoder 502 to be processed next is operating, the instruction fetch is repeated, and when the instruction decoder 502 ends the processing,
According to the order of instruction fetch in the instruction queue 501,
Decoded by the instruction decoder 502, the instruction execution unit 503
The instruction is executed via.

In recent years, with the increase in the speed of microcomputer processing, the technology described in Japanese Patent Application Laid-Open No. 1-193939 (second conventional technology) and the technology described in Japanese Patent Application Laid-Open No. 4-195630 (third conventional technology) have been proposed. ), A circuit for operating a microcomputer based on the above circuit at high speed has been proposed. Next, they will be described.

FIG. 10 is a block diagram of a circuit for increasing the speed of a microcomputer for unconditional branches described in Japanese Patent Application Laid-Open No. 1-193939 (second prior art). Referring to FIG. 10, the instruction storage memory 101
Is a memory for storing the instruction code 102. Each instruction code 102 has, separately from the instruction code 102, a branch instruction detection flag 103 indicating that the instruction code is a branch instruction code, and is "1" for a branch instruction and "0" for other instructions.
Is set to The instruction queue 109 is connected to the data bus 1
04 and the instruction storage memory 1 via the input port 105
Instruction codes 102 are stored sequentially from 01. The queue counter 110 is a counter for indicating the instruction code storage state of the instruction queue 109 by a counter value, and is input to the instruction fetch request control circuit 111. When the instruction code 102 is stored in the instruction queue 109, the branch instruction detection flag 103 is input to the flip-flop 113 via the branch instruction detection signal line 106. Flip-flop 11
3 and the result inverted by the inverter 116 and the output from the instruction fetch request control circuit 111 are ANDed by the AND gate 112, and the fetch request signal 11
4. Input to the instruction fetch circuit 115.

Next, the operation of the second prior art will be described with reference to FIG. First, the instruction code 102 is transmitted from the instruction storage memory 101 to the data bus 104 and the input port 10.
5 is stored in the instruction queue 109 and output to the instruction decoder. The queue counter 110 stores the instruction queue 10
9 has an empty space, the instruction fetch request control circuit 111
"1", and "0" otherwise.

When an instruction code 102 other than an unconditional branch instruction is fetched into the instruction queue 109, the branch instruction detection signal line 106 becomes "0". The input from the inverter 116 to the AND gate 112 becomes “1”, and the instruction fetch circuit 115 performs an instruction fetch operation according to the input from the instruction fetch request control circuit 111.

When an unconditional branch instruction code is fetched into the instruction queue 109, the branch detection signal line 10
6 becomes “1”. The flip-flop 113 is set to “1”, and the inverter 116 supplies the AND gate 112
Becomes "0", the instruction fetch request signal 114 becomes "0" regardless of the input from the instruction fetch request control circuit 111. From the above, the instruction fetch circuit 1
Reference numeral 15 denotes a state in which the instruction fetch operation is stopped, and an unconditional branch instruction code is fetched into the instruction queue 109. Thereafter, while the instruction fetch operation is stopped, the instruction codes 102 in the instruction queue 109 are sequentially executed,
When the unconditional branch instruction is executed, the instruction fetch operation is resumed, and the branch destination instruction code 102 is fetched.

Since the instruction code 102 has not been fetched from the instruction fetch of the unconditional branch instruction until the instruction is executed, the microcomputer does not execute the instruction.

FIG. 11 is a block diagram showing the internal configuration of an instruction fetch unit described in Japanese Patent Application Laid-Open No. 4-195630 (third prior art). Referring to FIG. 11, an instruction fetch unit described in the third related art includes an instruction code 202A fetched from an external memory, a branch initialization signal 205B at the time of a branch instruction, a CAM 206 of a comparison circuit,
A CA bus 261 for outputting a branch destination address of a branch instruction;
It has a branch instruction detection flag 206A indicating that a branch instruction has been fetched, an instruction queue 207, a selector 207A, and a branch destination address registration memory 208A for registering past branch destination addresses.
6, and can be compared.

Reference numeral 208B denotes a branch destination address registration memory 20
A branch instruction registration memory for registering a branch instruction corresponding to 8A, 208C is an address mismatch signal, 208D is a hit signal for outputting the result of comparison between the value of the CA bus 261 and the branch destination address registration memory 208A, and 209 is a branch destination address registration Memory 208A and branch instruction registration memory 208
A registration valid flag indicating whether the memory indicated by B is valid or invalid, 21
0 is an address counter indicating the address of the instruction to be fetched.

Next, the operation of the third prior art will be described. In the present embodiment, when the instruction fetch is started from the external memory after the reset, the instruction code 202A is input to the instruction queue 207 via the selector 207A,
At the same time, it is also input to CAM 206,
The code of the unconditional branch instruction registered in 06 is compared with the input code.

This comparison operation is repeated every time an instruction is fetched. When the comparison is performed by the CAM 206 and the unconditional branch instruction is fetched for the first time, the branch instruction detection flag 206A is set and registered in the branch destination address registration memory 208A. Thereafter, when the unconditional branch is executed, the instruction queue 207 is initialized by the branch initialization signal 205B.

Next, the operation of the third prior art in the case where a previously executed unconditional branch instruction is fetched from an external memory will be described. As soon as the unconditional branch instruction is fetched into the instruction queue 207, the CAM 206
Is entered and compared with the registered code. The branch instruction detection flag 206A is set, and the branch destination instruction is read from the registered branch destination address registration memory 208A and the registered branch instruction registration memory 208B. By incrementing the read address of the branch destination address registration memory 208A and outputting it to the address counter 210, the instruction next to the branch destination instruction is fetched.

On the other hand, the branch destination instruction read from the branch instruction registration memory 208B is input to the instruction queue 207 via the selector 207A. Thereby, the instruction queue 2
Instruction code 2 of unconditional branch without initializing 07
02A executes instructions continuously.

[0015]

However, when a branch instruction is executed in the above-mentioned prior art microcomputer, the instruction code in the instruction queue is invalidated and the instruction code of the branch instruction destination is fetched again. However, there is a problem that a time loss occurs and the processing performance decreases.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and an object of the present invention is to predict a branch instruction destination of a conditional branch instruction and to execute the next instruction code by an instruction fetch operation after the branch instruction code. It is another object of the present invention to provide a microcomputer and a conditional branch instruction fetch control method for controlling the microcomputer to prevent a decrease in execution performance caused by a time loss of the microcomputer due to the branch instruction.

[0017]

The gist of the present invention is that an instruction queue for storing an instruction code, an instruction fetch unit for fetching an instruction, an instruction decoder unit for decoding an instruction code, and an instruction Execution performance that has an operation / instruction execution unit to execute, predicts the branch instruction destination of a conditional branch instruction, and controls the next instruction code in the instruction fetch operation after the branch instruction code, thereby causing the microcomputer to lose time due to the branch instruction A program counter value of a branch instruction executed in the past, a branch instruction destination address for the branch instruction, and a history counter value indicating the number of times of branching to the branch destination are recorded as conditional branch information. The present invention resides in a microcomputer having means. According to another aspect of the present invention, there is provided a means for detecting a branch instruction by comparing a program counter value of the branch instruction, which is branch information, with a prefetch counter value during a prefetch operation to the instruction queue. The microcomputer according to claim 1, wherein: The gist of the invention described in claim 3 is that, when the conditional branch instruction is prefetched into the instruction queue, a branch predicting circuit for predicting a conditional branch destination address to branch this time based on the conditional branch information is provided. A microcomputer according to claim 1 characterized by the above-mentioned. According to a fourth aspect of the present invention, there is provided the microcomputer according to the third aspect, wherein the branch prediction circuit includes a unit that predicts a branch destination from a branch feature of a program using conditional branch. . The gist of the invention described in claim 5 is that
It has an instruction queue for storing instruction codes, an instruction fetch unit for fetching instructions, an instruction decoder unit for decoding instruction codes, and an operation / instruction execution unit for executing instructions, and predicts a branch instruction destination of a conditional branch instruction. A program counter for a previously executed branch instruction for a microcomputer that controls the next instruction code in the instruction fetch operation after the branch instruction code to prevent the microcomputer from deteriorating execution performance caused by the time loss of the microcomputer due to the branch instruction A conditional branch instruction fetch control method characterized by comprising a step of recording, as conditional branch information, a value, a branch instruction destination address for the branch instruction, and a history counter value indicating the number of branches to the branch destination. The gist of the invention described in claim 6 includes a step of detecting a branch instruction by comparing a program counter value of the branch instruction, which is branch information, with a prefetch counter value during a prefetch operation to the instruction queue. A conditional branch instruction fetch control method according to claim 5, characterized in that: The gist of the invention described in claim 7 is that, when the conditional branch instruction is prefetched into the instruction queue, a branch prediction step of predicting a conditional branch destination address to branch this time based on the conditional branch information is provided. A conditional branch instruction fetch control method according to claim 5 is provided. The gist of the invention described in claim 8 is that the branch predicting step is characterized by the following:
8. The method according to claim 7, further comprising a step of predicting a branch destination.

[0018]

SUMMARY OF THE INVENTION An object of the present invention is to prevent a decrease in execution performance caused by a time loss of a microcomputer due to a branch instruction, and to provide a branch information RAM for recording branch information and a prediction of a branch destination. The circuit is characterized by predicting a branch instruction destination of a conditional branch instruction and controlling the next instruction code by an instruction fetch operation after the branch instruction code.

The branch information RAM records the program counter value, the branch destination address, the history counter, and the determination result information of the conditional branch instruction executed in the past as branch information in the branch information RAM. When the conditional branch instruction is fetched, the magnitude determining circuit determines whether or not the branch instruction address R, which is the aforementioned branch information,
The branch destination address of the conditional branch instruction is predicted using the AM and the history counter, and the branch destination address is set in the program fetch counter. As a result, the instruction code following the branch instruction code is fetched with the instruction code of the branch instruction destination in the instruction queue 3 (PreFetch Memory), and there is no need to re-fetch the instruction after executing the branch instruction. This makes it possible to execute the processing. Hereinafter, various embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a system configuration diagram of a microcomputer 30 according to the first embodiment of the present invention. In FIG. 1, 1 is a data bus (Data Bus), 2 is an address bus (Address Bus), 3 is an instruction queue (PreFetch Memory), 4 is an instruction fetch unit (Fetch), and 5 is an instruction decoder unit (Decode).
e) and 6 are operation / instruction execution units (ALU), 7 is a program counter (PC), 8 is a program fetch counter (PFC), 9 is a table detection circuit, 10 is a selector (SEL), and 11 is a branch instruction address RAM. , 12 are branch destination address latch circuits, 13 is branch information RAM, 14
Is a history counter, 15 is a selector (SEL), 16 is P
FC branch PC value comparison circuit, 17 is a magnitude judgment circuit, 18 is a selector (SEL), 19 is judgment result information, 20 is a branch destination comparison circuit, and 30 is a microcomputer.

Referring to FIG. 1, a microcomputer 30 of the present embodiment has an address bus 2 (AddressBus) connected to a memory storing a program.
s), a data bus 1 (DataBus), and an instruction queue 3 (PreF
etch Memory) and the instruction fetch unit 4 (Fe
tch), an instruction decoder unit 5 (Decode), an operation / instruction execution unit 6 (ALU), and a program counter 7
(PC) and instruction queue 3 (PreFetchMemo)
ry) stores a program fetch counter 8 (PFC) for outputting an address of an instruction code to be fetched to the address bus 2 (Address Bus) and a branch destination address of a branch instruction decoded by the instruction decoder unit 5 (Decode). A branch destination address latch circuit 12, a magnitude determination circuit 17, a PFC branch PC value comparison circuit 16, a table detection circuit 9, a branch instruction address RAM 11,
Determination result information 1 indicating the history counter 14 and the previous branch destination
9, a branch information RAM 13 and a branch destination comparison circuit 20.

The branch information RAM 13 stores a program counter value (PC value) of a previously executed branch instruction, an address of a branch destination, a history counter 14 indicating the number of branches, and a RAM for recording branch information including determination result information 19. Write / read memory as needed).

The magnitude determination circuit 17 controls the selector 18 (SEL) to set the predicted branch destination address in the program fetch counter 8 (PFC). In the case of the switching, the history counter 14 of the branch information RAM 13 detects, in the case where the number of times of branching in the past is equal, or the difference of the number of times of branching is within 1, detects a branch destination address opposite to the previously predicted branch destination address in the table. The selector 18 (SEL) is switched so that the circuit 9 is also set. In other cases, the selector 18 (SEL) is switched so that a branch destination address having a large number of branches in the past is set in the program fetch counter 8 (PFC). At the same time as the selector 18 (SEL) is switched, the magnitude determination result is recorded in the determination result information 19.

When the branch instruction is executed, the table detection circuit 9 compares the current program counter value (PC value) with the branch program address (PC value) in the branch instruction address RAM 11.
Value). If they match, the branch destination history counter 14 is incremented. If they do not match, the current program counter value (PC value) and the branch destination address latched by the branch destination address latch circuit 12 are recorded in the branch information RAM 13, the history counter 14 is initialized, and the branch destination history counter 14 Is incremented.

The PFC branch PC value comparison circuit 16 compares the current program fetch counter value (PFC value) with the branch instruction address RAM 11 of the branch information RAM 13. As a result of the comparison, if they match, the branch destination address selected from the branch information RAM 13 by the magnitude determination circuit 17 is set in the program fetch counter 8 (PFC).
If they do not match, the current value of the program fetch counter 8 (PFC) is incremented.

When the conditional branch instruction is executed by the operation / instruction execution unit 6 (ALU), the branch destination comparing circuit 20 determines the branch result obtained by predicting the conditional branch instruction at the time of prefetching. Compare the execution results of the branch instructions. Only when the comparison result does not match, the instruction decoder unit 5
(Decode), instruction fetch unit 4 (Fetch) and instruction queue 3 (PreFetch Memory)
Is set, and the branch destination address of the conditional branch instruction is set in the program fetch counter 8 (PFC).

Next, the main operation of this embodiment will be described with reference to FIG. Referring to FIG. 1, in the present embodiment, a program counter value (PC value) indicated by a program fetch counter 8 (PFC) is stored in an address bus 2 (Adr).
essBus), and the instruction code stored at the address is stored in the instruction queue 3 (PreFetch Memory) via the data bus 1 (DataBus).
Is prefetched to Each time, the program fetch counter 8 (PFC) sets the address bus 2 (AddressBus).
s), every time the program counter value (PC value) is output, the PFC branch PC value comparison circuit 16 compares the program counter value (PC value) in the branch instruction address RAM 11 with the value of the program fetch counter 8 (PFC). . Subsequently, the instruction queue 3 (PreFetch Mem)
ory) from the instruction fetch unit 4 (Fetc)
h), it is input to the instruction decoder unit 5 (Decode), decoded, and executed by the operation / instruction execution unit 6 (ALU).

As a series of detailed processes, there are a process of acquiring branch information used for branch prediction, a process of performing branch destination prediction, and a process of confirming branch prediction. The respective operations will be described below.

First, the process of acquiring branch information will be described with reference to FIG. FIG. 2 is a block diagram of a circuit related to branch information acquisition of the microcomputer 30 according to the first embodiment of the present invention. Only blocks necessary for branch information acquisition are selected from the block diagram shown in FIG. FIG. First, the conditional branch instruction is decoded by the instruction decoder unit 5 (Decode), and the operation
The operation when executed by the instruction execution unit 6 (ALU) will be described.

Referring to FIG. 2, in the present embodiment, when the instruction code decoded by the instruction decoder unit 5 (Decode) is determined to be a conditional branch instruction, the instruction code is decoded by the branch destination address latch circuit 12. The conditional branch destination address is latched. The conditional branch instruction is executed by the operation / instruction execution unit 6
(ALU), the table detection circuit 9 compares the program counter value (PC value) of the conditional branch instruction in the branch instruction address RAM 11 with the current program counter 7
Compare the value of (PC).

As a result of the comparison, if the program counter value (PC value) does not match, that is, if a conditional branch instruction that has not been executed before is executed, the current program counter value (PC value) is branched. The branch destination program counter value (PC value) latched in the destination address latch circuit 12 is stored in the branch instruction address RAM 11 of the branch information RAM 13 and the branch destination program counter value (PC value).
Value). At the same time, the corresponding history counter 14 is cleared, and the history counter 14 at the branch destination this time is counted up. Through this series of processing, information necessary for predicting the conditional branch instruction destination address is newly recorded in the branch information RAM 13.

On the other hand, when the comparison results of the table detection circuit 9 match, the history counter 14 corresponding to the program counter value (PC value) of the matching branch instruction is incremented. As a result, information necessary for predicting the branch destination of the conditional branch instruction is recorded.

Next, the operation of performing branch prediction will be described with reference to FIG. FIG. 3 is a block diagram of a circuit relating to branch prediction of the microcomputer 30 according to the first embodiment of the present invention, in which only blocks necessary for branch prediction are selected from the block configuration diagram shown in FIG. It is a block diagram. With reference to FIG. 3, in the present embodiment, the program fetch counter 8 (PFC)
(AddressBus) contains the program counter value (PC
Each time the value is output, the PFC branch PC value comparison circuit 16 is used to compare the program counter value (PC value) in the branch instruction address RAM 11 with the current value of the program fetch counter 8 (PFC).

If the comparison results by the PFC branch PC value comparison circuit 16 match, the matched branch instruction address RA
The value of the history counter 14 corresponding to the program counter value (PC value) of M11 is input to the magnitude determination circuit 17.

Subsequently, using the magnitude determination circuit 17, the predicted branch destination address in the branch information RAM 13 is set in the program fetch counter 8 (PFC) by controlling the selector 18 (SEL). I do. At the same time, the result predicted by the magnitude determination circuit 17 is also recorded in the determination result information 19.

If the comparison result by the PFC branch PC value comparison circuit 16 does not match, the current value of the program fetch counter 8 (PFC) is incremented. As a result, the predicted instruction code of the branch destination is instruction-fetched to the instruction code following the conditional branch instruction, and if the prediction matches when the conditional branch instruction is executed, the instruction code of the branch destination is continuously fetched without fetching. The microcomputer 30 can operate.

Next, the operation of confirming the branch prediction will be described with reference to FIG. Referring to FIG. 3, in the present embodiment,
Each time a conditional branch instruction is executed, the previous branch destination prediction result recorded in the corresponding determination result information 19 and the current branch result of the conditional branch instruction are compared by the branch destination comparison circuit 20.

When the comparison result by the branch destination comparison circuit 20 does not match, that is, when the program counter value (PC value) of the branch destination predicted by the magnitude judgment circuit 17 differs from the branch destination address of the conditional branch instruction, Instruction decoder unit 5 (Decode), instruction fetch unit 4 (Fetc)
h) and instruction queue 3 (PreFetch Mem)
The instruction code in (ory) is invalidated, and the program counter value (PC value) of the branch destination indicated by the conditional branch instruction is set in the program fetch counter 8 (PFC).

Next, the operation when the conditional branch instruction recorded in the branch information RAM 13 is executed according to the program flow shown in FIG. 6 will be described with reference to the timing charts of FIGS. FIG. 6 is a flowchart for explaining the operation of the conditional branch instruction fetch control method according to the present invention. Referring to FIG. 6, in the present embodiment, the instruction codes indicated by,,, I, II, and III are instruction codes other than the conditional branch instruction code, and the instruction codes are conditional branch instruction codes. When the conditional branch instruction is executed, if the branch condition is satisfied, the process branches to the instruction code indicated by I and executes the instruction. If the branch condition is not satisfied, the process branches to the instruction code indicated by で and executes the instruction.

FIG. 4 is a timing chart at the time of branch prediction matching according to the conditional branch instruction fetch control method according to the present invention, showing a case where the branch prediction matches the execution result of the conditional branch instruction. When the conditional branch instruction indicated by the cycle T2 is fetched, the instruction code indicated by I predicted by the magnitude determination circuit 17 is fetched in the cycle T3.

Subsequently, the conditional branch instruction code shown in cycle T4 is executed, and when it is determined, using the branch destination comparison circuit 20, that the branch destination address matches the address of the branch destination code shown by I. , Microcomputer 3
0 executes the instruction continuously in cycle T5, cycle T6, and cycle T7.

FIG. 5 is a timing chart of the conditional branch instruction fetch control method according to the present invention when the branch prediction does not match. Shows the timing of the operation. Referring to FIG. 5, in the present embodiment, when the conditional branch instruction indicated by cycle T2 is fetched, in cycle T3, the instruction code predicted by the magnitude determination circuit 17 is fetched.

The conditional branch instruction code shown in cycle T4 is executed, and it is determined that the branch destination address does not match the address of the instruction code shown by the branch destination comparison circuit 20. I
The instruction code is re-fetched for the branch instruction code indicated by. As a result, the instruction code fetched in the cycles T3 and T4 is not executed in the cycles T5 and T6, but starts executing the instruction indicated by the conditional branch destination I in the cycle T7.

In the above description of the operation, the case where the conditional branch instruction is executed has been described. However, since the present embodiment corresponds to an unconditional branch instruction, the operation is different from that of the conditional branch instruction. Only the part is described.

The first different operation is an operation of recording the program counter value (PC value) of the branch destination from the branch destination address latch circuit 12 to the branch information RAM 13. While there are two branch destinations for the conditional branch instruction, there is one branch destination for the unconditional branch instruction. Therefore, the branch information RAM1
3 are the program counter values of two branch destinations (PC
Value) is recorded in one of the RAMs.

In order to prevent the above uncertainty, in the case of an unconditional branch instruction, the program counter value (PC value) of the branch destination of the unconditional instruction is recorded in both of the RAMs. As a second different operation, in the case of an unconditional branch, the history counter 14
Is performed on only one of the counters.

Although there is a difference between the first and second operations described above, the same branch prediction operation as that of the conditional branch instruction always causes the result of the branch prediction by the magnitude judgment circuit 17 to be always the unconditional branch destination program counter value. (PC value) by selecting the program fetch counter 8 (PFC),
The instruction code at the branch destination is fetched into the code following the unconditional branch instruction code.

(Second Embodiment) Next, a second embodiment aiming at improving the accuracy of branch prediction will be described with reference to FIG. Note that the same parts as those already described in the above embodiment are denoted by the same reference numerals, and redundant description will be omitted. FIG. 7 is a system configuration diagram of a microcomputer 30 according to the second embodiment of the present invention.

In FIG. 7, reference numeral 1 denotes a data bus (Data).
Bus), 2 is an address bus (Address Bus),
3 is an instruction queue (PreFetch Memory),
4 is an instruction fetch unit (Fetch), 5 is an instruction decoder unit (Decode), and 6 is an operation / instruction execution unit (AL).
U), 7 are a program counter (PC), 8 is a program fetch counter (PFC), 9 is a table detection circuit, 10 is a selector (SEL), 11 is a branch instruction address RAM, 12 is a branch destination address latch circuit, 13 is Branch information RAM, 15 is a selector (SEL), 16 is PF
C branch PC value comparison circuit, 18 is a selector (SEL), 1
Reference numeral 9 denotes judgment result information, 20 denotes a branch destination comparison circuit, 21 denotes a prediction circuit, 22 denotes history information, and 30 denotes a microcomputer.

Referring to FIG. 7, this embodiment is different from the first embodiment in that the history counter 14 and the magnitude judgment circuit 17 are changed to history information 22 and a prediction circuit 21. Has features. In the history information 22, branch destinations of conditional branch instructions executed in the past are recorded in the order of execution, and instead of the magnitude judgment by the magnitude judgment circuit 17,
By predicting the branch tendency from the past branch history by the prediction circuit 21, an effect is obtained that the prediction result of the conditional branch instruction can be made higher in probability.

(Third Embodiment) Next, a third embodiment aiming at making the circuit configuration smaller will be described with reference to FIG. Note that the same parts as those already described in the above embodiment are denoted by the same reference numerals, and redundant description will be omitted. FIG. 8 shows a third embodiment of the present invention.
FIG. 2 is a system configuration diagram of a microcomputer 30 according to the embodiment.

In FIG. 8, reference numeral 1 denotes a data bus (Data).
Bus), 2 is an address bus (Address Bus),
3 is an instruction queue (PreFetch Memory),
4 is an instruction fetch unit (Fetch), 5 is an instruction decoder unit (Decode), and 6 is an operation / instruction execution unit (AL).
U), 7 are a program counter (PC), 8 is a program fetch counter (PFC), 9 is a table detection circuit, 10 is a selector (SEL), 11 is a branch instruction address RAM, 12 is a branch destination address latch circuit, 13 is Branch information RAM, 14 is a history counter, 15 is a selector (SEL), 16 is a PFC branch PC value comparison circuit, 17 is a magnitude judgment circuit, 18 is a selector (SEL), 19 is judgment result information, and 20 is a branch destination comparison circuit. , 30 indicate a microcomputer.

In this embodiment, in the location of the program instruction code, of the two branch destinations of the conditional branch instruction,
Instructions subsequent to one of the branch conditions that are satisfied or not satisfied are sequentially arranged. In the following description, a case will be described in which the instruction code at the time of branch establishment is continuously arranged after the branch instruction.

As operations different from those in the first embodiment, only the operation of selecting a branch destination address in branch prediction and the operation of recording a branch destination address from the branch destination address latch circuit 12 to the branch information RAM 13 will be described.

Referring to FIG. 8, in the present embodiment, when the instruction code decoded by instruction decoder unit 5 (Decode) is determined to be a conditional branch instruction, it is decoded by branch destination address latch circuit 12. , The condition branch destination address when the branch is not taken is latched.

The magnitude determination circuit 17 controls the selector 18 (SEL) to store the predicted branch destination address in the branch information RAM 13 or the current incremented address of the program fetch counter 8 (PFC) to control the program fetch counter 8. (PFC).

By changing the above processing from the first embodiment, it is possible to delete one RAM (random write / read memory) for recording the program counter value (PC value) of the branch destination from the branch information RAM 13. This makes it possible to reduce the size of the circuit.

As described above, according to the above embodiments, the following effects can be obtained. First, the first effect is
When the branch prediction by this circuit coincides with the execution of a conditional branch instruction, there is no need to fetch useless instructions other than the execution of the branch instruction, so that the instructions can be fetched efficiently. The reason is that, when the conditional branch instruction is prefetched, the branch destination address is predicted from the branch information RAM 13 and the size determination circuit 17, and the prefetch operation is controlled so as to prefetch the instruction code stored in the branch destination address. is there.

The second effect is that not only unconditional branch but also conditional branch instruction can be predicted.
The reason is that the program counter value (PC value) of the previously executed conditional branch instruction and unconditional branch instruction, the program counter value (PC value) of the branch destination, the history counter 14 indicating the number of past branches, and the judgment result information 19 The branch history information 22 required for branch prediction is stored in a branch information RAM.
13 is recorded.

It should be noted that the present invention is not limited to the above embodiments, and it is clear that each embodiment can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0061]

Since the present invention is configured as described above, the following effects can be obtained. First, the first effect is that when the branch prediction by the present circuit coincides with the execution of the conditional branch instruction, the instruction can be efficiently fetched without fetching a useless instruction other than executing the branch instruction.
The reason is that when the conditional branch instruction is prefetched, the branch destination address is predicted from the branch information RAM and the size determination circuit, and the prefetch operation is controlled so as to prefetch the instruction code at the branch destination address.

The second effect is that not only unconditional branch but also conditional branch instruction can be predicted.
The reason is that the PC value of the previously executed conditional branch instruction and the unconditional branch instruction, the PC value of the branch destination, a history counter indicating the number of past branches, and the branch history information necessary for branch prediction including the determination result information are described below. This is for recording in the branch information RAM.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a circuit relating to acquisition of branch information of the microcomputer according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a circuit relating to branch prediction of the microcomputer according to the first embodiment of the present invention.

FIG. 4 is a timing chart at the time of branch prediction matching according to the conditional branch instruction fetch control method according to the present invention.

FIG. 5 is a timing chart at the time of branch prediction mismatch according to the conditional branch instruction fetch control method according to the present invention.

FIG. 6 is a flowchart illustrating an operation of a conditional branch instruction fetch control method according to the present invention.

FIG. 7 is a system configuration diagram of a microcomputer according to a second embodiment of the present invention.

FIG. 8 is a system configuration diagram of a microcomputer according to a third embodiment of the present invention.

FIG. 9 is a block diagram of a microcomputer 104 according to the first related art.

FIG. 10 is a configuration diagram of a circuit for increasing the speed of a microcomputer for unconditional branches described in Japanese Patent Application Laid-Open No. 1-193939 (second prior art).

FIG. 11 is a block diagram showing an internal configuration of an instruction fetch unit described in Japanese Patent Application Laid-Open No. 4-195630 (third prior art).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Data bus (DataBus) 2 ... Address bus (Address Bus) 3 ... Instruction queue (PreFetch Memory) 4 ... Instruction fetch part (Fetch) 5 ... Instruction decoder part (Decode) 6 ... Arithmetic / instruction execution part (ALU) 7 ... Program counter (PC) 8 Program fetch counter (PFC) 9 Table detection circuit 10 Selector (SEL) 11 Branch instruction address RAM 12 Branch destination address latch circuit 13 Branch information RAM 14 History counter 15 selector ( SEL) 16 PFC branch PC value comparison circuit 17 Size determination circuit 18 Selector (SEL) 19 Determination result information 20 Branch destination comparison circuit 21 Prediction circuit 22 History information 30 Microcomputer

Claims (8)

[Claims] An instruction queue for storing an instruction code, an instruction fetch unit for fetching an instruction, an instruction decoder unit for decoding an instruction code, an operation / instruction execution unit for executing an instruction, and a conditional branch instruction A microcomputer that predicts a branch instruction destination and controls the next instruction code by an instruction fetch operation after the branch instruction code, thereby preventing a decrease in execution performance caused by time loss of the microcomputer due to the branch instruction, and executed in the past. A microcomputer having means for recording, as conditional branch information, a program counter value of a branch instruction, a branch instruction destination address for the branch instruction, and a history counter value indicating the number of times of branch to the branch destination. 2. The apparatus according to claim 1, further comprising means for detecting a branch instruction by comparing a program counter value of the branch instruction, which is branch information, with a prefetch counter value during a prefetch operation to the instruction queue. 1
The microcomputer according to 1. 3. The branch prediction circuit according to claim 1, further comprising a branch prediction circuit for predicting a conditional branch destination address to branch this time based on the conditional branch information when the conditional branch instruction is prefetched into the instruction queue. The microcomputer as described. 4. The microcomputer according to claim 3, wherein said branch prediction circuit has means for predicting a branch destination from a branch feature of a program using a conditional branch. 5. An instruction queue for storing an instruction code, an instruction fetch unit for fetching an instruction, an instruction decoder unit for decoding an instruction code, and an operation / instruction execution unit for executing an instruction. A past instruction was executed for a microcomputer that predicts the branch instruction destination and controls the next instruction code in the instruction fetch operation after the branch instruction code, thereby preventing the microcomputer from losing execution performance caused by the branch instruction's time loss. A conditional branch instruction fetch control method, comprising the step of recording, as conditional branch information, a program counter value of a branch instruction, a branch instruction destination address for the branch instruction, and a history counter value indicating the number of times of branch to the branch destination. 6. The method according to claim 1, further comprising the step of detecting a branch instruction by comparing a program counter value of the branch instruction, which is branch information, with a prefetch counter value during a prefetch operation to the instruction queue. 5
2. The conditional branch instruction fetch control method according to 1. 7. The method according to claim 5, further comprising a branch predicting step of predicting a conditional branch destination address to branch this time based on the conditional branch information when the conditional branch instruction is prefetched into the instruction queue. The described method for controlling conditional branch instruction fetch. 8. The method according to claim 7, wherein the branch prediction step includes a step of predicting a branch destination from a branch feature of a program using a conditional branch.