EP3437138A1 - Vertical sic mosfet - Google Patents

Abstract

The invention relates to a vertical SiC MOSFET (20) comprising a source connection (2), a drain connection (4) and a gate region (36) as well as an epitaxial layer (22) arranged between the source connection (2) and the drain connection (4) and comprising a first-type doping, where a horizontally extending intermediate layer (24) comprising regions (40) having a second-type doping different from the first-type doping is embedded in the epitaxial layer (22). The vertical SiC MOSFET (20) is characterised in that at least the regions with a second type of doping (40) are electroconductively connected to the source connection (2). The gate region (36) can be arranged in a gate trench (39).

Description

 description

title

 Vertical SiC-MOSFET

The present invention relates to a vertical SiC-MOSFET, that is, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor, German metal oxide-semiconductor field effect transistor), which is made of silicon carbide-based and whose elements are arranged predominantly vertically one above the other. In particular, the direction of current flow is also substantially vertically aligned.

State of the art

Semiconductor devices, in particular power devices such as PowerMOSFETs, have various criteria to be optimized. For example, a high short-circuit strength, ie the survival of a short-circuit situation in the form of a load-free operation without damage is desirable. Similarly, generally low values for Rdson, that is, the drain-to-source resistance in the on-state, are advantageous in reducing power dissipation. Classically, in conventional MOSFETs, both values are directly correlated:

For a typical conventional MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), which is considered to be representative of a power MOSFET or power MOSFET,

apply the elementary MOSFET equations, after which the saturation current dson

is. Here, V _g denotes the applied gate voltage, V _t h the

Use threshold voltage of the MOS channel and

Channel resistance of the MOSFET in the linear range. For the constant f

For the MOSFET according to the prior art, the value KF = 1 (for at measured at the beginning of the linear operation plateau).

The short-circuit strength is typically energy-limited, for example by melting the aluminum metallization after impressing the

Short-circuit energy E _sc , max, so that the achievable short-circuit time t _SC wt with applied voltage Uds due

 1 scwt - ~ j 77 ^ dson

'dsat ^{' u} ds

directly depends on R * d _SO n. In conventional MOSFETs, a reduction of the R * dson therefore automatically leads to a reduction of the short-circuit strength, that is, R * dson and short-circuit strength can not be optimized independently of each other.

In traction applications, guaranteed short-circuit strength is

 State of the art for Si-based 1200V semiconductors such as IGBTs (Insulated Gate Bipolar Transistor, German: bipolar transistor with insulated gate electrode). This value is not achieved by current SiC MOSFET concepts and is made even more difficult to realize by the cost-driven trend towards lower Rdson values.

see for example

 "Short Circuit Robustness of 1200V SiC Junction Transistors and Power MOSFETs", Siddarth Sundaresan et al (GeneSiCSemiconductor) ICSCRM 2015; "Repetitive Short-Circuit Testing on SiC VMOS Devices", Maxime Berthou et al (Laboratoire Ampere, France), ICSCRM 2015 ; "Concept with grounded bottom layer from Mitsubishi"

 Tanaka et al (Mitsubishi Electr. Corp.) ISPSD2014; Impact of Grounding the Bottom Oxide Protection Layer on the Short-Circuit Ruggedness of 4H-SiC Trench MOSFETs;

 "Temperature-Dependent Short-Circuit Capability of Silicon Carbide Power MOSFETs" Z. Wang et al. (Univ. Of Tennessee) IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 2, FEBRUARY 2016

Another problem can be too high fields in the gate oxide. Basically, the gate oxide has a lower band offset on SiC (silicon carbide) Conduction band on as comparable Si devices, so that degradation due to tunneling currents even at lower gate field strengths occurs. For

SiC MOSFETs is a reasonable field strength in the gate oxide at about 3 MV / cm. Compliance with this limit is particularly critical in lock-up mode and requires design measures to limit the gate field strength, especially for trench devices, see, for example, Kevin Matocha, "Challenges in SiC power MOSFET design", Solid-State Electronics 52 (2008) 1631-1635 ; "High Performance SiC Trench Devices with Ultra-Low Ron", T. Nakamura et al., 2011 IEEE International Electron Devices Meeting p.26.51-26.53.

Possibilities are known in the art for limiting at least the gate field strength. For example, the field strength at the gate oxide can be reduced by introducing a double trench with deep p-type implantation. The lower-lying p regions shield the actual trench MOSFET structure electrostatically, see, for example, Nakamura et al.

The field strengths at the gate oxide can likewise be reduced to approximately 4 MV / cm by introducing p-doped regions, so-called "p-bubbles" below the gate oxide, see, for example, "High-Voltage Accumulation Layer

UMOSFET's in 4H-SiC ", J. Tan et al., IEEE ELECTRON DEVICE LETTERS, VOL.19, NO.12, DECEMBER 1998.

Alternatively, the two above-mentioned measures (double trench, p-bubble) can be combined, see Shinsuke Harada et al., "Determination of optimum structure of 4H-SiC trench MOSFET", Proceedings of the 2012

24 ^th lnternational Symposium on Power Semiconductor Devices and ICs, pp. 253ff.Als further variant, a corresponding doping profile can be represented without double trench, if the p-regions are very deeply implanted.

From DE10201400613A1 a vertical trench MOSFET is known, which has within the epitaxial layer a compensation layer with opposite doping, which makes it possible to limit the maximum field strengths occurring.

Disclosure of the invention According to the invention, a vertical SiC-MOSFET is provided, with a source terminal, a drain terminal and a gate area and with one between the source terminal and the drain terminal

arranged, a doping of a first type having epitaxial layer, wherein in the epitaxial layer a horizontally extending

 Intermediate layer is embedded, the regions having a different doping of the first type doping second type, wherein at least the doped regions of the second type are electrically connected to the source terminal. Thus, below the conventional MOS structure, there is another plane which has at least regions with doping opposite to the doping of the epitaxial layer.

By including the intermediate layer in the epitaxial layer, it is understood in particular that the intermediate layer is surrounded on both sides by the epitaxial layer. It can thus be said that the epitaxial layer penetrates through the intermediate layer into an upper region, which as a rule lies on the side of the intermediate layer facing the source connection, and into a lower region, which as a rule lies on the side of the intermediate layer facing the drain connection. is split. In a special case, further regions or layers may be arranged between the intermediate layer and the upper and / or the lower region of the epitaxial layer. But it is also possible that the intermediate layer directly and in a special case over the entire surface respectively at the top and / or at the bottom of the

Epitaxial layer adjoins. The upper and lower regions of the epitaxial layer may have the same or different doping concentrations.

Advantages of the invention

The SiC-MOSFET according to the invention has the advantage that the current through the component can be effectively limited in the event of a short circuit. This makes it possible to produce components with particularly high short-circuit ruggedness, which were previously not available for SiC technology.

Because the concept according to the invention is integrated vertically, the additional structures do not result in any additional space requirement on the chip. The invention is thus surface-neutral with respect to conventional components with respect to Rd _SO n * A.

Furthermore, the inventive design offers the advantage that the field strength in the gate oxide is limited to a level below 3 MV to high

To meet requirements for the life of the component. Thus, both the current limited in the event of a short circuit as well as in the case of blocking in adjacent

Voltage effectively shielded the gate oxide.

By shielding the MOS channel from the drain field, this results according to reliability advantages and it is also a reduction of

Short channel effects in the form of an increase in the saturation current with increasing drain voltage, which is also advantageous for the short circuit resistance.

It is also possible for the intermediate layer to have both regions of first doping and regions of second doping. By selecting from

Dimensioning and doping concentration of the different areas can then set the properties of the MOSFET targeted. The areas of both first and second doping may span the entire

Extend layer thickness.

Advantageously, it is provided that the regions of second doping are not completely eliminated when a voltage is less than or equal to a blocking voltage of the SiC-MOSFET. This can be achieved by a high doping, for example of at least 5 * 10 ¹⁷ / cm ³ . It is advantageous if the doping changes as abruptly as possible laterally from one region to the other region. In other words, if possible, there are no or only very small transition regions with less intense doping or mixed doping. Since the regions of doping of the second type in the blocking case by clearing these areas provide significant counter charge for receiving the blocking voltage, the channel length of the MOSFET can be reduced. This results in a favorable reduction of the Rdson. It is advantageously possible that the intermediate layer completely below the

Gate region is arranged. It then results in a relatively simple constructive structure. Including that the intermediate layer below the

Gate area is arranged, is in particular understood that the

Intermediate layer is arranged vertically between the gate region and the drain region. Elements of the gate region, for example a gate trench, do not then intersect or interrupt the interlayer.

According to a preferred embodiment of the invention it is provided that the intermediate layer together with the epitaxial layer functionally a

Forming junction field effect transistor. In the static blocking case with

When the gate is turned off, the areas of first doping are removed with increasing drain voltage, that is, in regions with dopants of the first type in the intermediate layer, there are no quasi-neutral areas, so that a further increase in the drain voltage can essentially be absorbed by the JFET. Through the junction field effect transistor (also English junction FET or JFET) can then by the MOSFET

flowing current can be effectively limited in the event of a short circuit.

Under that areas are not completely eliminated, it is understood in particular that even after applying the reverse voltage quasi-neutral

Areas in the area concerned.

Furthermore, this results in a further design parameter, since the MOS region in the upper part of the MOSFET can now be designed for a much lower blocking voltage, since the intermediate layer or the JFET absorbs the essential part of the blocking voltage. It is in the blocked case

provided cleared counter charge, so that there is only a much lower electric field to the actual MOS structure and therefore less counter-charge is required in the body. This allows the reduction of

Channel length over the prior art.

This is achieved by choosing the thickness and doping (NA = ppjf _e t) of the doped regions of the second mode so that the voltage of the drift zone can be dissipated at least by the charge of the doped regions of the second kind. This results in the following design rule (for constant doping):

l »l * (. ^d Pjfet + d _jfet )

jfet EP, * ( _{| ΛΜ | # dp} _ _fet _ _{ND d} . _fet Where ljf _e t is the thickness of the interlayer, IEPI is the thickness of the epitaxial layer, N DEPI is the doping concentration of the epitaxial layer, ND is the doping concentration of the areas of first doping of the interlayer, NA is the doping concentration of the areas of second doping of the interlayer, and djfet is the areal extent of the areas first Doping of the intermediate layer and dpjfet the horizontal extension of the regions of the second doping of the intermediate layer. A special, meaningful choice of doping ratios is for example ND = njf _e t> NEPI, NA = ppjf _e t> ND.

For non-sectionally constant dopants in the intermediate layer and the EPI layer, instead of the products of NA, ND and the dimensions, the

to take appropriate volume integrals.

Because of the JFET functionality, the sheet charge density can in the body according to the relationship qb _ne u = qb _a it - C | be reduced JFET ⁺ Delta3D. In this case, the reduced sheet charge density according to the invention in the body is

qbait is the sheet charge density in the body of a conventional MOSFET, as would be required in the design without a JFET region, qjFET is the maximum effective effective charge of the JFET region interlayer in the partially evanescerated field distribution, and Delta3D is an adaptation term for 3D effects as well as a safety margin for a sufficient blocking strength, so that no punch through body takes place to the source.

A development of the invention provides that the transition layer to the intermediate layer vertically in the direction of the source terminal and / or in the direction of the drain terminal with a stronger than in the epitaxial layer

Doping of the first kind adjoins. It is thus prevented that the vertical pn junctions to regions of second doping of the intermediate layer to large

vertical space charge zones or current narrowings above and below the intermediate layer lead.

Furthermore, it is advantageous if, at the epitaxial layer, vertically in the direction of the source terminal, a transition layer with a compared to

Epitaxial layer of stronger doping of the first kind adjacent. In other words Thus, the transition layer adjoins the upper region of the epitaxial layer. Again, current restrictions at the pn junctions are avoided.

For the same reason it is favorable if one between the

Source terminal and the intermediate layer arranged upper part of the

 Epitaxial layer has a higher doping of the first kind, in particular a factor of 2 to 4 higher doping of the first kind, as one between the

Intermediate layer and the drain terminal arranged lower part of the

Epitaxial layer.

The described transition layers with a stronger, ie a higher concentration, doping of the first kind, which adjoin the epitaxial layer, can also be referred to as spread layers. Advantageously, in the embodiment of the spread layers, the design rule is observed that the total dose of the introduced dopants compared to the simple

 Epitaxial layer is kept constant. In other words, as the concentration increases at a location elsewhere, a lower doping concentration may be chosen to compensate.

A development of the invention provides that the first areas

Doping the intermediate layer vertically in the direction of the source terminal and / or in the direction of the drain terminal adjacent transition regions with a stronger compared to the epitaxial layer doping first type, wherein at the regions of the second doping of the intermediate layer at least partially

Epitaxial layer adjoins. Compared to the previously described

Embodiment here are not used complete spread layers, but only to the areas of second doping of the intermediate layer adjacent transition areas or spread areas. This results in a further optimization of the on-resistance of the MOSFET. The described

For example, design can be implemented using a multiple implant of different depths in combination with a mask spacer.

A special embodiment of the invention provides that the areas of first doping of the intermediate layer are a double-funnel-shaped or a

have hourglass-shaped profile. In other words, the rejuvenates horizontal extension of the regions of the first doping of the intermediate layer in each case from above and from below to the middle of the intermediate layer. Even with this measure, the breakdown voltage can be increased. All

As far as possible geometrically possible measures can be combined with each other.

An advantageous embodiment of the invention provides that a channel of

Junction field effect transistor and a channel of the MOSFET are arranged vertically one above the other The periodicity (cell pitch) of the junction field effect transistor can correspond to half the cell pitch of the TrenchMOS cell.

 In this way, the contributions of the junction field effect transistor for

Minimize resistance RDS _OP . Starting from an optimal position is the

Function of the device thereby relatively little sensitive to a lateral

Displacement (misalignment) of the JFET region with respect to the MOS region

or a change in the size of dpjFET.

It is advantageously provided that the functional junction field effect transistor is electrically connected in series with the MOSFET. Under the MOSFET is here the classic, functional MOSFET within the device, so usually the above the intermediate layer arranged region of the device understood. This enables the integration of a short-circuit proofed MOSFET JFET cascade into a single device. An advantage of this configuration is that the JFET is fed back across the voltage drop of the MOS region

If the drain current increases so far that the voltage drop across the MOS region is on the order of magnitude of the pinch voltage of the JFET, then the JFET contributes to

Current limitation significantly in. The drain current is then limited by reaching the threshold condition (pinch voltage) of the JFET. A

Channel length modulation and thus a further increasing saturation current of the MOSFET at high drain voltages are thus avoided. Achieving the threshold condition can be caused by the voltage drop across or

Doping the MOS region and the pinch voltage can be set within certain limits. The JFET channels within the JFET region or inside the

Interlayer may also have a different periodicity and / or another

Orientation as the MOS cell. In other words, the

Elements of the MOS structure, which are arranged on a certain width of the chip, differ in number and distance from the elements of the intermediate layer.

There may also be any angle between the orientation of the elements of the MOS plane, for example the gate electrodes, and the orientation of the elements of the intermediate plane. Furthermore, other JFET gate shapes such as a honeycomb structure, a

Square structure or similar possible. A typical extent of the regions of the first doping of the intermediate layer is in the region of 500 nm. Advantageously, the lateral extent of the regions of second doping of the intermediate layer is slightly larger than that of the regions of first doping, for example by a factor of 1, 2 or 1.5. The number of regions of first and second doping per unit cell of the MOS structure, that is, for example per gate trench, then results from the ratio between the distance between these MOS structures and the periodicity of the intermediate layer.

The MOS structure can be on the chip (supervision or layout) as

Line structure or two-dimensional grid structure may be present. Within the plane of the JFET layer or the intermediate plane, three-dimensional structures such as square gratings, honeycombs or

Hexagonal grid be present. These can in principle be combined with any analog periodic JFET grid structure.

Advantageous developments of the invention are in the dependent claims

specified and described in the description.

Drawings Embodiments of the invention will be explained in more detail with reference to the drawings and the description below. Show it:

FIG. 1 shows an equivalent circuit diagram of an embodiment of the invention, FIG. 2 shows a cross section through an exemplary embodiment of a MOSFET according to the invention,

FIG. 3 shows a detailed illustration of the intermediate layer from FIG. 2,

FIG. 4 shows a diagram in which possible doping concentrations are plotted,

FIG. 5 shows a further diagram in which possible doping concentrations are plotted,

6 shows a cross section through an embodiment in which a path for a line integral is shown schematically, FIG. 7 shows a cross section through an embodiment with transition layers,

8 shows a development of the embodiment shown in FIG. 7,

FIG. 9 shows a further embodiment of the invention,

FIG. 10 shows an alternative possibility for designing the intermediate layer,

Figure 1 1 three embodiments, which differ in the embodiment of

Distinguish epitaxial layer above the intermediate layer,

12 shows a longitudinal and a cross section through an embodiment analogous to the embodiment shown in Figures 2 and 3,

FIG. 13 shows a horizontal section through the exemplary embodiment from FIG. 11,

FIG. H shows a representation analogous to FIG. 12,

Figure 15 shows two further embodiments of the MOSFET according to the invention, Figure 16 is a typical embodiment of the invention, and 17 shows the applicability of the concept to different transistor concepts, and

Figure 18 output characteristics of embodiments. Embodiments of the invention

FIG. 1 shows an equivalent circuit diagram of an embodiment of the invention. On display are the typical elements of a MOSFET 1, namely the

In addition, two resistors are plotted, namely the resistance of the MOS area 8 and the resistance of the drift region 10. The conductive connection 12 between the source terminal 2 and the JFET gate 14 is a

A junction field effect transistor is formed which effectively limits high currents through the device 1.

When the voltage drop across the MOS region 6 and 8 becomes greater than or equal to the amount of the pinch voltage of the junction field effect transistor, it absorbs the further drain voltage increase. A

Channel length modulation and thus a further increasing saturation current of the MOSFET at high drain voltages are thus avoided. The exact operation of the junction field effect transistor or JFET is described in US Pat

Explained below with reference to the other figures.

Figure 2 shows a cross section through an embodiment of a

It shows only a section of the device, typically, the device may consist of a plurality of unit cells. Also, some elements of MOSFET 20 are not fully illustrated.

On a typically heavily doped substrate 21 is an n-doped

Epitaxial layer 22 applied, in turn, an intermediate layer 24 is embedded. In practice, the epitaxial layer is divided into an upper region 22.1 and a lower region 22.2. At the bottom, a metallization 26 represents the drain connection. The intermediate layer 24 is initially illustrated in FIG. 2 without further details. In the upper part of the figure are the typical Elements of a trench MOSFET 20 shown: It can be seen a metallization 28 as a source contact 2 and a metallization 30 as a gate contact.

Furthermore, the n-doped source region 34 and the gate region 36 arranged in a trench, that is to say a trench structure, are shown. The gate region 36 is formed by an insulating layer 38 from the source region 32 and from the

Epitaxial layer 22 separated. If a voltage is applied between the source contact 2 and the gate contact 4, an electric current flows in the figure from top to bottom, ie vertically, through the MOSFET 20, when a voltage above the threshold voltage of the MOSFET 20 is applied to the gate contact 32 and at the drain 26 a positive with respect to the source contact 28

Voltage applied.

FIG. 3 shows a detailed illustration of the intermediate layer 24 from FIG. 2. In addition, the upper and lower parts of the epitaxial layer adjoining the intermediate layer 24 are in each case in the upper and in the lower region of the FIGURE

22.1, 22.2. It is clear that the intermediate layer 24 in

horizontal or lateral direction has a special structure. Thus, p-doped regions 40.1, 40.2 and 40.3 as well as n-doped regions 42.1 and 42.2 are present in the intermediate layer. It should be noted at this point once again that, as usual with MOSFETs, the illustrated

 Embodiments can also be made with reversed doping.

Important design parameters for the functionality of the device 20 are the dimensions of the p-doped regions 40 and the n-doped regions 42 as well as the thickness lj _fe t of the intermediate layer 22. The intermediate layer 22 as such forms the so-called JFET region as a whole. The width of the p-doped regions 40 is denoted by dpj _f et and the width of the n-doped regions 42 by dj _f et. Schematically drawn in turn is the conductive connection 12, which establishes the electrical connection between the p-doped regions 40 and the source connection 2. Also schematically and only to illustrate the principle of operation is the switching symbol 16 of

Junction field effect transistor shown, the source terminal 17 is in the upper portion of the epitaxial layer 22 in the figure, whereas the drain terminal 18 of the junction field effect transistor 16 in the lower

Area of the epitaxial layer 22 is located. The gate 19 of the Junction field effect transistor is connected to the p-doped regions 40. Thus, these p-doped regions 40 are the gate of the

Junction field effect transistor 16.

Another important design parameter is the doping of the regions 40 and 42. FIG. 4 shows a diagram in which possible doping concentrations for the n-doped regions 42 are dependent on the width of the n-doped regions

Areas 42 for different JFET pinch voltages _{U gJFETth} , that is, by an appropriate choice of parameters, the pinch voltage of the JFET can be adjusted. All values shown are for one

Doping concentration of the p-doped regions of 5 * 10 ¹⁸ / cm ^{3 has been} calculated. Curve 101 is for the minimum size for djfet for each

Doping concentration. Curve 102 is for a JFET pinch voltage Ugthr = 5V, curve 103 is for a JFET pinch voltage Ugthr = 10V, curve 104 is for a JFET pinch voltage Ugthr = 20V and curve 105 is for a JFET pinch - Voltage Ugthr = 50V.

Figure 5 shows a diagram analogous to Figure 4 with the difference that of a doping concentration of 5 * 10 ¹⁷ / cm ³ for the p-doped regions

is assumed.

That of the JFET region, between the contact 17 and 19

 (see, for example, FIGS. 2 and 3), is characterized in that the n-side space charge zones become the same size as djfet, that is, between the p-doped regions 40 disappear the quasi-neutral areas of the n-majority carriers of the n-doped areas 42. The depth tjfet and the n-type doping within the MOS region are chosen to account for the short-circuit behavior such that for the target saturation current sat at applied voltage Uds = Ucc, which typically corresponds to 50% of the nominal blocking resistance of the devices, for n- Majority carrier, a potential drop "UMOS" is reached to the n-type opening of the JFET region 24, which places the JFET in the current-limiting state, in other words, the bias increases

Space charge zones of the n-layer 42 enclosing pn compounds to the extent that it is greater than or equal to djfet. UMOS expediently has values of at least 1V, typically between 5V and 20V. A reasonable upper limit may be 20% of the reverse voltage. It applies

UMOS = Ug _JFE T _THR ^ANDU MOS = J, _n ti (t _jfet) E dl where the path for the line integral in FIG. 6 is plotted as Int1. The line integral Int1 extends from the source region 34 through the epitaxial layer 22 to the n-doped region 42.

The lateral extent and doping of the n-type regions 40 and the p-type regions 42 within the JFET region are chosen such that at Uds = 0V the n-aperture djfet is greater than the double n-side space-charge region of the pn junction between NA and ND is such that n-majority carriers remain in the de-energized state within the n-region of the JFET region for current transport.

In the case of the one-dimensional abrupt pn junction, the following ideal-typical design rule follows:

2 e _r ∈ ₀ ND

d ^{jfet> 2} * ~ qe ^~ T ^Ubi NA * (NA + ND)

 The limit for djfet corresponds to the lowest one as djfet_min

drawn curve in Figure 4 and Figure 5. For real, spatial geometries and Dotierverteilungen the corresponding relationships are analytically not representable, but equally present and numerically solvable. Ubi refers to the "built-in" voltage, which already decays without any external applied voltage due to doping in the valence and conduction band across the pn junction, NA is the p-doping concentration and ND is the n-doping concentration.

Figure 7 shows a cross section through an embodiment with

Transition layers 50.1, 50.2, respectively above and below the

Intermediate layer 24 are arranged. The transition layers 50.1, 50.2 each have an n-doping of higher concentration than the epitaxial layer 22.1 or 22.2. Such a configuration prevents large space charge zones or current restrictions from occurring form the vertical pn junctions to the p-doped regions 40.

Also drawn is pijfet as the lateral dimension of the JFET structure.

FIG. 8 shows a development of the exemplary embodiment shown in FIG. 6, which is characterized by a third transitional layer 50

Source region 34 and the epitaxial layer 22 is arranged. It also becomes clear that the dopants of the three transition layers ns _P i, ns _P 2 and ns _P 3 can be different. FIG. 9 shows a variant in which the transition layers do not cover the entire cross-section of the MOSFET, but only extend in regions in the addressed layers. They are therefore considered

Transition areas or spread areas 52.1, 52.2, 52.3 are designated. Of the

Transition region 52.1 is again above the intermediate layer 24 in the region between the intermediate layer 24 and the epitaxial layer 22. Der

Transition region 52.2 is located below the intermediate layer 24 between the intermediate layer 24 and the epitaxial layer 22. The transition regions 52.1, 52.2 each span the n-doped region 42 between two p-doped regions 40.1, 40.2. Moreover, on both sides of the n-doped region of the intermediate layer 24, they cover a small part of the

adjacent p-doped region 40.1, 40.2 from. The extent of the

Transition regions 52.1, 52.2 across the "gap" between the p-doped

In this case, regions 40.1, 40.2 are approximately as large as half the width of the n-doped region in the intermediate layer.

The third transition region 52.3 is arranged in the region in which the gate region 36, p-body 64 and epitaxial layer 22 adjoin one another. It has a relatively small extent. It becomes clear that NA and N D, ie ppjfet and rijfet, N DEPI, as well as the doping between the MOSFET body and the JFET region, need not be constant, but may have a location dependency.

FIG. 10 shows a further possibility for designing the intermediate layer 24. Here, too, the goal is to avoid current constrictions. In the exemplary embodiment shown, this is achieved by slightly "retracting" the p-doped regions 40 in the vicinity of the epitaxial layer 22. The

Interlayer 24 here as from three separate layers 24.1, 24.2, 24.3 understood, which are basically identical, but differ in the lateral extent. The middle layer 24.2 is in

Essentially constructed as in the already described embodiments. It can be the thickest of the three layers 24.1, 24.2, 24.3.

In particular, the width of the n-doped region 42.2 is the middle layer

24.2 equal to the width of the n-doped regions 40 in the embodiments already described. However, the upper layer 24.1 and the lower layer 24.3 of the n-doped region 42 have a larger extent. The overall result is a roughly hourglass-shaped or double-funnel-shaped cross section for the n-doped region 40.

Figure 1 1 shows three embodiments, which are in the embodiment of

Epitaxial layer 22.1 above the intermediate layer 24 differ. An exemplary embodiment is shown in the left-hand area of the figure, in which a p-doped region 62.1 extending to the intermediate layer 24 is introduced below the gate trench 39 in the epitaxial layer 22. In other words, the area between gate trench 39 and intermediate layer 24 is mostly filled with p-doped material. The region of the intermediate layer 24 which lies below the gate trench 39 is also made of p-doped material. It is thus in comparison to the previously described embodiments below the

Gate Trenches 39 n-doped material has been replaced by p-doped material.

In the middle region of FIG. 11, another p-doped region 62.2 is arranged below the p-body region 64. Also this area is in

Substantially congruent over a p-doped region 40 of

 Intermediate layer 24 is arranged. In the right portion of Figure 1 1 is a

Embodiment shown that combines both versions together, so both the p-doped region 62.1 and the p-doped region has 62.2. All the embodiments shown in FIG. 11 have the advantage that p-charges are provided which are not in the channel region.

Figure 12 shows a longitudinal and a cross section through an embodiment analogous to the embodiment shown in Figures 2 and 3. The vertical dashed line indicates the sectional plane of the section shown in the right portion of FIG. It can be seen that the p-doped regions 40 are conductively connected to the source pad 2. Farther It can be seen that the gate electrode 36 arranged in the gate trench 39 was partially interrupted for the contacting. Technically, the

Contacting for example by means of a contact implants in the trench 39 in

Realize connection with p-doped transverse webs 60 between the p-doped regions. These transverse webs 60 are shown in FIG.

Also possible is a contact via deep contact implant. In the case of two JFET channels per parallel MOS cell, no transverse webs are required for the electrical connection of the p areas. The contacts are not limited to running parallel to the trench JFET structures but can also be made selectively at contact points between JFET grid (p regions of the JFET region) and the contact designs. Likewise, contacting the p regions outside the active MOS cells is conceivable.

 FIG. 13 shows a horizontal section along the horizontal dashed line from FIG. 12. The section thus runs through the intermediate layer 24 and parallel to it. As dashed lines lying on the plane above the gate areas 36 are shown. After the vertical

Contacting of the p-doped regions 40 by means of the interruptions of

Trenches 39 can be seen here, it can be seen that the individual p-doped regions 40 are interconnected by the n-doped

Areas 42 of the intermediate layer 24 are interrupted.

FIG. 14 shows a representation analogous to FIG. 13. On the basis of the gate regions 36, again shown as dashed lines, it becomes clear that the

Intermediate plane 24 by any angle α to the rest of the MOSFET

can be turned. In other words, between, for example, the

Gate trenches 39 and the n-doped regions 42 of the intermediate layer 24 an angle of for example 20 °, 45 ° or even 90 ° exist. Of course, however, the n-doped regions 42 of the intermediate layer 24 can also run parallel to the gate regions 39. Likewise, different periodicities are possible.

FIG. 15 shows two embodiments of the MOSFET 20 according to the invention, which are characterized only by the structure of the intermediate layer 24 and in turn by the spacing and number of the n-doped regions 42 and the p-doped regions Regions 40 of the intermediate layer 24 differ. In the left-hand portion of the figure, an example is shown which has only one n-doped region 42 in the intermediate layer 24 per MOS cell. The embodiment shown in the right part of the figure, however, has five n-doped regions 42 per unit cell, one of which is located centrally below the gate trench 39 and, since only one half cell is shown, only half is shown. The p-doped regions 40 lying between the n-doped regions 42 are made slightly wider than the n-doped regions 40.

Figure 16 shows a typical embodiment. All important dimensions are illustrated once more in the figure. There are the already known from the other figures reference numerals.

Figure 17 shows the applicability of the concept to various

Transistor concepts. The left part of the figure shows the already known integration into a trench MOSFET. In the middle part of the figure, a DMOS (English: double-diffused metal-oxide semiconductor field effect transistor) with an intermediate layer 24 according to the invention can be seen. In the right part of the figure, a VMOS (from English: v-groved MOS field-effect transistor) is shown with an intermediate layer 24 according to the invention.

FIG. 18 shows output characteristics (107) of a conventional MOSFET in comparison to two MOSFETs (108), (109) according to the invention.

In a conventional MOSFET, there is a marked increase in the

Saturation current with increasing drain voltage to recognize. In the

According to the MOSFET according to the invention is to detect a large increase in current at low drain voltages (ie good on-resistance). For higher drain voltages, a sharp transition to an almost horizontal characteristic occurs. When the drain voltage reaches the pinch voltage of the

Junction field effect transistor it comes to the transition. Depending on the design and design of the saturation current at high drain voltages, that is, voltages above the transition voltage can be set to different values, as can be seen from the comparison of the two MOSFET characteristics of the invention. Advantageously, one chooses the position of the pinch voltage of the JFET so that they are well above typical

Forward voltages in the on state of the MOSFET but is meaningfully does not exceed 20% of the blocking voltage of the MOSFET.

In all the described exemplary embodiments, it is of course possible to exchange the signs of the doping without deviating from the inventive concept. In other words, all described n-

Dopants be replaced by p-type dopants and vice versa.

Claims

claims 1. SiC vertical MOSFET (20) with a source (2), a  Drain terminal (4) and a gate region (36) and with a between the source terminal (2) and the drain terminal (4) arranged, a doping of a first type having epitaxial layer (22), wherein in the epitaxial layer (22) has a horizontally extending intermediate layer (24) is embedded, the regions (40) having a different doping of the first type doping of the second type, characterized in that at least the doped regions of the second type (40) are electrically connected to the source terminal (2). 2. The vertical SiC MOSFET (20) of claim 1, wherein the intermediate layer (22) comprises both first dopant regions (42) and second doped regions (40). The vertical SiC-MOSFET (20) according to claim 1 or 2, wherein the regions of second dopant (40) are not completely removed when a voltage equal to or lower than a reverse voltage of the SiC-MOSFET (20) is applied. 4. The vertical SiC-MOSFET (20) according to any one of the preceding claims, wherein the intermediate layer (24) is disposed completely below the gate region (36). 5. A vertical SiC MOSFET (20) according to any one of the preceding claims, wherein the intermediate layer (24) together with the epitaxial layer (22) functionally forms a junction field effect transistor. A vertical SiC-MOSFET (20) according to any one of the preceding claims, wherein the pinch voltage of the junction field effect transistor is in the range between 1 V and 50% of the breakdown voltage of the SiC-MOSFET (20). A vertical SiC-MOSFET (20) according to any one of the preceding claims, wherein the intermediate layer (24) is oriented vertically in the direction of  Source terminal (2) and / or in the direction of the drain terminal (4) adjacent to a transition layer (50.1, 50.2) with a comparison with the epitaxial layer (22) stronger doping of the first kind. A vertical SiC MOSFET (20) according to any one of the preceding claims, wherein the epitaxial layer (22) is oriented vertically in the direction of  Source terminal (2) a transition layer (50.3) with a comparison with the epitaxial layer (22) stronger doping of the first kind adjacent. A vertical SiC-MOSFET (20) according to one of the preceding claims, wherein an upper part of the epitaxial layer (22.1) arranged between the source terminal (2) and the intermediate layer (24) has a higher doping of the first kind, in particular a factor of 2 to 4 higher Doping of the first kind as a between the intermediate layer (24) and the drain terminal (4) arranged lower part of the epitaxial layer (22.2). 10. A vertical SiC-MOSFET (20) according to any one of the preceding claims, wherein at the areas of first doping (42) of the intermediate layer (24) vertically in the direction of the source terminal (2) and / or in the direction of the drain terminal (4) transition regions (52 ) are adjacent to a stronger doping of the first kind compared to the epitaxial layer (22), the epitaxial layer (22) being at least partially adjacent to the regions of second doping (40) of the intermediate layer (24). 1 1. A vertical SiC MOSFET (20) according to any one of the preceding claims, wherein the areas of first doping (42) of the intermediate layer (24) have a double-funnel-shaped profile or an hourglass-shaped profile. 12. A vertical SiC MOSFET (20) according to any one of claims 5 to 11, wherein a channel (56) of the junction field effect transistor and a channel (58) of the MOSFET are arranged vertically one above the other. 13. The vertical SiC MOSFET (20) according to any one of claims 5 to 12, wherein the junction field effect transistor is electrically connected in series with the MOSFET. 14. A control device for a vehicle, comprising a vertical SiC-MOSFET (20) according to any one of the preceding claims.