DE10345464A1 - Multi-chip housing has carrier substrate with terminal line regions for connecting semiconductor chip metallization contacts with printed circuit board contact surfaces acting as encapsulation housing - Google Patents

Multi-chip housing has carrier substrate with terminal line regions for connecting semiconductor chip metallization contacts with printed circuit board contact surfaces acting as encapsulation housing Download PDF

Info

Publication number
DE10345464A1
DE10345464A1 DE10345464A DE10345464A DE10345464A1 DE 10345464 A1 DE10345464 A1 DE 10345464A1 DE 10345464 A DE10345464 A DE 10345464A DE 10345464 A DE10345464 A DE 10345464A DE 10345464 A1 DE10345464 A1 DE 10345464A1
Authority
DE
Germany
Prior art keywords
housing
carrier substrate
circuit board
terminal line
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10345464A
Other languages
German (de)
Inventor
Holger Huebner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10345464A priority Critical patent/DE10345464A1/en
Publication of DE10345464A1 publication Critical patent/DE10345464A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

The multi-chip housing (9) has a carrier substrate (10) with 2 terminal line regions (11,12), a chip stack with at least one semiconductor chip (2) having metallization contacts (5) connected to one terminal line region of the carrier substrate, the second terminal line region contacting contact surfaces of a printed circuit board, for providing an electrical connection between the semiconductor chip metallization contacts and the printed circuit board contact surfaces. The carrier substrate acts as the encapsulation housing enclosing the chip stack.
DE10345464A 2003-09-30 2003-09-30 Multi-chip housing has carrier substrate with terminal line regions for connecting semiconductor chip metallization contacts with printed circuit board contact surfaces acting as encapsulation housing Ceased DE10345464A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE10345464A DE10345464A1 (en) 2003-09-30 2003-09-30 Multi-chip housing has carrier substrate with terminal line regions for connecting semiconductor chip metallization contacts with printed circuit board contact surfaces acting as encapsulation housing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10345464A DE10345464A1 (en) 2003-09-30 2003-09-30 Multi-chip housing has carrier substrate with terminal line regions for connecting semiconductor chip metallization contacts with printed circuit board contact surfaces acting as encapsulation housing

Publications (1)

Publication Number Publication Date
DE10345464A1 true DE10345464A1 (en) 2005-05-04

Family

ID=34399096

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10345464A Ceased DE10345464A1 (en) 2003-09-30 2003-09-30 Multi-chip housing has carrier substrate with terminal line regions for connecting semiconductor chip metallization contacts with printed circuit board contact surfaces acting as encapsulation housing

Country Status (1)

Country Link
DE (1) DE10345464A1 (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4710798A (en) * 1985-09-10 1987-12-01 Northern Telecom Limited Integrated circuit chip package
JPS6321860A (en) * 1986-07-15 1988-01-29 Oki Electric Ind Co Ltd Semiconductor device
WO1992002040A1 (en) * 1990-07-25 1992-02-06 Dsm N.V. Package for incorporating an integrated circuit and a process for the production of the package
US5646828A (en) * 1995-02-24 1997-07-08 Lucent Technologies Inc. Thin packaging of multi-chip modules with enhanced thermal/power management
US5808878A (en) * 1995-03-16 1998-09-15 Kabushiki Kaisha Toshiba Circuit substrate shielding device
US6168969B1 (en) * 1996-02-16 2001-01-02 Micron Technology, Inc. Surface mount IC using silicon vias in an area array format or same size as die array
US6278190B1 (en) * 1999-03-04 2001-08-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6486001B1 (en) * 1999-03-10 2002-11-26 Kabushiki Kaisha Toshiba Fabricating method of semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4710798A (en) * 1985-09-10 1987-12-01 Northern Telecom Limited Integrated circuit chip package
JPS6321860A (en) * 1986-07-15 1988-01-29 Oki Electric Ind Co Ltd Semiconductor device
WO1992002040A1 (en) * 1990-07-25 1992-02-06 Dsm N.V. Package for incorporating an integrated circuit and a process for the production of the package
US5646828A (en) * 1995-02-24 1997-07-08 Lucent Technologies Inc. Thin packaging of multi-chip modules with enhanced thermal/power management
US5808878A (en) * 1995-03-16 1998-09-15 Kabushiki Kaisha Toshiba Circuit substrate shielding device
US6168969B1 (en) * 1996-02-16 2001-01-02 Micron Technology, Inc. Surface mount IC using silicon vias in an area array format or same size as die array
US6278190B1 (en) * 1999-03-04 2001-08-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6486001B1 (en) * 1999-03-10 2002-11-26 Kabushiki Kaisha Toshiba Fabricating method of semiconductor device

Similar Documents

Publication Publication Date Title
TW200707595A (en) Electronic device
WO2003054954A3 (en) Electrical/optical integration scheme using direct copper bonding
WO2004008532A3 (en) High power mcm package
SG115573A1 (en) Electronic device as multichip module and method for producing it
TW200419760A (en) Wafer level package, multi-package stack, and method of manufacturing the same
TW428258B (en) Semiconductor device with connection terminals in the form of a grid array
TW200707606A (en) Method of manufacturing an assembly and assembly
WO2003100858A3 (en) Surface mounted decoupling capacitor system and process of making the same
TW200742249A (en) Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
JP2002110905A5 (en)
SG99937A1 (en) An electronic device and a method of manufacturing the same
DE502004005445D1 (en) Multi-chip circuit module and method of making this
WO2003067646A3 (en) Semiconductor substrate comprising an electrically isolated region, in particular for vertical integration
TW200715499A (en) Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts
TW200731140A (en) A semiconductor device and a method for manufacturing the same
ATE358333T1 (en) INTEGRATION OF OPTOELECTRONIC COMPONENTS
TW200802828A (en) Semiconductor device
AU2002316910A1 (en) Circuit board with at least one electronic component
TW200501290A (en) A semiconductor device and manufacturing method thereof
MY126242A (en) Electronic assembly with laterally connected capacitors and manufacturing method
TW200605279A (en) Semiconductor device and manufacturing method thereof
TW200501838A (en) Hybrid integrated circuit device
GB9718127D0 (en) Chip package device and a multi-chip module mountable on a printed circuit board
TW200516732A (en) Semiconductor package
WO2004015773A3 (en) Semiconductor wafer having electrically connected contact and testing surfaces

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection