CN223772444U - LED chip components and display devices - Google Patents

Abstract

This application provides an LED chip assembly and a display device. The LED chip assembly includes: a driving substrate; multiple LED chips, arrayed and bonded to the driving substrate; a common electrode layer covering the multiple LED chips for electrical connection with the electrodes of each LED chip; multiple first reflective barriers, each first reflective barrier disposed on the common electrode layer between two adjacent LED chips, forming a metal grid; and multiple second reflective barriers, each second reflective barrier bonded to the first reflective barriers. This application improves the luminous efficiency of Micro-LED chips by setting first and second reflective barriers between the LED chips to form a reflective grid structure, thereby changing the light direction emitted from the sidewalls of the LED chips and allowing most light to be emitted from the front.

Description

LED chip assembly and display device

Technical Field

The invention relates to the technical field of LED chips, in particular to an LED chip assembly and display equipment.

Background

Micro light emitting diode (Micro-LED) display is a very promising display technology, and has great potential application value in Virtual Reality (VR), augmented Reality (AR) and other technologies. Compared with Liquid Crystal Displays (LCD) and Organic Light Emitting Diodes (OLED), micro-LEDs have excellent characteristics of high resolution, high brightness, low power consumption, fast response, high contrast, long service life, and the like. Micro-LEDs have a wide range of applications including optical neural networks, maskless digital lithography, visible light communications, wearable/implantable devices, and super-resolution imaging.

Micro-LEDs are typically prepared by etching an epitaxial layer of III-V semiconductor material into individual island-shaped light emitting mesas (measa) using ICP etching. The light emitted from the Mesa sidewall mostly exits at a large angle close to perpendicular to the sidewall. However, in AR and VR display applications, these light rays emitted at large angles are often blocked and lost, and do not enter the human eye well, thereby reducing luminous efficiency and luminous intensity.

Disclosure of utility model

In view of the foregoing deficiencies of the prior art, it is an object of the present application to provide an LED chip assembly and a display device, which aim to improve the light emitting efficiency and light emitting intensity of Micro-LEDs at large angles in AR and VR display applications.

In a first aspect, the present application provides an LED chip assembly comprising a driving substrate;

the LED chip arrays are bonded on the driving substrate;

the common electrode layer is covered on the LED chips and is electrically connected with the electrodes of each LED chip;

The first reflection retaining walls are arranged on the common electrode layer between two adjacent LED chips to form a metal grid;

And the second reflection retaining walls are bonded on the first reflection retaining walls.

In one possible embodiment, the material of the first reflective retaining wall is a metal material.

In a possible embodiment, the first reflective retaining wall is rectangular in shape.

In one possible embodiment, the material of the second reflective retaining wall is a metal material or a metal alloy material.

In a possible embodiment, the second reflective retaining wall is in the shape of an isosceles trapezoid.

In a possible embodiment, the thickness of the first reflective retaining wall is smaller than the thickness of the second reflective retaining wall.

In a possible embodiment, the sum of the thickness of the first reflective retaining wall and the thickness of the second reflective retaining wall is less than or equal to the height of the LED chip.

In a possible embodiment, the LED chip is a vertical structure.

In a possible embodiment, the common electrode layer is a transparent conductive layer.

In a second aspect, the application also provides a display device comprising an LED chip assembly according to any one of the first aspects.

The beneficial effects are that:

According to the LED chip assembly and the display device, the plurality of LED chip arrays are bonded on the driving substrate, the common electrode layer is arranged on the plurality of LED chips, and then the first reflection retaining wall and the second reflection retaining wall are sequentially arranged on the common electrode layer between the adjacent LED chips, so that a reflection grid structure is formed, the emergent light direction of the side wall of the LED chip is changed, most of light can be emergent from the front surface, and therefore the luminous efficiency of the Micro-LED chip is improved.

Drawings

Fig. 1 is a schematic structural diagram of an LED chip assembly according to an embodiment of the present application;

fig. 2 is a schematic flow chart of a method for manufacturing an LED chip assembly according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of an epitaxial wafer in the method for manufacturing the LED chip assembly shown in fig. 2;

FIG. 4 is a schematic diagram of a structure of the LED chip assembly shown in FIG. 2 after vapor deposition of a transparent conductive layer;

FIG. 5 is a schematic diagram of the LED chip assembly shown in FIG. 2 after bonding to a driving substrate;

FIG. 6 is a schematic diagram of a structure of the LED chip assembly shown in FIG. 2 after vapor deposition of electrodes;

FIG. 7 is a schematic diagram of a patterning process in the method for fabricating the LED chip assembly shown in FIG. 2;

FIG. 8 is a schematic diagram illustrating a process structure of a passivation layer and openings in the method for fabricating an LED chip assembly shown in FIG. 2

Fig. 9 is a schematic diagram illustrating a process structure of evaporating a common electrode layer in the method for manufacturing an LED chip assembly shown in fig. 2

FIG. 10 is a schematic diagram of a process of sputtering an under bump metallization layer in the method of fabricating an LED chip assembly shown in FIG. 2;

Fig. 11 is a schematic diagram illustrating a process of forming a second reflective retaining wall in the method for manufacturing the LED chip assembly shown in fig. 2.

Fig. 12 is a schematic view illustrating a process of forming a first reflective retaining wall in the method for manufacturing the LED chip assembly shown in fig. 2.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.

The disclosure of the present invention provides many different embodiments or examples for implementing different structures of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described herein. They are, of course, merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Generally, the terminology may be understood, at least in part, in accordance with the usage of the application. For example, the term "one or more" as used herein depends at least in part on the application and may be used to describe any component, structure or feature in the singular or may be used to describe any combination of components, structures or features in the plural. Similarly, terms such as "a," "an," or "the" may also be construed to convey a singular usage or a plural usage depending, at least in part, on the application above. In addition, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but rather as may be dependent, at least in part, upon the above that the application may instead allow for the presence of additional factors that are not necessarily explicitly described.

It should be readily understood that the meanings of "on," "over," and "above" in the present invention should be interpreted in the broadest sense so that "on" means not only "directly on" but also "on" including an intermediate member or layer that exists therebetween, and "on" or "over" means not only "on" or "over" but also the meaning of "on" or "over" without an intermediate member or layer therebetween.

Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be rotated 90 deg. in other orientations or in other orientations and the spatially relative descriptors used in the present invention may be interpreted accordingly as such.

The term "layer" as used in the present invention refers to a portion of material comprising regions having a certain thickness. The layers may extend over the entire underlying or overlying structure, or may have a degree less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereon. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

Referring to fig. 1, a schematic structure of an LED chip assembly according to an embodiment of the present application includes a driving substrate 110, an LED chip 120, a common electrode layer 130, a first reflective barrier wall 140 and a second reflective barrier wall 150.

The driving substrate 110 is a CMOS (Complementary Metal Oxide Semiconductor ) substrate.

Alternatively, the number of the LED chips 120 is plural, and the plural LED chips 120 are bonded on the driving substrate 110 in an array. The specific number of the LED chips 120 is determined according to the size and pixel density of the driving substrate 110, and is not particularly limited herein.

Alternatively, the LED chip 120 is a micro LED. Which includes red light emitting micro LEDs, green light emitting micro LEDs, and/or blue light emitting micro LEDs.

Alternatively, the LED chip 120 is a vertical structure, i.e., the LED chip 120 is a vertical chip.

In the embodiment of the present application, the layer structure of the LED chip 120 includes a bonding metal layer 122, a transparent conductive layer 121, a first semiconductor layer 123, an active layer 125, a second semiconductor layer 127, and an electrode 129 stacked in order, where the first semiconductor layer 123 and the second semiconductor layer 127 are doped semiconductor layers of different types. The bonding metal layer 122 is used for gold-bonding with the metal layer on the driving substrate 110.

It is understood that the material of the transparent conductive layer 121 may be a transparent material with low sheet resistance such as ITO, IGO, IZO.

It is understood that the LED chip 120 may further include other layer structures, such as a current spreading layer, an ohmic contact layer, a passivation layer, and the like.

The first semiconductor layer 123 may be an N-doped semiconductor layer or a P-doped semiconductor layer, and the second semiconductor layer 127 may be a P-doped semiconductor layer or an N-doped semiconductor layer. The active layer 125 may be a multiple quantum well structure (Multiple Quantum Well, MQW). Specifically, the semiconductor layer may be a group III-V compound semiconductor material such as GaN, alGaN, inGaN, alInP, gaInP, alGaInP, the quantum well or quantum layer may be InGaN, alGaN, inN, inAlN, alInGaN, and the quantum barrier alternately stacked with the quantum well layer may be GaN, alN, alGaN, alInGaN, inAlN, or the like, the multiple quantum well structure may include one or two or three or four or five or six or seven or eight quantum wells (or at least one quantum hole), and the wavelength emitted from the active layer 125 may be a wavelength of a blue light band, a wavelength of a green light band, or a wavelength of the red light band.

Optionally, a common electrode layer 130 covers the electrode 129 of each LED chip 120 to be electrically connected with the electrode 129 of each LED chip. For example, if the LED chips 120 share N-poles, the common electrode layer 130 is covered on the N-poles of each LED chip 120 to interconnect the N-poles of the LED chips 120 together using the common electrode layer 130, whereas if the LED chips 120 share P-poles, the common electrode layer 130 is covered on the P-poles of each LED chip 120.

Alternatively, the common electrode layer 130 is a transparent conductive layer. The material can be ITO, IGO, IZO or other transparent materials with low sheet resistance.

In the embodiment of the application, the first reflective barrier wall 140 is an Under Bump Metallurgy (UBM) structure, and the material thereof may be Cr/Ni/Au, ti/Pt/Au, or Ti-W/Au.

Optionally, the first reflective barrier wall 140 material is Ti-W/Au.

In the embodiment of the application, the number of the first reflective barriers 140 is plural, and each first reflective barrier 140 is disposed on the common electrode layer 130 between two adjacent LED chips 120 to form a metal grid.

It is understood that the first reflective barrier 140 may be formed by a surface sputtering process and a wet etching process, which are not particularly limited herein.

Alternatively, the first reflective retaining wall 140 is rectangular in shape. For example square or rectangular.

It should be noted that the first reflective retaining wall 140 is used for adhesion and diffusion blocking.

In the embodiment of the application, the second reflective retaining wall 150 is bonded to the first reflective retaining wall 140.

Optionally, the number of the second reflective retaining walls 150 is equal to the number of the first reflective retaining walls 140.

Optionally, the material of the second reflective retaining wall 150 is a metal material or a metal alloy material. Here, the present invention is not particularly limited.

Optionally, the second reflective retaining wall 150 is isosceles trapezoid in shape.

It can be appreciated that by making the second reflection barrier 150 in a regular trapezoid between the adjacent LED chips 120, it is convenient to specularly reflect the light emitted from the side walls of the chips, so as to improve the light extraction efficiency of a single pixel point, and improve the light emitting angle of the whole chip.

Optionally, the thickness of the first reflective retaining wall 140 is smaller than the thickness of the second reflective retaining wall 150.

Optionally, the sum of the thickness of the first reflective retaining wall 140 and the thickness of the second reflective retaining wall 150 is less than or equal to the height of the LED chip 120.

In one possible embodiment, the width of the first reflective barrier 140 is smaller than the spacing between the adjacent LED chips 120.

It can be appreciated that, in the LED chip assembly provided in this embodiment, the plurality of LED chips 120 are bonded on the driving substrate 110 in an array manner, the common electrode layer 130 is disposed on the plurality of LED chips 120, and then the first reflective retaining wall 140 and the second reflective retaining wall 150 are sequentially disposed on the common electrode layer 130 between the adjacent LED chips 120, so as to form a reflective grid structure, change the light direction emitted from the side wall of the LED chip 120, and enable most of the light to be emitted from the front surface, thereby improving the light emitting efficiency of the Micro-LED chip. And since the metal conductivity of the first reflective barrier wall 140 and the second reflective barrier wall 150 is superior to that of the common electrode layer 130, it is helpful to promote the common electrode current spreading and improve the brightness uniformity of the core region.

As shown in fig. 2, based on the same inventive concept, an embodiment of the present application further provides a method for manufacturing an LED chip assembly, where the method includes:

and 101, providing an epitaxial wafer.

The epitaxial wafer includes a substrate and functional layers sequentially stacked on the substrate.

Illustratively, as shown in fig. 3, in the embodiment of the present application, the functional layer is a main epitaxial layer structure of the LED chip, and may include a second semiconductor layer 127, an active layer 125, and a first semiconductor layer 123 sequentially stacked on the substrate 12.

102, Evaporating a transparent conductive layer on the functional layer.

For example, as shown in fig. 4, a P-side up structure epitaxy is adopted, a transparent conductive layer 121 is evaporated on the surface of the functional layer far away from the substrate, and the material can be a transparent material with low sheet resistance such as ITO, IGO, IZO and the like, and ohmic contact is formed with the epitaxy. For example, ohmic contact with the first semiconductor layer 123.

And 103, evaporating a bonding metal layer on the transparent conductive layer, and bonding the bonding metal layer with the driving substrate.

Illustratively, as shown in fig. 5, the epitaxy is transferred onto the drive substrate 110 by metal bonding, the material of the bonding metal layer 122 may be Au, al, sn, in, cu, pt or the like.

Optionally, after bonding is completed, the substrate 12 on the epitaxial wafer is stripped to expose the second semiconductor layer 127, wherein the stripping may be wet etching.

And 104, evaporating an electrode on the second semiconductor layer.

Illustratively, as shown in FIG. 6, electrode 129 is deposited on the epitaxial surface, which may be Au, al, ag, cu, ni, auZn, auBe, auGe, auGeNi or the like (similar to a conductive metal), and then annealed at 300-500C for 10-60 seconds to form an ohmic contact between electrode 129 and second semiconductor layer 127.

The functional layer and bond metal layer are patterned 105 to form a plurality of individual LED chips.

Illustratively, as shown in fig. 7, the functional layers and bond metal of the epitaxial wafer are etched into individual island structures by ICP etching to form a plurality of individual LED chips.

And 106, depositing a passivation layer on the LED chip, and etching and opening the passivation layer of the LED chip by utilizing ICP etching to expose the electrode on the LED chip.

Illustratively, as shown in FIG. 8, a passivation layer 10 is deposited on the epitaxial surface using PECVD and then the passivation layer 10 on the LED chip surface is etched open using ICP etching.

107 Vapor plating a common electrode layer.

Wherein the common electrode layer covers the LED chips to interconnect the electrodes of each LED chip together.

For example, as shown in fig. 9, a common electrode layer is deposited on the surface of the LED chip, and the material may be a transparent material with low sheet resistance such as ITO, IGO, IZO, etc., and the electrodes of the core particle are interconnected together by the common electrode layer. Then, the common electrode layer at the periphery of the core region is removed by wet etching.

And 108, sputtering an under bump metal layer on the common electrode layer.

Illustratively, as shown in fig. 10, an under bump metallization layer 13 (UBM) is sputtered on the Wafer surface, primarily serving as an adhesion and diffusion barrier. For Au bumps, the UBM is commonly selected from Cr/Ni/Au, ti/Ni/Au, ti/Pt/Au and Ti-W/Au, and the Ti-W/Au structure is selected.

And 109, spin-coating a layer of negative photoresist, and patterning the surface of the LED chip by using the negative photoresist to expose the gap position of the LED chip, wherein other positions are covered by the photoresist.

And 110, electroplating a second reflection retaining wall at the gap position of the LED chip by using an electroplating gold device.

Illustratively, as shown in FIG. 11, the second reflective barrier 150 is plated at the LED chip gap location with an electro-gold plating device.

And 111, removing the negative photoresist and removing the under bump metal layer outside the second reflection retaining wall.

Optionally, wet etching is used to remove the under bump metallization layer outside the second reflective barrier wall.

It is understood that the post bump metallurgy layer is removed to form the first reflective barrier 140 under the second reflective barrier 150.

As shown in fig. 12, the under bump metal layer outside the second reflective barrier wall 150 is removed by wet etching, and then the first reflective barrier wall 140 is formed under the second reflective barrier wall 150.

In one possible embodiment, the method further comprises vapor plating metal at the interface region as a wire bond metal pad.

Optionally, the material of the metal pad includes Ti/Pt/Au, ti/Al, etc.

Based on the same inventive concept, the embodiment of the present application also provides a display device including the LED chip assembly according to the above embodiment.

Alternatively, the display device may be an AR display device, a VR display device, a smart wearable device, a smart phone, or the like.

It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.

Claims (10)

1. An LED chip assembly, characterized in that it comprises: Drive substrate; Multiple LED chips, and an array of the multiple LED chips are bonded to the driving substrate; A common electrode layer covers the plurality of LED chips to be electrically connected to the electrodes of each LED chip; Multiple first reflective barriers are provided, each of which is disposed on the common electrode layer between two adjacent LED chips to form a metal grid; Multiple second reflective barriers, each of which is bonded to the first reflective barrier. 2. The LED chip assembly as described in claim 1, wherein the material of the first reflective barrier is a metal material. 3. The LED chip assembly as described in claim 1 or 2, wherein the first reflective barrier is rectangular in shape. 4. The LED chip assembly as described in claim 1, wherein the material of the second reflective barrier is a metal material or a metal alloy material. 5. The LED chip assembly as claimed in claim 4, wherein the second reflective barrier is in the shape of an isosceles trapezoid. 6. The LED chip assembly as described in claim 5, wherein the thickness of the first reflective barrier is less than the thickness of the second reflective barrier. 7. The LED chip assembly as claimed in claim 6, wherein the sum of the thickness of the first reflective barrier and the thickness of the second reflective barrier is less than or equal to the height of the LED chip. 8. The LED chip assembly as described in claim 1 or 7, wherein the LED chip has a vertical structure. 9. The LED chip assembly as claimed in claim 1, wherein the common electrode layer is a transparent conductive layer. 10. A display device, characterized in that it comprises: an LED chip assembly as described in any one of claims 1-9.