CN223229702U - Test structure and integrated circuit for electrical property detection - Google Patents

Abstract

The utility model provides a test structure and an integrated circuit for electrical detection, wherein the test structure comprises at least one test unit and an isolation component connected with the test unit, and the isolation component is arranged on a pin connection line of the test unit and is used for controllably disconnecting external connection of the test unit when the electrical test is performed on at least one test unit. The utility model realizes the purpose of isolating the test unit to be tested from the peripheral circuit structure with minimum area expenditure, thereby controllably isolating the electrical signals applied or flowing out of the test unit to be tested, avoiding the influence of the electric potential of other test units or circuit structures in the peripheral circuit on the electrical test of the test unit to be tested, and ensuring the reliability and the accuracy of the electrical test result.

Description

Test structure and integrated circuit for electrical property detection

Technical Field

The utility model belongs to the technical field of semiconductor design and production, and particularly relates to a test structure for electrical property detection and an integrated circuit.

Background

Electrical failure analysis (Electronical Failure Analysis, EFA) is an electrical measurement-based failure analysis, the primary purpose of which is to determine the failed test structure in the chip. The electrical failure analysis is based on the detection of functionality by providing an electrical test signal to the chip, analyzing whether the electrical test results match the theoretical analysis, to determine the failed test structure.

In the field of semiconductor electrical testing, it is often necessary to analyze the test structure for electrical failure after the test structure has been tested for failure. In general, the secondary electrical verification is performed on the test structure by using a nano probe, then the specific failure position is located by using technical means such as EMMI (Emission Microscope, light radiation microscope), obirch (Optical Beam Induced RESISTANCE CHANGE, photoresistance change microscope), and finally the specific failure site is confirmed by using FIB (Focused Ion Beam), TEM (Transmission Electron Microscope ), so as to determine the root cause of the process problem, so that the corresponding process improvement is performed on the process problem later.

However, when the secondary electrical verification is performed on the test structure through the nano probe, the connection between the test structure and other circuit structures cannot be controlled to be in a disconnected state due to the limitation of the pin number of the nano probe, so that mutual interference cannot be avoided, and the secondary electrical verification of the nano probe fails.

Disclosure of utility model

The present utility model provides a test structure and an integrated circuit for electrical testing to solve all or part of the above problems in the prior art, so as to avoid interference of peripheral circuits on the testing result during the electrical testing of the test unit.

In order to achieve the above object, the present utility model provides a test structure for electrical inspection, the test structure comprising at least one test unit and an isolation assembly connected to the test unit,

The isolation component is arranged on a pin connection line of the test unit and used for controllably disconnecting the external connection of the test unit when at least one test unit is subjected to electrical test.

In some embodiments, the isolation component includes at least one of an E-fuse cell, a tri-state flip-flop, and a MOS transistor.

In some embodiments, the E-fuse comprises at least one of:

A polysilicon fuse unit, niSiPT fuse units, and a metal fuse unit.

In some embodiments, the isolation assembly includes an E-fuse unit and a test pad, wherein,

The E-fuse unit comprises a fuse element which is connected in series to a pin connecting wire of the test unit;

The test pad is configured to perform a failure test on the test unit, and includes:

A first bonding pad connected between the test unit and the fuse element, and

A second bonding pad connected to an end of the fuse element remote from the first bonding pad;

in the first state, the test unit is connected with the corresponding pins through the fusing element, and in the second state, the fusing element is broken to disconnect the external connection of the test unit.

In some embodiments, the first pad and the second pad are mini-pads.

In some embodiments, the test unit comprises at least one of:

semiconductor device, via link structure, resistive structure, and capacitive structure.

The utility model also provides an integrated circuit comprising the test structure of any one of the above embodiments and a test circuit electrically connected to the test structure, the test circuit being configured to perform a failure test on the test structure;

The isolation assembly is connected between the test unit and the test circuit and is used for controllably disconnecting the electrical connection with the test circuit when at least one test unit is subjected to electrical testing.

In some embodiments, the test structure includes a first test unit and a second test unit, and two isolation components respectively connected to the first test unit and the second test unit, where the two isolation components are respectively disposed on pin wires of the first test unit and the second test unit and connected between the corresponding test units and the test circuits.

In some embodiments, the test circuit includes an addressing circuit and a switching circuit,

The addressing circuit is connected with the switching circuit, the addressing circuit outputs an address signal to control the on-off state of a switch in the switching circuit, the switching circuit is connected with the test structure, and the switching circuit selects a designated test unit in the test structure through the on-off state of the switch;

An external test device applies test signals to selected ones of the test cells through the test circuit.

The test structure for electrical property detection and the integrated circuit comprise at least one test unit and the isolation component connected with the test unit, wherein the isolation component is arranged on the pin connecting line of the test unit, and the external connection of the test unit is controllably disconnected when the electrical property test is performed on at least one test unit, so that the purpose of isolating the test unit to be tested from the peripheral circuit structure is realized with minimum area overhead, further, the electrical signals of the test unit to be tested are controllably isolated, the influence of the electric potential of other test units or circuit structures in the peripheral circuit on the electrical property test of the test unit to be tested is avoided, and the reliability and the accuracy of the electrical property test result are ensured.

Drawings

In order to more clearly illustrate the technical solutions of specific embodiments of the present utility model, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.

Fig. 1 is a schematic diagram of a test structure for electrical testing according to an embodiment of the present utility model.

FIG. 2 is a schematic view of a spacer assembly according to an embodiment of the present utility model.

Fig. 3 is a schematic diagram of a test structure for electrical testing before programming a isolation device according to an embodiment of the present utility model.

Fig. 4 is a schematic diagram of a test structure for electrical testing after programming a isolation device according to an embodiment of the present utility model.

Fig. 5 is a schematic structural diagram of an integrated circuit according to a second embodiment of the present utility model.

Fig. 6 is a schematic structural diagram of an integrated circuit in the related art.

Fig. 7 is a schematic diagram of another structure of an integrated circuit according to a second embodiment of the utility model.

The figure illustrates 1, test structure, 10/11, test unit, 111, first test unit, 112, second test unit, 12, isolation component, 121, E-fuse unit, 1211, fuse element, 122, test pad, 1221, first pad, 1222, second pad, 13, pin, 20/2, test circuit, 3, integrated circuit.

Detailed Description

The foregoing and other features, aspects, and advantages of the present utility model will become more apparent from the following detailed description of a preferred embodiment, which proceeds with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or rear, etc., are only referring to the directions of the attached drawings. Thus, the directional terminology is used for purposes of illustration and is not intended to be limiting of the utility model.

The test structure comprises test units, wherein the test structure can be formed by one test unit or a plurality of test units according to different test conditions. The following description describes two test structures and test structures formed by combining a plurality of test units and/or a plurality of test units with reference to the accompanying drawings.

Embodiment one:

The test structure 1 provided in this embodiment can be used in various electrical tests, such as process monitoring, device characteristic testing, reliability testing, parasitic parameter testing, and the like. Critical data and feedback can be obtained through the test structure 1, helping to optimize the manufacturing process, improve device performance and ensure product quality.

Typically, after a test structure failure is tested, an electrical failure analysis of the test structure is required. And carrying out secondary electrical verification on the test result of the test structure through failure analysis, and determining the root cause of the process problem so as to carry out corresponding process improvement on the process problem later.

At present, a mode of contact needle insertion of a nano probe platform is mainly adopted to carry out secondary electrical verification on a test structure. The nanoprobe station is a precision tool necessary for chip testing, and as a test interface, the nanoprobe station is conventionally equipped with 6 ultra-fine nanoprobes vertically arranged. The nano probe platform is connected with the tester and the test structure through the nano probe, and can perform various electrical measurements, including current-voltage characteristics (I-V curve), capacitance measurement, resistance measurement and the like.

However, when the secondary electrical verification is performed on the test structure through the nano probe, the connection between the test structure and other circuit structures cannot be controlled to be in a disconnected state due to the limitation of the pin number of the nano probe, so that mutual interference cannot be avoided, and the secondary electrical verification of the nano probe fails.

In view of the above-mentioned deficiencies of the related art, the present application provides a test structure 1 for electrical inspection. Referring to fig. 1, a test structure 1 provided in this embodiment includes at least one test unit 11 and an isolation assembly 12 connected to the test unit 11.

In this embodiment, the test unit 11 may optionally include at least one of a semiconductor device, a via chain structure, a resistive structure, and a capacitive structure.

The Semiconductor device may be a MOS (Metal-Oxide-Semiconductor) transistor, a diode, a resistor, a capacitor, an amplifier, or the like. Illustratively, the MOS transistor may be, but not limited to, NMOS (N-Metal-Oxide-Semiconductor), PMOS (P-Metal-Oxide-Semiconductor), or CMOS (Complementary Metal Oxide Semiconductor, complementary Metal-Oxide-Semiconductor) integrating NMOS and PMOS.

The via chain structure Via Chain Structure is an arrangement structure in which a plurality of vias are connected in series to form a chain. Each via is connected to a previous via and a next via, forming a continuous conductive link. The via chain structure can be used to detect the connection performance of the via hole (via) on the semiconductor chip and the quality of the manufacturing process.

The resistance structure can be an ohmic resistance structure for measuring the resistivity and contact resistance of a material, and can also be an on-chip resistance (SHEET RESISTANCE) test structure, such as a Van der Pauw structure, wherein the resistance of a sample is measured by using four probes, the on-chip resistance is obtained through mathematical calculation, and a linear four-Probe (Linear Four-Point Probe) structure, wherein four probes are placed on a straight line, the voltage is measured by using two middle probes, and the current is applied to two outer probes, so that the on-chip resistance is obtained through calculation.

The capacitor structure includes, but is not limited to, a capacitor chain structure (Capacitor Chain Structure), i.e., a chain structure formed by connecting a plurality of capacitors in series or parallel, a capacitor array structure (Capacitor Array Structure), i.e., a capacitor array structure formed by arranging a plurality of capacitors, for testing the performance of different capacitors and performing statistical analysis, or a single capacitor test structure (Single Capacitor Test Structure) for performing detailed tests on a single capacitor.

In this embodiment, each test structure 1 may include at least one test unit 11, and the test structure 1 may be formed by one test unit 11 or may be a set of a plurality of test units 11.

The isolation component 12 is disposed on a pin 13 of the test unit 11, and is configured to controllably disconnect the external connection of the test unit 11 when performing an electrical test on at least one of the test units 11. The isolation assembly 12 can be provided in a plurality, and can be flexibly designed according to the number of pins 13 of the test unit 11 and the test requirement. In some embodiments, the test unit 11 has at least two pins 13, the test structure 1 includes at least two isolation components 12 corresponding to the pins 13, and at least two isolation components 12 are respectively connected in series to each pin 13 connection line of the test unit 11, so as to separate signal paths of different pins 13 and prevent signal interference.

Of course, in other embodiments, the isolation components 12 may be alternately arranged on different pins 13 of the test unit 11 under the preconditions of ensuring the test requirements and the isolation effect, so as to provide flexible signal isolation under different test conditions.

When one test unit 11 is included in the test structure 1, the isolation assembly 12 controllably isolates the test unit 11 such that the test unit 11 is individually accessed for testing, and when a plurality of (greater than 1) test units 11 are included in the test structure 1, the plurality of isolation assemblies 12 controllably isolate the corresponding test unit 11, respectively, such that each test unit 11 may be individually accessed for testing.

It should be noted that isolation assembly 12 may be any electronic device capable of providing electrical connection between points in an electrical circuit and controllably breaking electrical connection between different points.

Illustratively, the isolation unit may be an E-fuse unit 121.E-fuse cell 121 (E-fuse cell) is a programmable, non-volatile memory technology, and eFuse cells may change the conductance state of a circuit through current, voltage, laser, etc. programming operations to achieve signal isolation. In some embodiments, the E-fuse cell 121 includes at least one of a polysilicon fuse cell, niSiPT fuse cell, and a metal fuse cell. In the practical application process, different types of E-fuse units 121 can be flexibly designed and applied as isolation units according to the requirements of programming modes, reliability, environmental conditions and power consumption, so as to meet the requirements of various electrical tests.

As shown in fig. 2, in some embodiments, the isolation assembly 12 includes an E-fuse unit 121 and a test pad 122.

The E-fuse unit 121 includes a fuse element 1211. The fuse element 1211 is connected in series to the pin 13 connection of the test unit 11. Alternatively, the fuse element 1211 may be constructed of one or more metallic or semiconductor materials, the physical state of which may be changed by programming, the fuse element 1211 may undergo a permanent physical change, such as melting or breaking, to change the electrical conductance state of the circuit. Since the physical change of eFuse cells is irreversible, there is a high reliability and stability.

The test pads 122 are used for performing failure test on the test unit 11, and include a first pad 1221 and a second pad 1222. A first pad 1221 is connected between the test unit 11 and the fuse element 1211, and a second pad 1222 is connected to an end of the fuse element 1211 remote from the first pad 1221.

With the above arrangement, the first pads 1221 and the second pads 1222 are connected to both ends of the fuse element 1211, and the fuse element 1211 can be programmed through the first pads 1221 and the second pads 1222, thereby controlling the connection state of the test unit 11 with the peripheral circuit, and controllably disconnecting the external connection of the test unit 11. In addition, the first pad 1221 is connected between the test unit 11 and the fuse element 1211, and in the disconnected state of the fuse element 1211, the measuring loop can be directly formed by connecting a nanoprobe as a test pad. When the test unit is measured, the nano probe connected to the measuring instrument is landed on the first pad 1221, and the measurement signal enters the first pad 1221 through the nano probe, and then enters the test unit connected to the first pad 1221, and the test unit is measured to detect whether a failure defect exists. Therefore, by matching with the control of the measuring instrument and the software, the test signal and the feedback signal are fed into the test unit 11 through the nano probe, and the failed test structure 1 can be screened out, so that the secondary electrical verification is realized.

Specifically, as shown in fig. 3, before the electrical test, the test structure 1 is in the first state, and at this time, the test unit 11 is connected via the fuse element 1211 and the corresponding pin 13, and the fuse element 1211 is used as a normal connection wire. At the time of electrical testing, the fuse element 1211 may be programmed from an "on state" to an "off state" by the first pad 1221 and the second pad 1222. Specifically, the surface of the sample can be observed through an optical or electron microscope, the target test unit 11 can be found, two nano probes are precisely positioned on the first bonding pad 1221 and the second bonding pad 1222 of the test unit 11, short-time current/voltage is applied, when enough current/voltage is applied, the fusing element 1211 can be permanently melted or broken, so that electrical isolation is realized, and the external connection of the test unit 11 is disconnected.

As shown in FIG. 4, after programming fuse element 1211, fuse element 1211 melts or breaks and test structure 1 is in the second state. In the second state, the nano-probe is precisely positioned on the first pad 1221 close to the test unit 11, and appropriate test conditions, such as voltage or current range, test mode, test environment, and other electrical parameters, are set, and the test structure 1 is electrically tested, including measuring resistance, current-voltage characteristics, leakage current, and the like. And processing and analyzing according to the acquired data to realize secondary electrical verification of the test structure 1. Illustratively, through the plurality of first pads 1221 in the plurality of isolation components 12, the resistance value of the test cell may be measured using a two-terminal method or a four-terminal kelvin method for determining conductivity, contact resistance, device performance, evaluating process window, and the like.

In some embodiments, the first pads 1221 and the second pads 1222 are Mini pads (Mini pads). The mini pad is smaller than the standard pad, the mini pad and the nano probe are matched for use in electrical measurement, the nano probe can accurately measure in a tiny space of the mini pad, and the mini pad can be suitable for more compact or high-density circuit layout, so that the space utilization rate and the electrical performance of the test structure 1 are optimized.

Of course, in other embodiments, the isolation unit may be a MOS transistor, a tri-state flip-flop, or other electronic device. In some embodiments, by controlling the tri-state flip-flop to be in a high impedance state, its output is in an off state, i.e., not driving any current, equivalent to a circuit break, thereby providing reliable signal isolation.

In other embodiments, the isolation unit may be a PMOS transistor or an NMOS transistor, where the PMOS transistor is turned on under conditions including a gate voltage less than a source voltage and an absolute value of the source-gate voltage greater than a threshold voltage, and the NMOS transistor is turned on under conditions including a gate voltage greater than the source voltage and an absolute value of the source-gate voltage greater than the threshold voltage. The turn-off of the PMOS transistor can be achieved by controlling the test pad 122 to output a corresponding control voltage.

Embodiment two:

Referring to fig. 5, the present embodiment provides an integrated circuit 3, which includes the test structure 1 and the test circuit 2 electrically connected to the test structure 1. The implementation principle and the generated technical effects of the test structure 1 are the same as those of the first embodiment, and for brevity, reference may be made to the corresponding contents of the first embodiment.

The test circuit 2 is used for performing failure test on the test structure 1. Different circuit structures can be selected and used in different test environments, and the application is not limited herein.

In some embodiments, at least one test unit 11 in the test structure 1 is directly connected to a PAD (PAD) of the test circuit 2, respectively. The isolation component 12 is disposed on a pin 13 of the test unit 11, and is connected between the test unit 11 and the test circuit 2. The electrical connection to the test circuit 2 is controllably disconnected when an electrical test is performed on at least one of said test units 11.

In other embodiments, the test structure 1 comprises a plurality of test units 11 (two or more), the test circuit 2 comprises an addressing circuit and a switching circuit, the addressing circuit and the switching circuit are connected, the plurality of test units 11 share the test circuit 2, and an external test device applies test signals to selected ones of the test units 11 through the test circuit 2.

Specifically, for a test structure 1 containing more test units 11 (Device Under Test, DUTs), the entire DUT area may be divided and then separately provided with switching circuits and addressing circuits. The addressing circuit outputs address signals to control row and column addresses so as to control on-off states of switches in the switching circuit, the switching circuit is connected with the test structure, and the switching circuit selects a designated test unit 11 in the test structure through the on-off states of the switches.

After the designated test unit 11 is selected, the test signals of the external test equipment can be individually input into the selected test unit 11 to perform the corresponding electrical test. After the designated test unit 11 is determined by addressing, the nanoprobe station connects the tester with the selected test unit 11 through nanoprobes, and applies test signals to the selected test unit 11 for failure verification.

However, as shown in fig. 6, in the related art, when two test units 10 are directly connected to the test circuit 2, respectively, without providing isolation components, the test units 10 not selected by the addressing circuit, the corresponding test circuits 20 such as the switching circuit and the addressing circuit, increase leakage currents, which may reach several tens or even hundreds of nanoamperes, thereby resulting in inaccurate measurement of the test units 10.

Referring to fig. 7, in the present embodiment, the test structure 1 includes a first test unit 111 and a second test unit 112, and two isolation components respectively connected to the first test unit 111 and the second test unit 112, and by respectively disposing the two isolation components on the connection lines of the pins 13 of the first test unit 111 and the second test unit 112 and connecting the two isolation components between the corresponding test units 11 and the test circuit 2, when performing an electrical test on the first test unit 111, the electrical connection between the test circuit 2 and the second test unit 112 can be controllably disconnected, so that the purpose of isolating the first test unit 111 to be tested from the peripheral circuit structure is achieved with minimum area overhead, and further the electrical signals applied to or flowing out of the first test unit 111 are controllably isolated, so that the influence of the electrical potential of the second test unit 112 and the test circuit 2 in the peripheral circuit on the electrical test of the first test unit 111 to be tested is avoided, and reliability and accuracy of the electrical test result are ensured.

According to the test structure without isolation components shown in fig. 6 and the test structure with isolation components shown in fig. 7, the electrical test is performed by using the test circuit 2 and the secondary electrical verification is performed by using the nano probe. The test data are shown in table 1 below. Wherein:

In test example 1, the MOS transistor leakage current (MOS loff) test conditions are S=G=B=0V, D=Vdd;

In test example 2, open-Via (Via chain open) test conditions were pin1=vdd, pin2=0v;

In test example 3, the Metal chain (Metal LK) test condition is pin1=vdd, pin2=0v;

Table 1 electrical test meter

As can be seen from table 1, the test data of the electrical verification using the nano probe and the test data of the electrical test using the test circuit have significantly larger deviation, which indicates that when the isolation component is not used, the connection between the test unit 10 to be tested and the peripheral circuit is in an uncontrollable state (i.e. whether the connection is at a high potential or a low potential is uncertain), and it is difficult to avoid the interference of the test circuit 20 and other test units 10 connected to the test circuit to the test data of the test unit 10 to be tested.

In the test structure 1 of the present application, the isolation component 12 is connected between the test unit and the test circuit, and is controllably disconnected from the electrical connection with the test circuit when performing an electrical test on at least one of the test units 11, and the test data for performing an electrical test by using the nanoprobe in the table matches with the test data for performing an electrical test by using the test circuit, so that the purpose of isolating the test unit 11 to be tested from the peripheral circuit structure is achieved with minimum area overhead, and the reliability and the accuracy of the electrical test result are ensured.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the utility model, which are described in detail and are not to be construed as limiting the scope of the utility model. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the utility model, which are all within the scope of the utility model. Accordingly, the scope of protection of the present utility model is to be determined by the appended claims.

Claims (9)

1. A test structure for electrical inspection is characterized in that the test structure comprises at least one test unit and an isolation component connected with the test unit,

The isolation component is arranged on a pin connection line of the test unit and used for controllably disconnecting the external connection of the test unit when at least one test unit is subjected to electrical test.

2. The test structure of claim 1, wherein the isolation component comprises at least one of an E-fuse cell, a tri-state flip-flop, and a MOS transistor.

3. The test structure of claim 1, wherein the E-fuse unit comprises at least one of:

A polysilicon fuse unit, niSiPT fuse units, and a metal fuse unit.

4. The test structure of claim 2, wherein the isolation assembly comprises an E-fuse cell and a test pad, wherein,

The E-fuse unit comprises a fuse element which is connected in series to a pin connecting wire of the test unit;

The test pad is configured to perform a failure test on the test unit, and includes:

A first bonding pad connected between the test unit and the fuse element, and

A second bonding pad connected to an end of the fuse element remote from the first bonding pad;

in the first state, the test unit is connected with the corresponding pins through the fusing element, and in the second state, the fusing element is broken to disconnect the external connection of the test unit.

5. The test structure of claim 4, wherein the first pad and the second pad are mini-pads.

6. The test structure of claim 1, wherein the test unit comprises at least one of:

semiconductor device, via link structure, resistive structure, and capacitive structure.

7. An integrated circuit comprising the test structure of any one of claims 1-6 and a test circuit electrically connected to the test structure, the test circuit for performing a failure test on the test structure;

The isolation assembly is connected between the test unit and the test circuit and is used for controllably disconnecting the electrical connection with the test circuit when at least one test unit is subjected to electrical testing.

8. The integrated circuit of claim 7, wherein the test structure comprises a first test unit and a second test unit, and two isolation components respectively connected with the first test unit and the second test unit, wherein the two isolation components are respectively arranged on pin wires of the first test unit and the second test unit and connected between the corresponding test units and the test circuit.

9. The integrated circuit of claim 7, wherein the test circuit comprises an addressing circuit and a switching circuit,

The addressing circuit is connected with the switching circuit, the addressing circuit outputs an address signal to control the on-off state of a switch in the switching circuit, the switching circuit is connected with the test structure, and the switching circuit selects a designated test unit in the test structure through the on-off state of the switch;

An external test device applies test signals to selected ones of the test cells through the test circuit.