CN206379929U - A kind of gain-adaptive error amplifier - Google Patents

Abstract

The utility model discloses a kind of gain-adaptive error amplifier, including level shift circuit, operation transconductance amplifying circuit and comparison circuit.Level shift circuit makes the incoming level of operation transconductance amplifying circuit meet normal work requirement；Operation transconductance amplifying circuit provides current offset to reduce power consumption using metal-oxide-semiconductor common source configuration current mirror by the use of dual-polar triode as differential pair tube for its differential pair tube, to ensure to provide bigger gain；Comparison circuit utilizes feedback arrangement control ratio compared with circuit output Slew Rate, so as to export the control signal of operation transconductance amplifying circuit；Amplitude limiter circuit carries out amplitude limit to operation transconductance amplifying circuit output voltage.The utility model reduces the power supply output ripple in load current stable application, so as to reduce system power dissipation, but influences very little to load transient characteristic simultaneously.

Description

A Gain Adaptive Error Amplifier

technical field

The utility model relates to the technical field of integrated circuit design, in particular to a gain adaptive error amplifier.

Background technique

The error amplifier is an indispensable module in analog integrated circuits and hybrid integrated circuits. It is commonly used in circuit systems such as power amplifiers and DC-DC converters. It is used to compare the difference between an input voltage and a reference external reference voltage and convert the difference The value is amplified to provide a difference voltage for other circuit modules, and its characteristics affect the performance of the entire system to a large extent.

For the DC-DC power management system in PWM control mode, the output ripple characteristic is a very important topic in system design. As a power supply, in order to avoid damage to the load, the output ripple should be as small as possible. The output ripple of the PWM DC-DC power management system is mainly affected by the error amplifier. In order to improve the transient characteristics of the power management system, the traditional error amplifier has a large transconductance gain as much as possible. Under the same input voltage difference condition , output a larger current. The structure of the error amplifier proposed later is mainly to improve the transient characteristics when the load current changes. Although the transient characteristics when the load current changes are improved, it leads to a large ripple when the load current is stable. output.

Utility model content

The technical problem to be solved by the utility model is that the performance of the existing error amplifier is not good enough, and a gain self-adaptive error amplifier is provided.

In order to solve the above problems, the utility model is achieved through the following technical solutions:

A kind of gain self-adaptive error amplifier, comprises level shifting circuit, operational transconductance amplifying circuit and comparison circuit; Level shifting circuit, input connects external reference voltage V _ref1 and external feedback voltage v _FB ; Makes operational transconductance amplifying circuit The input level meets the normal working requirements; the operational transconductance amplifier circuit, the input is connected to the external bias voltage V _nbias1 , and the output of the level shift circuit and the comparison circuit; the bipolar triode is used as a differential pair of tubes, and the MOS tube is used The common source structure current mirror provides current bias for its differential pair tubes to reduce power consumption and ensure greater gain; the comparison circuit, the input is connected to the external reference voltage V _ref2 and the external feedback voltage V _FB , and the operational transconductance amplifier circuit The bias output terminal V _pbias ; use the feedback structure to control the output slew rate of the comparison circuit, thereby outputting the control signal of the operational transconductance amplifier circuit; the limiter circuit, the input is connected to the external bias voltage V _nbias2 , and the output of the operational transconductance amplifier circuit Terminal V _e ; limit the output voltage of the operational transconductance amplifier circuit.

The above level shifting circuit includes bipolar transistors Q1~Q2, and resistors R1~R2; the base of bipolar transistor Q1 is connected to external reference voltage V _ref1 , the base of bipolar transistor Q2 is connected to external feedback voltage v _FB ; The collectors of transistors Q1 and Q2 are grounded to GND; the emitters of bipolar transistors Q1 and Q2 are connected to resistors R1 and R2 respectively, and the other ends of resistors R1 and R2 are connected to power supply VDD; the emitter of bipolar transistor Q1 is used as a level shift The first output terminal of the circuit is connected to the first input terminal of the operational transconductance amplifier circuit; the emitter of the bipolar transistor Q2 is used as the second output terminal of the level shift circuit, and is connected to the second input terminal of the operational transconductance amplifier circuit end.

The bipolar transistors Q1 and Q2 in the above level shift circuit are PNP type bipolar transistors.

The above operational transconductance amplifier circuit includes MOS transistors MP1~MP5, MOS transistors MN1~MN5, bipolar transistors Q3~Q6, and resistor R3; the sources of MOS transistors MN1~MN5 are all connected to ground GND; MOS transistors MP1, MP2, The sources of MP3 and MP5 are all connected to the power supply VDD; the gates of the MOS transistors MN1, MN2 and MN3 are connected, and at the same time connected to the external bias voltage V _nbias1 ; the gates of the MOS transistors MP1, MP2, MP3 and MP5 are connected, Commonly used as the bias output terminal V _pbias of the operational transconductance amplifier circuit, and connected to the bias input terminal V _pbias of the comparison circuit; the drain of the MOS transistor MN1 is connected to the drain and gate of the MOS transistor MP1; the drain of the MOS transistor MN2 The drains are connected to the emitters of the bipolar transistors Q3 and Q5; the drains of the MOS transistor MN3 are connected to the emitters of the bipolar transistors Q4 and Q6; the collectors of the bipolar transistors Q3 and Q4 are connected to the drains of the MOS transistor MP2; the bipolar transistors The collectors of Q5 and Q6 are connected to the drain of MOS transistor MP3; the bases of bipolar transistors Q3 and Q4 are jointly used as the first input terminal of the operational transconductance amplifier circuit and connected to the first output terminal of the level shift circuit; The bases of the transistors Q5 and Q6 are jointly used as the second input terminal of the operational transconductance amplifier circuit and connected to the second output terminal of the level shift circuit; the gate and drain of the MOS transistor MN4 are short-circuited and connected to the MOS transistor MN4 The gate of MN5 is connected to the drain of MOS transistor MP3; the gate of MOS transistor MP4 is used as the third input terminal of the operational transconductance amplifier circuit and connected to the output terminal of the comparison circuit; the source of MOS transistor MP4 is connected to bipolar transistor Q5 and the base of Q6 and the emitter of Q2 in the level shift circuit; resistor R3 is connected between the drain of MOS transistor MP5 and the drain of MOS transistor MP4; the drain of MOS transistor MP5 and the drain of MOS transistor MN5 connected together as the operational transconductance amplifier circuit, that is, the output terminal V _e of the entire amplifier, and connected to the output terminal of the limiting circuit.

The MOS tubes MP1-MP5 in the above operational transconductance amplifier circuit are PMOS type MOS tubes; the MOS tubes MN1-MN5 are NMOS type MOS tubes; the bipolar transistors Q3-Q6 are NPN type bipolar transistors.

The comparison circuit above includes MOS transistors MN7~MN9, MOS transistors MP7~MP12, inverters INV1 and INV2; the gate of MOS transistor MP9 is connected to the external reference voltage _Vref2 ; the gates of MOS transistors MP10 and MP11 are connected to the external feedback voltage _vFB ; The sources of the MOS transistors MP9, MP10 and MP11 are connected to the drain of the MOS transistor MP7; the gates of the MOS transistors MP7 and MP8 are connected to serve as the bias input terminal V _pbias of the comparator circuit, and connected to the operational transconductance amplifier The bias output terminal V _pbias of the circuit; the sources of the MOS transistors MP7 and MP8 are connected to the power supply VDD; the source and drain of the MOS transistor MN7 are short-circuited, and connected to the gate of the MOS transistor MN8 and the drain of the MOS transistor MP9 ; The drains of the MOS transistors MN8, MP10 and MP12 are connected, and are connected to the gate of the MOS transistor MN9; the drain of the MOS transistor MP11 is connected to the source of the MOS transistor MP12; the sources of the MOS transistors MN7, MN8 and MN9 The pole is grounded to GND; the drains of MOS transistors MN9 and MP8 are connected, and are connected to the input terminals of inverters INV1 and INV2; the gate of MOS transistor MP12 is connected to the output terminal of inverter INV1; the inverter INV2 The output end of the comparison circuit is used as the output end of the comparison circuit, and is connected to the third input end of the operational transconductance amplifier circuit.

The MOS transistors MN7-MN9 in the above comparison circuit are NMOS MOS transistors; the MOS transistors MP7-MP12 are PMOS MOS transistors; the inverters INV1 and INV2 are CMOS inverters.

Above-mentioned limiting circuit comprises diode D1, MOS tube MN6, and MOS tube MPX; The anode of diode D1 is used as the output terminal of limiting circuit, and is connected with the output terminal V _e of operation transconductance amplifying circuit; The cathode of diode D1 is connected with MOS tube The drain of MN6 is connected to the drain of the MOS transistor MPX; the gate of the MOS transistor MPX is connected to the drain, and the source of the MOS transistor MPX is connected to the power supply VDD. The source of the MOS transistor MN6 is grounded to GND; the gate of the MOS transistor MN6 is connected to the external bias voltage V _nbias2 .

The above limiting circuit MOS tube MN6 is an NMOS type MOS tube, and the MOS tube MPX is a PMOS type MOS tube.

Compared with the prior art, the utility model has the following characteristics:

1. Adopt voltage comparison detection method to generate adaptive control signal;

2. The voltage sampling current summation negative feedback structure is used to reduce the voltage gain of the error amplifier, thereby adaptively reducing the differential voltage output of the error amplifier;

3. The output ripple of the power supply in the application of load current stabilization is reduced, thereby reducing the power consumption of the system, but at the same time, it has little influence on the transient characteristics of the load.

Description of drawings

Fig. 1 is a schematic diagram of the circuit structure of the utility model.

Fig. 2 is a schematic structural diagram of a comparison circuit of the present invention.

Fig. 3 is the simulation result of the output ripple voltage when the DC-DC power management chip 7A outputs a large current based on the error amplifier of the present invention and the traditional open-loop error amplifier circuit.

detailed description

Below in conjunction with accompanying drawing and embodiment, describe the technical scheme of the utility model in detail:

A gain adaptive error amplifier, as shown in Figure 1, includes a level shift circuit, an operational transconductance amplifier (OTA), a comparison circuit and a limiter circuit.

The level shifting circuit makes the input level of the operational transconductance amplifying circuit meet the normal working requirement. In a preferred embodiment of the present invention, the above-mentioned level shifting circuit includes bipolar transistors Q1-Q2, and resistors R1-R2. The bipolar transistors Q1-Q2 are PNP type bipolar transistors. The collectors of bipolar transistors Q1 and Q2 are grounded to GND. The emitters of bipolar transistors Q1 and Q2 are respectively connected to resistors R1 and R2. The base of the bipolar transistor Q1 is connected to the external reference voltage V _ref1 , and the base of the bipolar transistor Q2 is connected to the changing feedback voltage v _FB . The other ends of the resistors R1 and R2 are both connected to the power supply VDD. The emitter of the bipolar transistor Q1 is connected to the bases of the bipolar transistors Q3 and Q4 in the operational transconductance amplifier circuit, and the emitter of the bipolar transistor Q2 is connected to the bases of the bipolar transistors Q5 and Q6 in the operational transconductance amplifier circuit.

The operational transconductance amplifier circuit uses a MOS tube common source structure current mirror to provide current bias for the differential pair tube of the operational amplifier to reduce power consumption. NPN type bipolar transistors are used as differential pair tubes to ensure greater gain. In a preferred embodiment of the present invention, the operational transconductance amplifying circuit includes MOS transistors MP1-MP5, MOS transistors MN1-MN5, bipolar transistors Q3-Q6, and a resistor R3. Among them, the MOS tubes MP1-MP5 are PMOS type MOS tubes. The MOS transistors MN1-MN5 are NMOS type MOS transistors. The bipolar transistors Q3-Q6 are NPN type bipolar transistors. The sources of the MOS transistors MN1 - MN5 are all connected to the ground GND. The sources of the MOS transistors MP1, MP2, MP3 and MP5 are all connected to the power supply VDD. The gates of the MOS transistors MN1, MN2 and MN3 are connected together, and at the same time connected to the external bias voltage V _nbias1 . The gates of the MOS transistors MP1, MP2, MP3 and MP5 are connected to each other, and are connected to the gates of the MOS transistors MP7 and MP8 of the comparison circuit. The drain of the MOS transistor MN1 is connected to the drain and the gate of the MOS transistor MP1. The drain of the MOS transistor MN2 is connected to the emitters of the bipolar transistors Q3 and Q5. The drain of the MOS transistor MN3 is connected to the emitters of the bipolar transistors Q4 and Q6. The collectors of the bipolar transistors Q3 and Q4 are connected to the drain of the MOS transistor MP2. The collectors of the bipolar transistors Q5 and Q6 are connected to the drain of the MOS transistor MP3. The bases of the bipolar transistors Q3 and Q4 are connected to the emitter of the bipolar transistor Q1 of the level shifting circuit. The bases of the bipolar transistors Q5 and Q6 are connected to the emitter of the bipolar transistor Q2 of the level shifting circuit. The gate and drain of the MOS transistor MN4 are short-circuited, and connected to the gate of the MOS transistor MN5 and the drain of the MOS transistor MP3. The gate of the MOS transistor MP4 is connected to the output terminal of the inverter INV2 of the comparison circuit. The source of the MOS transistor MP4 is connected to the bases of the bipolar transistors Q5 and Q6 and the emitter of Q2 in the level shift circuit. The resistor R3 is connected between the drain of the MOS transistor MP5 and the drain of the MOS transistor MP4. The drain of the MOS transistor MP5 is connected to the drain of the MOS transistor MN5, which are used as the output terminal V _e of the operational transconductance amplifier circuit, that is, the output terminal of the entire gain adaptive error amplifier, and connected to the diode D1 and the resistor in the limiting circuit. one end of R3.

The comparison circuit monitors the large signal fluctuation of the DC-DC output voltage, and uses the feedback structure to control the output slew rate of the comparison circuit, thereby outputting the control signal of the transconductance amplifier. A current mirror is used to provide bias current for the differential pair tube, and a two-stage open-loop operational amplifier structure is used to realize a large-gain comparison circuit. In a preferred embodiment of the present invention, the comparison circuit includes MOS transistors MN7-MN9, MOS transistors MP7-MP12, and inverters INV1 and INV2. The MOS tubes MN7-MN9 are NMOS MOS tubes; the MOS tubes MP7-MP12 are PMOS MOS tubes; the inverters INV1 and INV2 adopt a traditional CMOS inverter structure. The gate of the MOS transistor MP9 is connected to the external reference voltage V _ref2 . The gates of the MOS transistors MP10 and MP11 are connected to the external feedback voltage v _FB . The sources of the MOS transistors MP9, MP10 and MP11 are connected to the drain of the MOS transistor MP7. The gates of the MOS transistors MP7 and MP8 are connected to each other, and are connected to the gate of the MOS transistor MN1 of the operational transconductance amplifier circuit, and an external voltage bias is provided to provide a suitable operating point. The sources of the MOS transistors MP7 and MP8 are connected to the power supply VDD. The source and drain of the MOS transistor MN7 are short-circuited and connected to the gate of the MOS transistor MN8 and the drain of the MOS transistor MP9. The drains of the MOS transistors MN8, MP10 and MP12 are connected to each other, and are connected to the gate of the MOS transistor MN9. The drain of the MOS transistor MP11 is connected to the source of the MOS transistor MP12. The sources of the MOS transistors MN7, MN8 and MN9 are grounded to GND. The drains of the MOS transistors MN9 and MP8 are connected, and are connected with the input terminals of the inverters INV1 and INV2. The gate of the MOS transistor MP12 is connected to the output terminal of the inverter INV1. The output terminal of the inverter INV2 is used as the output terminal of the comparison circuit, and is connected to the gate of the MOS transistor MP4 of the operational transconductance amplifier circuit. See Figure 2.

The limiting circuit limits the output voltage. The limiter circuit is connected with the output of the operational transconductance amplifier circuit, and it utilizes the characteristic that the conduction voltage drop of the diode is 0.7V to limit the output amplitude of the transconductance amplifier within a reasonable range. In a preferred embodiment of the present invention, the limiting circuit includes a diode D1, a MOS transistor MN6, and a MOS transistor MPX. The MOS transistor MN6 is an NMOS type MOS transistor. The MOS transistor MPX is a PMOS type MOS transistor. The anode of the diode D1 is connected to the drain of the MOS transistor MP5 of the operational transconductance amplifier circuit. The cathode of the diode D1 is connected to the drain of the MOS transistor MN6 and the drain of the MOS transistor MPX; the gate of the MOS transistor MPX is connected to the drain, and the source of the MOS transistor MPX is connected to the power supply VDD. The source of the MOS transistor MN6 is grounded to GND. The gate of the MOS transistor MN6 is connected to an external bias voltage V _nbias2 to provide a proper working point bias.

The utility model uses the comparison circuit to output the control signal to control whether the operational transconductance amplifying circuit adopts an open-loop structure or a closed-loop feedback structure; it uses the voltage sampling current summation negative feedback structure to reduce the voltage gain of the operational amplifier while maintaining the output current basically unchanged ;Use diodes in series with NMOS type MOS tube structure to limit the error voltage output range.

The working principle of the utility model is:

The level shifting circuit adopts a common-collector amplifier structure, with base input and emitter output. Among them, Q1 and R1 form a first-stage common-collector amplifier, and Q2 and R2 form a first-stage common-collector amplifier. Taking Q2 and R2 as an example, in order to ensure that Q2 works in the state of the amplification region, the static operating point level of the emitter of Q2 will be 0.7V greater than the base input v _FB of Q2, that is, the output static potential of the amplifier is v _FB +0.7 V. The AC gain of the common-collector amplifier, expressed as

In the formula, β is the common emitter current gain of the bipolar triode, and R _iota is the OTA input resistance. A _v ≈ 1, that is, the output AC signal is the same as the input AC signal. Therefore, through the level shift circuit, the potential of the signal operating point is increased without affecting the AC signal, so that the signal can drive the subsequent OTA circuit.

The core circuit of the utility model is an operational transconductance amplifying circuit with variable adaptive gain. Among them, MP1, MP2, MP3 and MN1, MN2, MN3 form a three-way current mirror, which works in the constant current region and is used to mirror the current, provide bias current, and increase the amplification gain. The reference current I _ref of the current mirror is determined by the parameters of the MN1 tube and bias voltage V _nbias1 control. When the MOS transistor works in the amplification region, the relationship between the drain current and the gate-source voltage can be approximately expressed as

In the formula, ID is the drain current of the _MOS tube, and W/L is the width-to-length ratio of the MOS tube; is the characteristic current, μ _n is the electron mobility of the MOS tube, C _OX =ε _OX /t _OX is the capacitance of the gate oxide layer, ε _OX is the dielectric constant of the oxide, t _OX is the thickness of the oxide layer, and V _GS is the MOS The gate-source voltage of the type MOS tube, V _TH =k _B T/q is the thermal voltage, k _B is the Boltzmann constant, q is the electron charge, and V _TH is the threshold voltage of the MOS type MOS tube.

In the example of the utility model,

In the formula, V _nbias1 is the gate bias voltage of MN1, W/L is the width-to-length ratio of MN1, and I _ref is the reference branch current.

For the mirror branch, the mirror current can be expressed as

In the formula, I _MIR is the mirror current, (W/L) _mir is the mirror branch MOS tube width-to-length ratio, (W/L) _ref is the reference branch MOS type MOS tube width-to-length ratio, I _ref is the reference branch current .

MP1 works in the enlarged region, its gate and drain are shorted, and the drain channel does not work. When MP2 and MP3 also work in the amplification area, the three MOS tubes have limited output resistance, and the mirror current of the mirror current source is controlled by the gate-source voltage, while the three MOS tubes MP1, MP2, and MP3 have limited output resistance. The gate-to-source voltages are the same. In the example of the present utility model, the parameters of MP2 and MP3 are consistent, and the drain terminal current is the same, and the mirror current is expressed as

The OTA described in Figure 1 is a common emitter amplifier with NPN bipolar transistors Q3 and Q6 as differential input transistors and a PMOS mirror current source as a load. When the differential input v _i <0.7V, the input transistor is off, and the load transistor is in the linear region. When v _i increases gradually, the input transistor gradually produces a conduction current and enters the saturation region, and the load transistor gradually transitions from the linear region to the amplification region. When the load is in the working state of the amplification region, a small change in _vi will cause a large change in the operating point current, thereby achieving a large gain. The voltage gain can be expressed as

A _v ＝-g _m (r _o1 //r _o2 )

In the formula, g _m is the transconductance of the input transistor, r _o1 is the equivalent exchange resistance of the input transistor, and r _o2 is the equivalent exchange resistance of the load transistor. The larger the current, the larger the transconductance g _m and the smaller the output resistance. Since the bipolar transistor is used as a differential input transistor, a higher voltage gain can be obtained under a certain current condition. Q4 and Q5 adopt a cross-coupling structure to realize fast switching of the output of the differential amplifier, increase the transconductance g _m , and further increase the voltage gain.

MN4, MN5, and MP5 constitute a mirror current mirror, which completes the function of converting the output voltage of the differential amplifier circuit into an output current. MN4 works in the amplification region, its gate and drain are shorted, and the output voltage of the differential amplifier controls the current flowing through the transistor.

In the utility model example, when MP4 cuts off, OTA belongs to open-loop structure, has

After this current is mirrored,

V _e ＝I _out r _omp5

In the formula, V _e is the output voltage of the error amplifier, r _omp5 is the equivalent output resistance of the MP5 tube.

When MP4 is turned on, the OTA output and the differential input are terminated through the resistor R3, realizing a feedback structure. The feedback structure is voltage sampling parallel negative feedback, when deep negative feedback,

In the formula, A _vf is the voltage gain of the feedback structure, ve is the AC component of the error amplifier output voltage _Ve , and v _fb is the AC component of the input voltage vFB. R _i is the input resistance of the common collector amplifier circuit formed by Q2. The feedback closed-loop gain that meets the requirements can be obtained by designing R3.

The limiter circuit described in Figure 1 is composed of a diode and MN6 connected in series. Select an appropriate gate bias voltage of MN6 to make _MN6 work in the amplification region, and the drain potential is determined. Then the highest potential of ve can be expressed as

V _e =v _DMN6 +0.7

In the formula, v _DMN6 is the drain potential of MN6, and 0.7V is the turn-on voltage of the diode.

What Fig. 2 describes is the comparison circuit of the utility model example, its function is to monitor the large signal fluctuation of the DCDC output voltage, and use the output signal of the comparison circuit to control whether the OTA loop adopts an open-loop structure or a closed-loop structure, thereby controlling different amplifier voltage gains . The comparison circuit is divided into two stages, the first stage is an operational transconductance amplifier circuit, and the second stage is a constant current source load common source amplifier circuit. In the example of the utility model, the out point is the output of the second stage amplifying circuit, which is converted into a standard CMOS logic level through INV2.

The output swing at the out point is expressed as

v _dsMN9 ≤v _out ≤V _DD -|v _dsMP8 |

Where, v _dsMN9 is the drain-source voltage of transistor MN9, and v _dsMP8 is the drain-source voltage of transistor MP8.

When the transistor MP12 is turned off, the voltage gain at the out point is expressed as

A _vout ＝g _mMP10 (r _oMP10 //r _oMN8 )g _mMN9 (r _oMP8 //r _oMN9 )

When the transistor MP12 is turned on, the voltage gain at the out point is expressed as

A _vout ＝(g _mMP10 +g _mMP11 )(r _oMP10 //r _oMN8 )g _mMN9 (r _oMP8 //r _oMN9 )

The output slew rate of the compare circuit is:

The function of the comparison circuit is to monitor the large signal fluctuation of the output voltage of the DCDC chip. The output delay of the comparison circuit is different when the slew rate is different, so that under the same external reference voltage condition, the output delay time of the comparison circuit is different. Small fluctuations in the input signal will not affect the output change, only large signal changes will affect the output change.

A step-down DC-DC power supply management chip is realized based on the error amplifier of the utility model patent and a traditional open-loop error amplifier example. Fig. 3 has described the simulation result of the output voltage ripple fluctuation of the power management chip in the case of a large current load, under the load current condition of 7A, the output voltage ripple of the power management chip based on the error amplifier of the present utility model is effectively reduced .

The utility model relates to the field of integrated circuit design, in particular to an error amplifier of a DC-DC power supply manager. The error amplifier solves the problem of the contradiction between ripple and transient characteristics in the prior art under the condition of large current application , so that the output voltage has good transient characteristics with low ripple. In the utility model, the large signal fluctuation of the output voltage is monitored by using the comparison current, and the gain of the transconductance operational amplifier is changed in real time. When the load current is stable, the gain of the transconductance operational amplifier becomes smaller, thereby reducing the output ripple; when the load current fluctuates, and the comparison circuit detects abnormal fluctuations in the output voltage, the gain of the transconductance operational amplifier becomes larger, and the output voltage is tracked in time state to obtain good transient characteristics. A step-down DC-DC power management chip is implemented based on the error amplifier of the present invention, and the output voltage of the power management chip is simulated and monitored. The comparison of the simulation results shown in FIG. 3 verifies the effectiveness of the technology of the present invention.

Claims (9)

1. A gain-adaptive error amplifier, characterized in that: comprise a level shift circuit, an operational transconductance amplifying circuit and a comparator circuit; Level shifting circuit, the input is connected to external reference voltage V _ref1 and external feedback voltage v _FB ; so that the input level of the operational transconductance amplifier circuit meets the normal working requirements; Operational transconductance amplifier circuit, the input is connected to the external bias voltage V _nbias1 , and the output terminals of the level shift circuit and the comparison circuit; the bipolar transistor is used as the differential pair tube, and the MOS tube common source structure current mirror is used as the differential pair The tube provides current bias to reduce power consumption to ensure greater gain; The comparison circuit, the input is connected to the external reference voltage V _ref2 and the external feedback voltage v _FB , and the bias output terminal V _pbias of the operational transconductance amplifier circuit; the feedback structure is used to control the output slew rate of the comparison circuit, thereby outputting the control of the operational transconductance amplifier circuit Signal; The limiting circuit is connected to the external bias voltage V _nbias2 as input and the output terminal V _e of the operational transconductance amplifier circuit; the output voltage of the operational transconductance amplifier circuit is limited. 2. A gain-adaptive error amplifier according to claim 1, characterized in that: the level shift circuit comprises bipolar transistors Q1-Q2, and resistors R1-R2; The base of the bipolar transistor Q1 is connected to the external reference voltage V _ref1 , the base of the bipolar transistor Q2 is connected to the external feedback voltage v _FB ; the collectors of the bipolar transistors Q1 and Q2 are grounded to GND; the emitters of the bipolar transistors Q1 and Q2 are respectively Connect resistors R1 and R2, and the other ends of resistors R1 and R2 are connected to power supply VDD; the emitter of bipolar transistor Q1 is used as the first output end of the level shift circuit, and connected to the first input end of the operational transconductance amplifier circuit; The emitter of the bipolar transistor Q2 serves as the second output terminal of the level shift circuit, and is connected to the second input terminal of the operational transconductance amplifier circuit. 3. A gain adaptive error amplifier according to claim 2, wherein the bipolar transistors Q1 and Q2 are PNP bipolar transistors. 4. A kind of gain adaptive error amplifier according to claim 1, characterized in that: the operational transconductance amplifier circuit comprises MOS transistors MP1-MP5, MOS transistors MN1-MN5, bipolar transistors Q3-Q6, and resistor R3; The sources of the MOS transistors MN1~MN5 are all connected to the ground GND; the sources of the MOS transistors MP1, MP2, MP3 and MP5 are connected to the power supply VDD; Set the voltage V _nbias1 ; the gates of the MOS transistors MP1, MP2, MP3 and MP5 are connected together, and are used as the bias output terminal V _pbias of the operational transconductance amplifier circuit, and connected to the bias input terminal V _pbias of the comparison circuit; the MOS transistor MN1 The drain of the MOS transistor MP1 is connected to the drain and the grid; the drain of the MOS transistor MN2 is connected to the emitters of the bipolar transistors Q3 and Q5; the drain of the MOS transistor MN3 is connected to the emitters of the bipolar transistors Q4 and Q6; The collectors of bipolar transistors Q3 and Q4 are connected to the drain of MOS transistor MP2; the collectors of bipolar transistors Q5 and Q6 are connected to the drain of MOS transistor MP3; the bases of bipolar transistors Q3 and Q4 are jointly used as an operational transconductance amplifier circuit The first input end of the level shifting circuit is connected to the first output end of the level shifting circuit; the bases of the bipolar transistors Q5 and Q6 are jointly used as the second input end of the operational transconductance amplifier circuit, and are connected to the first output end of the level shifting circuit Two output terminals; the gate and drain of the MOS transistor MN4 are short-circuited, and connected to the gate of the MOS transistor MN5 and the drain of the MOS transistor MP3; the gate of the MOS transistor MP4 is used as the third input of the operational transconductance amplifier circuit terminal, connected to the output terminal of the comparator circuit; the source of the MOS transistor MP4 is connected to the bases of the bipolar transistors Q5 and Q6 and the emitter of Q2 in the level shift circuit; the resistor R3 is connected to the drain of the MOS transistor MP5 and the MOS transistor Between the drains of MP4; the drain of the MOS transistor MP5 is connected to the drain of the MOS transistor MN5, which together serve as the operational transconductance amplifier circuit, that is, the output terminal V _e of the entire amplifier, and are connected to the output terminal of the limiting circuit. 5. A kind of gain self-adaptive error amplifier according to claim 4, it is characterized in that: MOS tubes MP1～MP5 are PMOS type MOS tubes; MOS tubes MN1～MN5 are NMOS type MOS tubes; bipolar transistors Q3～Q6 are NPN type bipolar transistor. 6. A kind of gain self-adaptive error amplifier according to claim 1, is characterized in that: comparison circuit comprises MOS tube MN7～MN9, MOS tube MP7～MP12, inverter INV1 and INV2; The gate of MOS transistor MP9 is connected to external reference voltage V _ref2 ; the gates of MOS transistors MP10 and MP11 are connected to external feedback voltage v _FB ; the sources of MOS transistors MP9 , MP10 and MP11 are connected to the drain of MP7 of MOS transistor; The gates of MP7 and MP8 are connected together as the bias input terminal V _pbias of the comparison circuit, and connected to the bias output terminal V _pbias of the operational transconductance amplifier circuit; the sources of the MOS transistors MP7 and MP8 are connected to the power supply VDD; the MOS transistors The source and drain of MN7 are short-circuited and connected to the gate of MOS transistor MN8 and the drain of MOS transistor MP9; the drains of MOS transistors MN8, MP10 and MP12 are connected and connected to the gate of MOS transistor MN9 The drain of the MOS transistor MP11 is connected to the source of the MOS transistor MP12; the sources of the MOS transistors MN7, MN8 and MN9 are grounded to GND; the drains of the MOS transistors MN9 and MP8 are connected and connected to the inverters INV1 and INV2 The input terminal of the MOS transistor MP12 is connected to the output terminal of the inverter INV1; the output terminal of the inverter INV2 is used as the output terminal of the comparison circuit, and is connected to the third input terminal of the operational transconductance amplifier circuit. 7. A kind of gain self-adaptive error amplifier according to claim 6, it is characterized in that: MOS tubes MN7～MN9 are NMOS type MOS tubes; MOS tubes MP7～MP12 are PMOS type MOS tubes; Inverters INV1 and INV2 are CMOS inverter. 8. A kind of gain self-adaptive error amplifier according to claim 1, is characterized in that: limiter circuit comprises diode D1, MOS transistor MN6, and MOS transistor MPX; The anode of the diode D1 is used as the output end of the limiter circuit, and is connected with the output end V _e of the operational transconductance amplifier circuit; the cathode of the diode D1 is connected with the drain of the MOS transistor MN6 and the drain of the MOS transistor MPX; the MOS transistor MPX The gate of the MOS transistor MPX is connected to the drain, the source of the MOS transistor MPX is connected to the power supply VDD; the source of the MOS transistor MN6 is grounded to GND; the gate of the MOS transistor MN6 is connected to the external bias voltage V _nbias2 . 9. The gain adaptive error amplifier according to claim 8, wherein the MOS transistor MN6 is an NMOS MOS transistor, and the MOS transistor MPX is a PMOS MOS transistor.