CN205693679U - Terminal test system - Google Patents

Abstract

The utility model provides a terminal testing system. The terminal testing system includes: a base station simulator, a full anechoic chamber, a DSP chip and an FPGA chip; a plurality of probes are evenly arranged in the full anechoic chamber, which are wirelessly connected to the antennas of the terminal under test respectively. Connection; the base station simulator outputs base station signals to multiple probes in the full anechoic chamber; the multiple probes are used to receive the base station signals output by the base station simulator and send out downlink signals respectively, and are also used to receive feedback from the terminal under test according to the downlink signal the uplink signal; the DSP chip is used to obtain the power of the uplink signal received by the plurality of probes, and output a control signal for controlling switches of a preset number of probes among the plurality of probes according to the magnitude of the power, The preset number of probes sends test signals to the terminal under test in the anechoic chamber to test the terminal under test; the FPGA chip is used to control the switches of the corresponding probes in the anechoic chamber according to the control signal.

Description

Terminal Test System

technical field

The utility model relates to the field of radio frequency technology, in particular to a terminal testing system.

Background technique

At present, when conducting performance tests such as protocol conformance testing and throughput on terminals, the conduction method is generally used for testing. The test system consists of several parts such as a wireless broadband comprehensive tester, a multi-antenna multiplexing unit, and a channel simulator. Through The way of conductive connection is to test the performance of the terminal in the simulated environment. The conformance test of the test terminal in the conduction mode cannot reflect the situation of the terminal in actual application, and for the terminal using the integrated array antenna, the conduction test system cannot be realized.

Utility model content

In order to solve the above technical problems, the utility model provides a terminal test system, the terminal test system includes: a base station simulator, a full anechoic chamber, a DSP chip and an FPGA chip; a plurality of probes are uniformly arranged in the anechoic chamber , respectively wirelessly connected to the antenna of the terminal under test;

The base station simulator is used to output base station signals to the plurality of probes in the fully anechoic chamber;

The plurality of probes are used to receive base station signals output by the base station simulator and send downlink signals respectively, and are also used to receive uplink signals fed back by the terminal under test according to the downlink signals;

The DSP chip is used to obtain the power of the uplink signal received by the multiple probes, and output a control signal for controlling switches of a preset number of probes among the multiple probes according to the magnitude of the power, the preset A set number of probes send test signals to the terminal under test in the fully anechoic chamber to test the terminal under test;

The FPGA chip is used to control the switches of the corresponding probes in the anechoic chamber according to the control signal.

In an embodiment, the terminal testing system further includes: a PA chip, configured to amplify the power of the downlink signal sent by the probe or the power of the test signal.

In an embodiment, the terminal under test includes: a single-antenna terminal, a multi-antenna terminal, and a terminal with an integrated antenna array.

Utilizing the utility model, not only the antenna test can be performed on the single-antenna terminal and the multi-antenna terminal, but also the antenna test can be performed on the antenna array integrated terminal. Moreover, the utility model can be used to carry out spatial tests on the protocol consistency and throughput and other performances of the terminals of the above-mentioned various antenna types, so that the performance of the terminals in actual application can be truly tested.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are only some embodiments of the utility model, and those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is a schematic structural diagram of a terminal testing system according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a DSP chip 3 according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. example. Based on the embodiments of the present utility model, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of the present utility model.

FIG. 1 is a schematic structural diagram of a terminal testing system according to an embodiment of the present invention. As shown in FIG. 1 , the terminal test system includes: a base station simulator 1 , an anechoic chamber 2 , a DSP chip 3 and an FPGA chip 4 . A plurality of probes 5 are evenly arranged in the anechoic chamber 2, and when testing a terminal, these probes 5 can be respectively connected to the antenna of the terminal under test in a wireless manner.

The base station simulator 1 is used to output base station signals to multiple probes 5 in the fully anechoic chamber 2 .

The multiple probes 5 in the anechoic chamber 2 are used to receive the base station signal output by the base station simulator 1, respectively send downlink signals to the terminal under test according to the base station signal, and receive the uplink signal fed back by the terminal under test according to the downlink signal.

The DSP chip 3 is used to obtain the power of the uplink signal received by the plurality of probes 5, and output a control signal for controlling the switches of the preset number of probes in the plurality of probes according to the power of the uplink signal received by each probe. A preset number of probes send test signals to the terminal under test in the fully anechoic chamber 2 to test the terminal under test.

The FPGA chip 4 is used to control the switches of the corresponding probes in the anechoic chamber 2 according to the control signal generated by the DSP chip 3, that is, to turn on the selected preset number of probes and to turn off the unselected probes.

Utilizing the utility model, not only the antenna test can be performed on the single-antenna terminal and the multi-antenna terminal, but also the antenna test can be performed on the antenna array integrated terminal. Moreover, the utility model can be used to carry out spatial tests on the protocol consistency and throughput and other performances of the terminals of the above-mentioned various antenna types, so that the performance of the terminals in actual application can be truly tested.

Usually, in order to increase the power sent by the probe in the full anechoic chamber 2, the above-mentioned terminal test system also includes a PA (Power Amplifier, power amplifier) chip, which performs a power analysis on the power of the downlink signal sent by the probe 5 or the power of the test signal. enlarge.

When using the above-mentioned terminal testing system to test a terminal, the terminal to be tested needs to be placed in the full anechoic chamber 2, and the terminal to be tested can be a single-antenna terminal, a multi-antenna terminal, or an integrated antenna array terminal.

The DSP chip 3 generally includes a sorting module 31 , a probe selection module 32 and a signal output module 33 , as shown in FIG. 2 . After the probe 5 in the anechoic chamber 2 sends a downlink signal to the terminal under test, since the terminal under test is equipped with an antenna, the antenna will correspondingly feed back an uplink signal according to the downlink signal. After the probe receives the uplink signal fed back by the terminal under test, the sorting module 31 in the DSP chip 3 sorts the above-mentioned multiple probes according to the power of the received uplink signal from large to small; the probe selection module 32 sorts the above-mentioned multiple probes Select a preset number of probes with higher power; the signal output module 33 generates a control signal based on the selected probes and sends it to the FPGA chip 4 . For example, the sorting module 31 is sorted according to the power of the uplink signal received by the probes in descending order, and the probe selection module 32 selects the first 25% of the probes with higher power as the probes used for sending the test signal, wherein 25% This numerical value is an example and is not used to limit the present invention.

When the FPGA chip 4 receives the control signal generated by the DSP chip 3, it controls the switches of the corresponding probes in the anechoic chamber 2 according to the control signal, that is, the selected probes are turned on and the unselected probes are turned off. These selected probes send test signals to the terminal under test in the fully anechoic chamber 2 to test the terminal under test.

In the embodiment of the present utility model, the probe in the anechoic chamber 2 is wirelessly connected to the terminal under test. Therefore, the above-mentioned test can not only test the radio frequency performance of the antenna of the terminal under test, but also test the radio frequency performance of the terminal under test. The protocol consistency and performance of the terminal are tested. When the terminal test system is used to replace the existing conductive wire connection mode to test the protocol consistency and throughput performance of the terminal, the performance of the terminal in actual application can be tested more realistically.

Moreover, in the actual test, not all the probes in the full anechoic chamber 2 are used to send test signals, but some probes are selected to test the terminal under test, which greatly saves energy.

In the utility model, specific examples have been applied to explain the principle and implementation of the utility model, and the explanations of the above examples are only used to help understand the method of the utility model and its core idea; meanwhile, for those of ordinary skill in the art According to the idea of the present utility model, there will be changes in the specific implementation and scope of application. In summary, the content of this specification should not be construed as a limitation of the present utility model.

Claims (3)

1. A terminal test system, characterized in that, the terminal test system comprises: a base station simulator, a full anechoic chamber, a DSP chip and an FPGA chip; a plurality of probes are evenly arranged in the described full anechoic chamber, respectively connected to the tested The antenna wireless connection of the terminal; The base station simulator is used to output base station signals to the plurality of probes in the fully anechoic chamber; The plurality of probes are used to receive base station signals output by the base station simulator and send downlink signals respectively, and are also used to receive uplink signals fed back by the terminal under test according to the downlink signals; The DSP chip is used to obtain the power of the uplink signal received by the multiple probes, and output a control signal for controlling switches of a preset number of probes among the multiple probes according to the magnitude of the power, the preset A set number of probes send test signals to the terminal under test in the fully anechoic chamber to test the terminal under test; The FPGA chip is used to control the switches of the corresponding probes in the anechoic chamber according to the control signal. 2 . The terminal testing system according to claim 1 , further comprising: a PA chip, configured to amplify the power of the downlink signal sent by the probe or the power of the test signal. 3 . 3 . The terminal testing system according to claim 1 , wherein the tested terminal comprises: a single-antenna terminal, a multi-antenna terminal, and an antenna array integrated terminal. 4 .