CN200947341Y - Display controller for generating multiple shaded images - Google Patents

Abstract

A display controller generates an image with multiple light and shade levels on a display device composed of a plurality of binary state pixels in an array manner through a plurality of continuous frames. The display controller includes an image memory for providing a gradation data for each pixel. A waveform pattern selector outputs a waveform pattern selection signal to make a waveform pattern memory provide two groups of different waveform pattern signals for any two adjacent sub-pixel groups respectively. The frame rate of the plurality of consecutive frames is set high enough to avoid visual interference.

Description

Display controller for generating multiple shaded images

technical field

The utility model relates to a display controller, in particular to a display controller capable of generating multi-gradation (Multi-Gradation) images on a display device composed of binary state pixels.

current technology

A digitally controlled display device usually refers to an optoelectronic device composed of multiple pixels (Pixel) as the basic light source unit, in which each pixel is controlled by a digital electronic signal to be in a binary state ON and OFF (or bright and dark). ) to switch between. A pixel as a basic light source unit may be emissive, transmissive, or reflective. Examples of such digitally controlled display devices are liquid crystal display devices, light emitting diode display devices, or plasma display devices, and the like.

Since the pixels can only exhibit one of the binary states ON and OFF, if multiple light and dark gradation images are to be generated on a display device composed of binary state pixels (hereinafter referred to as a binary display device), it is necessary to use or develop a special display technology. For example, the analog modulation technology provides a plurality of driving voltages with different intermediate levels to the pixels of the binary display device, making them in an incomplete ON/OFF state, thereby achieving multiple light and dark levels of display. The disadvantage of this analog modulation technique is the need for complex drivers.

Another existing technology is the pulse width modulation technology, which controls the duty cycle (Duty Cycle) between the binary state ON and OFF of the pixel and utilizes the low-pass filtering effect of the human eye, thereby achieving the perception of multiple light and dark levels. The disadvantage of this pulse width modulation technique is that it requires complex drivers and complex control algorithms.

Another existing technology is the frame rate modulation technology, the principle of which is similar to that of the pulse width modulation technology, the difference lies in that multiple light and dark levels are perceived through the continuous display of multiple frames. A disadvantage of this frame rate modulation technique is that there is often perceived flicker in the displayed image.

Yet another prior art is a dithering technology, which utilizes a dithering matrix to eliminate flicker in a displayed image. However, this dithering technique requires complex control algorithms and circuits and causes stripes or sacrifices information capacity.

Contents of the invention

In view of the aforementioned problems, the purpose of the present invention is to provide a display controller capable of generating images with multiple light and dark levels on a display device composed of binary state pixels.

Through a plurality of consecutive frames, a display controller generates an image with multiple light and dark levels on a display device composed of a plurality of binary state pixels in an array. The plurality of pixels are divided into a plurality of sub-pixel groups having the same size. The display controller includes an image memory that provides a shading data for each pixel. The shading data is used to indicate the shading level to be generated on a desired pixel. A waveform pattern memory provides multiple sets of waveform pattern signals to the display device. Each of the plurality of sets of waveform pattern signals has the same number of waveform pattern signals. Each waveform pattern signal has a predetermined number of bits and produces a different light and dark gradation level when applied to a pixel. Each bit is displayed in a corresponding frame of the plurality of consecutive frames. A waveform pattern selector outputs a waveform pattern selection signal, so that the waveform pattern memory provides two sets of different waveform pattern signals for two adjacent sub-pixel groups respectively. The different two groups of waveform pattern signals are set so that the two adjacent sub-pixel groups are in different states from each other in at least one frame of the plurality of consecutive frames. The waveform pattern memory determines to provide a selected group of the plurality of groups of waveform pattern signals in response to the waveform pattern selection signal, and determines to provide a selected group of the selected group of waveform pattern signals in response to the light and dark level data , and sequentially provide the corresponding bits of the selected waveform pattern signal according to the progress of the plurality of consecutive frames. The frame rate of the plurality of consecutive frames is set high enough to avoid visual interference.

Preferably, the frame rate is greater than or equal to (2 ⁿ ×15) Hz.

Preferably, the waveform pattern memory provides two sets of waveform pattern signals to the display device. The waveform pattern selector outputs the waveform pattern selection signal in response to a least significant bit of the row number and a least significant bit of the column number. The waveform pattern memory stores one of the two sets of waveform pattern signals, and uses the waveform pattern selection signal to generate another set of waveform pattern signals from the set.

Preferably, the display device is a color display device.

Description of drawings

FIG. 1 shows a schematic diagram of a binary display device composed of a binary state pixel array.

Fig. 2 shows a schematic diagram of generating an image with 2 ⁿ levels of light and dark levels through 2 ⁿ frames on a binary display device.

FIG. 3( a ) is a schematic diagram showing that each pixel in a binary display device alternately receives two sets of different waveform pattern signals vertically and horizontally.

FIG. 3( b ) shows a schematic diagram of several possible spatial patterns of any 2×2 pixel array in one frame in a binary display device.

4(a) and 4(b) show a timing diagram of an example of two sets of waveform pattern signals provided by the display controller according to the present invention.

5(a) and 5(b) show circuit block diagrams of the display controller according to the present invention.

6(a) to 6(c) show schematic diagrams of a color display device applying the present invention.

Detailed ways

As mentioned above, there are various shortcomings in the prior art for generating images with multiple light and dark levels on a binary display device. However, the display controller according to the present invention provides the following advantages in addition to effectively producing multiple light and dark gradation images on the binary display device: (1) simple circuit configuration, (2) easy-to-implement control algorithm, (3) Avoidance of visual disturbances such as flicker or stripes, (4) Full utilization of information volume, and (5) Improvement of processing speed of digital image signals. Therefore, according to the display controller of the present invention, the binary display device is controlled by an easy-to-implement control algorithm to achieve uniform and streak-free multiple light and shade levels without loss of information, and directly avoid flicker phenomenon.

The following description and accompanying drawings will make the aforementioned and other objects, features and advantages of the present invention more apparent. Here, the preferred embodiments according to the present utility model will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1 , a binary display device 10 is composed of 240×160 binary state pixels arranged in an array with 240 rows and 160 columns. Please note that although the size of the binary display device 10 shown in FIG. 1 is 240×160, the present invention is not limited to this example, but can be applied to a binary display device with any size. In order to generate images with multiple light and dark levels on the binary display device 10, an image with multiple light and dark levels can be divided into multiple frames (Frames) displayed at equal intervals in time, wherein each frame can be displayed according to a specific The spatial pattern of the binary display device is realized by respectively setting a plurality of pixels in one of the binary states ON/OFF. As a result, under the effect of temporal/spatial integration of human vision, images with multiple light and dark levels can be effectively perceived from the binary display device.

Assume that the binary display device 10 is operated to display a series of images with 2 ⁿ order light and dark levels (n is a positive integer). As shown in Fig. 2, each ^2n- order light and dark layer image is composed of ²ⁿ frames, and a fixed frame period is separated between adjacent frames. The first frame of the next ^{2n order} light and dark level image is displayed after the fixed frame period after the display of the 2nth frame of the previous 2 ⁿ level light and dark level image. In other words, the binary display device 10 is operated to display frames at a fixed frame rate, wherein every combination of 2 ⁿ frames can make human eyes perceive an image with 2 ⁿ levels of light and dark levels. Specifically, in order to take advantage of the temporal integration effect of human vision, the frame rate must have a rather large value. In principle, the higher the frame rate is, the more beneficial it is to utilize the temporal integration effect of human vision, thereby generating high-quality images with multiple levels of light and shade. The frame rate adopted in the prior art is about 50 to 120 Hz, and when n≤2, it may still be able to display a good 2 ⁿ -order light and dark level image without causing flicker. However, when n≥3, the prior art must use complex control algorithms or dithering matrices to compensate for the low frame rate, otherwise flickering cannot be avoided.

In a preferred embodiment according to the present invention, the frame rate is set to be greater than or equal to (2 ⁿ ×15) Hz. Under this condition, since each ²ⁿ -order light-and-dark layer image has ²ⁿ frames, the display rate of any two frames with the same frame number in two adjacent ^2n- order light-dark layer images is greater than or equal to 15Hz ( That is, it occurs once every 2 ⁿ frame periods). In other embodiments according to the present invention, the preferred frame rate can also be determined through computer simulation or actual test, as long as the frame rate is high enough to avoid the flicker phenomenon perceived by human eyes.

In order to take advantage of the spatial integration effect of human vision, the display controller according to the present invention provides two sets of different waveform pattern signals to each pixel of the binary display device 10 in a manner of alternating vertically and horizontally. Specifically, as shown in FIG. 3(a), a basic 2×2 pixel unit 30 includes four pixels, wherein two pixels located on a diagonal line are used to receive the first group of waveform pattern signals WP1 and located at The two pixels on the other diagonal are used to receive the second wave pattern signal WP2. In the present invention, the second group of waveform pattern signals WP2 is designed to be different from the first group of waveform pattern signals WP1, which will be described in detail later. Referring back to FIG. 1 , the binary display device 10 can be regarded as composed of a plurality of basic 2×2 pixel units 30 as shown in FIG. 3( a ). As a result, the pixels marked with I represent the pixels for receiving the first wave pattern signal WP1, and the blank pixels without marks represent the pixels for receiving the second wave pattern signal WP2. Therefore, two adjacent pixels on the binary display device 10, whether they are vertically adjacent or horizontally adjacent, receive two different sets of waveform pattern signals WP1 and WP2.

FIG. 3( b ) shows a schematic diagram of several possible spatial patterns A to H in one frame of any 2×2 pixel array in the binary display device 10 . In Figure 3(b), the pixels marked with hollow circles represent the ON state (or bright state) in the binary state, while the pixels marked with solid circles represent the OFF state in the binary state. state (or dark state). In the present invention, two different groups of waveform pattern signals WP1 and WP2 respectively provided to two adjacent pixels of the binary display device 10 are set so that the two adjacent pixels can be divided into two groups in 2 ⁿ frames are in different operating states from each other in at least one frame, such as spatial pattern A or B in Fig. 3(b). In other words, the operation states of two adjacent pixels are spatially interleaved. As a result, the switching rate of pixels with a binary state perceivable under the spatial integration of human vision is doubled. In this way, in the aforementioned preferred embodiment where the frame rate is set to be greater than or equal to (2 ⁿ × 15) Hz, even if there is a pixel in the binary display device 10 that switches only once in 2 ⁿ frames, human The switching rate perceived by the eye is still greater than or equal to 30 Hz. Therefore, the display controller according to the present invention can more reliably avoid flickering and stripes.

4(a) and 4(b) show a timing diagram of an example of two sets of waveform pattern signals WP1 and WP2 provided by the display controller according to the present invention. The two sets of waveform pattern signals WP1 and WP2 provided in FIGS. 4( a ) and 4 ( b ) are extended for 32 frames, so they can be used to display images with 2 ⁵ (=32) levels of light and dark levels. In FIGS. 4(a) and 4(b), the m-th order waveform pattern signal is designed to have pulses in m frames out of 32 frames and not have pulses in the remaining (32-m) frames. As far as the corresponding m-th order waveform pattern signal is concerned, although the first and second sets of waveform pattern signals WP1 and WP2 both have m pulses respectively, the difference between them lies in the distribution of the pulses in the entire 32 frame period . As mentioned above, the waveform pattern signals WP1 and WP2 are set such that two adjacent pixels are in different operating states from each other in at least one frame of 2 ⁿ frames. With the design of different pulse distributions, the time/space integration effect of human vision can be utilized to achieve the perception effect of doubling the pixel switching rate. Each of the waveform pattern signals WP1 and WP2 shown in FIGS. 4(a) and 4(b) may also be considered as or implemented by a digital bit sequence. For example, the 22nd level signal of the first group of waveform pattern signals is [11111001111001111100111100111100], wherein bit 1 represents pulse and bit 0 represents no pulse. Each bit is displayed in a corresponding frame of the plurality of consecutive frames. Since each bit has a binary state, it is well suited for controlling the operation of binary state pixels.

Please note that only the 16th to 32nd order signals in the first and second groups of waveform pattern signals WP1 and WP2 are shown in FIGS. 4(a) and 4(b), because the 1st to 15th order signals are The order signals are designed as complements or inversion signals of the 31st to 17th order signals, so their illustrations are omitted. In another embodiment according to the present invention, the first-order signal can also be designed to have no pulse in all 32 frame periods.

Although the two groups of waveform pattern signals WP1 and WP2 shown in Figures 4(a) and 4(b) are used to display images with 32 levels of light and shade levels in the foregoing embodiment, the utility model is not limited to this example and can be applied from two Corresponding 16 waveform pattern signals are selected from each group of the waveform pattern signals WP1 and WP2 to display 16-level light and dark level images. Similarly, the present invention can also be applied to select 8 corresponding waveform pattern signals from each of the two groups of waveform pattern signals WP1 and WP2 to display 8-level light and dark layered images.

Here, the circuit configuration and operation of the display controller 51 according to the present invention for generating images with multiple light and dark levels on the display device 50 will be described with reference to FIGS. 5( a ) and 5 ( b ). Referring to FIG. 5( a ), the display controller 51 of the present invention includes a pixel counter 53 , a scan line counter 54 , an image memory 52 , a waveform pattern selector 57 and a waveform pattern memory 56 . Wherein the output end of pixel counter 53 and scan line counter 54 is all connected to the input end of image memory 52 and wave pattern selector 57; The output end of wave pattern selector 57 and image memory 52 is all connected to the input end of wave pattern memory 56 ; The output terminal of the waveform pattern memory 56 is connected to the input terminal of the display device 50 . The image memory 52 stores light and dark level data, and the light and dark level data indicates the light and dark level of each pixel in the binary pixel array constituting the display device 50 . The image memory 52 determines the address to be accessed by the row number signal CN output by the pixel counter 53 and the column number signal RN output by the scan line counter 54 . The pixel counter 53 and the scan line counter 54 respectively use the pixel clock PCK and the scan line clock SLCK as clock signals. In response to the row number signal CN and the column number signal RN, the image memory 52 outputs the shading data GD to be displayed on the pixel addressed by the row number signal CN and the column number signal RN. Although the shading data GD can be directly input into the waveform pattern memory 56, in a preferred embodiment of the present invention, the shading data GD is input into the waveform pattern memory 56 via a look-up table (Look Up Table) 55. The functions of the lookup table 55 usually include increasing the number of bits of the shading data GD, performing gamma correction on the shading data GD, or other similar calculations, so as to enhance the quality of the image to be displayed. The converted gradation data GD' is input from the look-up table 55 to the waveform pattern memory 56. The waveform pattern memory 56 stores a predetermined number of digital bit sequences corresponding to the waveform pattern signal according to the present invention, such as the waveform pattern signal shown in FIGS. 4( a ) and 4 ( b ).

On the other hand, the waveform pattern selector 57 is based on the received row number signal CN and column number signal RN used to determine the pixel address, according to the waveform pattern signal distribution method shown in Figure 3 (a) of the present utility model and outputs The waveform pattern selection signal WS is sent to the waveform pattern memory 56 for determining whether to use the first group or the second group of waveform pattern signals. Meanwhile, the frame counter 58 outputs the frame number signal FN to the waveform pattern memory 56 under the operation of the frame clock FCK. In response to the converted light and dark level data GD', the waveform pattern selection signal WS, and the frame number signal FN, the waveform pattern memory 56 sequentially outputs the waveform pattern signal bit WPB to the binary display device 50 one bit at a time, thereby generating multiple Light and dark layered image. In one embodiment, the waveform pattern memory 56 may store two sets of waveform pattern signals, and determine which set of waveform pattern signals to use based on the waveform pattern selection signal WS. In another embodiment, the waveform pattern memory 56 can only store a single set of waveform pattern signals, and it is determined based on the waveform pattern selection signal WS to directly use the set of waveform pattern signals or derive another set of waveform patterns from the set of waveform pattern signals. Signal. For example, another set of waveform pattern signals can be derived from the stored set of waveform pattern signals by using a phase offset. In a broad sense, in the display controller according to the present invention, the waveform pattern memory 56 can compress or simplify the information to be stored through various reasonable techniques or algorithms, as long as it can be effectively based on the converted light and dark level data GD', It is only necessary to correctly output the desired waveform pattern signal bit WPB for the waveform pattern selection signal WS and the frame number signal FN.

FIG. 5( b ) shows a partial circuit diagram of FIG. 5( a ) to illustrate an example of the waveform pattern selector 57 according to the present invention. With reference to Fig. 5 (b), because only use two groups of wave pattern signals in the utility model and carry out wave pattern signal space distribution according to basic 2 * 2 pixel units shown in Fig. 3 (a), so wave pattern selector 57 It can be implemented quite simply by only an Exclusive-OR logic circuit. Specifically, the exclusive-OR logic circuit receives the least significant bit CNLSB of the row number signal CN output from the pixel counter 53 and the least significant bit RNLSB of the column number signal RN output from the scan line counter 54 . Referring to the truth table of mutual exclusion or logic operation, it can be seen that when the two input logic values are the same, the output logic value is 0, and when the two input logic values are different, the output logic value is 1. Therefore, the mutually exclusive OR logic circuit can effectively distinguish two pairs of pixels respectively located on two diagonal lines in the basic 2×2 pixel unit shown in FIG. 3( a ).

In summary, the display controller according to the present invention can generate an image with 2 ⁿ light and dark levels on a binary display device by only using two sets of waveform pattern signals. The display controller according to the present invention can greatly reduce the waveform pattern The memory capacity of the memory 56 and the waveform pattern selector 57 with a simple structure are used to replace the spatial distribution pattern memory or the dithering matrix buffer in the prior art, thereby greatly improving the processing speed of the digital image signal.

Here, an example in which the display controller according to the present invention is applied to a color display device 60 will be described with reference to FIGS. 6( a ) to 6 ( c ). Referring to FIG. 6(a), the color display device 60 is formed by an array of a plurality of pixels, wherein each pixel is used to display red (R), green (G), and blue (B) among the three primary colors. Isshiki. In the color display device 60, typically, a red pixel (such as R ₁₁ ), a green pixel (such as G ₁₁ ), and a blue pixel (such as B ₁₁ ) are arranged together to form a color pixel group 61, which is used to combine the desired color. Although FIG. 6(a) only shows a three-primary-color pixel arrangement of a color display device, the present invention is not limited to this example and can be applied to color display devices composed of various three-primary-color pixel color arrangements.

FIG. 6( b ) shows a first way for the display controller to distribute two sets of waveform pattern signals to the color display device 60 according to the present invention. In the first manner, each pixel of the color display device 60 is regarded as the minimum allocation unit, regardless of its color. Therefore, the pixels of the color display device 60 are divided according to the basic 2×2 pixel unit 30 in FIG. 3( a ), so as to alternately receive two sets of waveform pattern signals WP1 and WP2 vertically and horizontally.

FIG. 6( c ) shows a second way for the display controller to distribute two sets of waveform pattern signals to the color display device 60 according to the present invention. In the second mode, the color pixel group 61 composed of red pixels, green pixels, and blue pixels of the color display device 60 is regarded as the minimum allocation unit. If four pixels in the basic 2×2 pixel unit 30 of FIG. The x2 pixel unit 30 determines which set of waveform pattern signals each pixel of the color display device 60 should receive. In this case, the color pixel groups 61 of the color display device 60 alternately receive two sets of waveform pattern signals WP1 and WP2 vertically and horizontally.

Although the present invention has been described by means of preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and similar arrangements apparent to those skilled in the art. Accordingly, the scope of the claims should be accorded the broadest interpretation to embrace all such modifications and similar arrangements.

Claims (5)

1. display controller, has the image of the multiple shade of grey on a display device of being formed with array way by a plurality of binary condition pixels in order to produce a width of cloth via a plurality of successive frames, these a plurality of pixels are distinguished into a plurality of sub-pixel groups with same size, and this display controller comprises:

One pixel counter is in order to specify the line number order of a pixel of expecting;

The one scan thread count is in order to the column number of the pixel of specifying this expectation;

One video memory provides a shade of grey data in response to this line number order of the pixel of this expectation and this column number, and these shade of grey data will result from the shade of grey color range on the pixel of this expectation in order to indication;

One waveform patterns storer, in order to provide many group waveform patterns signals to this display device, each group in these many group waveform patterns signals have the waveform patterns signal of similar number, wherein each waveform patterns signal has the position of a predetermined number and produce a different shade of grey color range when being applied to a pixel, and wherein each is to be used in the frame of the correspondence in these a plurality of successive frames to show; And

One waveform patterns selector switch, export a waveform patterns and select signal in response to this line number order of the pixel of this expectation and this column number, make this waveform patterns storer provide in these many group waveform patterns signals two groups inequality respectively for two adjacent sub-pixel groups, wherein:

This waveform patterns memory response is selected signal and is determined to provide one in these many group waveform patterns signals to select group in waveform patterns, determine to provide one in this selected group waveform patterns signal to select the waveform patterns signal in response to these shade of grey data, and the position of the correspondence of this selected waveform patterns signal is provided in regular turn according to the carrying out of these a plurality of successive frames;

Provide respectively to these two adjacent sub-pixel groups should many group waveform patterns signals in these inequality two groups be configured to make these two adjacent sub-pixel groups at least one frame of these a plurality of successive frames, to be in the state that differs from one another; And

The frame rate of these a plurality of successive frames is configured to enough high to avoid vision to disturb.

2. display controller as claimed in claim 1, wherein:

This frame rate is more than or equal to (2 ⁿ* 15) Hz.

3. as the display controller of claim 1, wherein:

It is that a binary is selected signal that this waveform patterns is selected signal.

4. display controller as claimed in claim 1, wherein:

This waveform patterns selector switch is an exor circuit.

5. display controller as claimed in claim 1, wherein:

This display device is a colour display device.

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