CN1301556C - CMOS component and its manufacturing method - Google Patents

Abstract

The invention provides a CMOS component and a manufacturing method thereof, and the structure thereof comprises a gate electrode arranged on a substrate, a source/drain electrode arranged in the substrate at two sides of the gate electrode, stress buffer liners arranged at two sides of the gate electrode in a compliance manner and partially extending to the substrate surface, and stress layers arranged on the gate electrode, the stress buffer liners and the source/drain electrode and contacting with the stress buffer liners, thereby improving the stress of a channel region in the substrate below the gate electrode.

Description

CMOS component and its manufacturing method

technical field

The present invention relates to a CMOS component and a manufacturing method thereof, in particular to a method and a structure thereof for increasing performance of a CMOS component by using local mechanical-stress control (LMC for short).

Background technique

In current semiconductor devices, silicon bulk (Sibulk) is used as the substrate, and the purpose of high-speed operation and low power consumption is achieved by reducing the size of the device. However, the current reduction in component size is approaching physical limits and cost limits. Therefore, it is necessary to develop other technologies other than the downsizing method to achieve high-speed operation and low power consumption.

Therefore, it has been proposed to use stress control in the channel region of the transistor to overcome the limit of device miniaturization. The method is to increase the mobility of electrons and holes by using stress to change the silicon lattice spacing.

A common method is to use a tensile-strained Si layer placed on a Si-Ge layer (under tensile stress) as the channel layer of an NMOS transistor, and a compressive-strained Si-germanium layer (compressive- strained Si-Ge layer) (under compressive stress) as the channel layer of the PMOS transistor. By using the tensile tension silicon layer and the compression tension Si-Ge layer as the channel layer of the MOS transistor, the mobility of surface electrons and holes will be increased, while achieving the purpose of high-speed operation and low energy consumption.

However, there are some problems with this technology. When forming a tensile Si layer (n-channel layer) and a compressive Si-Ge layer (p-channel layer) at the same time as the CMOS channel layer, the process will become very complicated. Moreover, it is quite difficult to selectively form the NMOS channel layer and the PMOS channel layer. Moreover, when the Si-Ge layer is formed by high-temperature heat treatment, dislocation or Ge segregation may occur, thereby deteriorating the gate breakdown voltage characteristic.

In addition, recent studies have used the silicon nitride layer used as the etch stop layer of the contact window to generate stress to affect the stimulant current of the transistor. This technology is called local mechanical stress control. By increasing the applied compressive stress, the mobility of the PMOS transistor can be improved; by reducing the applied compressive stress, the mobility of the NMOS transistor can be improved.

Although the above-mentioned method of using the silicon nitride layer to generate stress to improve the performance of the transistor is simpler than the method of using the Si-Ge buffer layer, its improvement effect is limited.

Contents of the invention

In view of this, the object of the present invention is to provide a CMOS component structure and its manufacturing method, which can further improve the performance of transistors by utilizing the technology of local mechanical stress control.

According to the purpose of the present invention, a CMOS component is provided, the structure of which includes setting the gate electrode on the base, setting the source/drain in the base on both sides of the gate electrode, and placing the stress buffer liner in a conformable manner. It is arranged on both sides of the gate electrode and partly extends to the surface of the substrate, and the stress layer is arranged on the gate electrode, the stress buffer liner and the source/drain, and is in contact with the stress buffer liner, so as to improve the underside of the gate electrode Stress in the channel region in the substrate.

Specifically, the CMOS assembly provided by the present invention has a structure comprising:

a base;

a gate electrode, disposed on the substrate;

a source/drain disposed in the substrate on both sides of the gate electrode;

a stress buffer liner conformably disposed on both sides of the gate electrode and partially extending to the surface of the substrate; and

a stress layer, disposed on the gate electrode, the stress buffer liner and the source/drain, and in contact with the stress buffer liner, so as to increase the stress of a channel region in the substrate below the gate electrode .

Wherein, if the above-mentioned stress layer has tensile stress, the transistors formed by the gate electrode and the source/drain covered under the stress layer are PMOS transistors and NMOS transistors. If the above-mentioned stress layer has compressive stress, the transistor covered by the gate electrode and the source/drain under the stress layer is a PMOS transistor.

In addition, the present invention also provides another CMOS component, the structure of which includes setting the gate electrode on the substrate provided with at least one isolation component, the shallow trench isolation component includes a first stress layer, and the source/ The drain is arranged in the substrate on both sides of the gate electrode and contacts the above isolation components, the stress buffer liner is conformably arranged on both sides of the gate electrode and partially extends to the surface of the substrate, and the second stress layer is arranged on the gate electrode On the electrode, the stress buffer liner and the source/drain, and in contact with the stress buffer liner, the stress of the channel region in the substrate under the gate electrode is increased by the first stress layer and the second stress layer.

Wherein, if the second stress layer has tensile stress and the first stress layer has tensile stress, the gate electrode and source/drain covered transistors under the second stress layer are PMOS transistors and NMOS transistors. If the second stress layer has compressive stress and the first stress layer has compressive or tensile stress, the gate electrode and source/drain covering the second stress layer are PMOS transistors.

The present invention also provides a method for manufacturing the CMOS component, and the method is as follows. Firstly, a gate electrode is formed on the active area of the base, and a shallow doped area is formed on the active area of the base on both sides of the gate electrode. Then, conformally form a stress buffer liner on both sides of the gate electrode and partially extend to the surface of the substrate, and form a spacer on the stress buffer liner on both sides of the gate electrode. Then, a heavily doped region is formed on the active region of the substrate not covered by the gate electrode and the spacer on both sides of the gate electrode, wherein the above-mentioned lightly doped region and heavily doped region form a source/drain region. After the source/drain region is formed, the spacer is removed, and a stress layer is covered on the gate electrode, the stress buffer liner and the source/drain, and is in contact with the stress buffer liner, thereby improving the gate electrode. Stress in a channel region in the substrate below the electrodes.

Furthermore, the present invention also provides a method for manufacturing the other CMOS component, and the method is as follows. Firstly, a gate electrode is formed on the active area of the substrate, wherein the active area is defined by at least one isolation element formed in the base, and the isolation element contains a first stress layer. Then a lightly doped region is formed in the active region of the substrate on both sides of the gate electrode and contacts the above-mentioned isolation components. Then, conformally form a stress buffer liner on both sides of the gate electrode and partially extend to the surface of the substrate, and form a spacer on the stress buffer liner on both sides of the gate electrode. Then, a heavily doped region is formed on the active region of the substrate not covered by the gate electrode and the spacer on both sides of the gate electrode, wherein the above-mentioned lightly doped region and heavily doped region form a source/drain region. After the source/drain region is formed, the spacer is removed, and a second stress layer is covered on the gate electrode, the stress buffer liner and the source/drain, and is in contact with the stress buffer liner, by The first stress layer and the second stress layer are used to increase the stress of a channel region in the substrate under the gate electrode.

In the above process, before removing the spacer, it may further include performing a self-aligned silicide process to form a metal silicide on the surface of the source/drain.

In addition, after removing the spacers, a self-aligned silicide process may be performed to form a metal silicide on the surface of the source/drain.

The thickness of the above-mentioned stress buffering liner is preferably less than 500 angstroms, and the material can be silicon oxide.

The material of the above-mentioned stress layer can be silicon nitride (SiN), silicon oxynitride (SiON), or a laminated layer of silicon nitride (SiN) and silicon oxynitride (SiON). Its formation methods include plasma enhanced chemical vapor deposition (PECVD), rapid thermal process chemical vapor deposition (RTCVD), atomic level chemical vapor deposition (ALCVD), or low pressure chemical vapor deposition (LPCVD).

In the manufacturing method of the above-mentioned CMOS device, the following steps may be further included: forming an interlayer dielectric layer on the stress layer or the second stress layer; using the stress layer or the second stress layer as an etch stop layer, etching a contact window opening in the electrical layer; and removing the stress layer or the second stress layer in the contact window opening.

To sum up, using the structure and method provided by the present invention, the mechanical stress can be concentrated in the channel region, so as to form a transistor with high-speed operation and low energy consumption.

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, a preferred embodiment is specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

Description of drawings

1A to 1E are schematic diagrams illustrating a method of manufacturing a CMOS device of the present invention.

2A to 2G are schematic diagrams illustrating another method of manufacturing a CMOS device of the present invention.

Detailed ways

According to the research results, for a P-channel transistor, when the compressive stress or the tensile stress of the channel region is increased, the mobility of hole carriers will be increased. For N-channel transistors, when the compressive stress of the channel region is reduced, that is, when the tensile stress of the channel region is increased, the mobility of electron carriers will be increased. In order to increase the mobility of carriers in the channel region, the present invention provides a structure and a manufacturing method of a CMOS device that can effectively increase the stress in the channel region.

structure:

The present invention provides a structure of a CMOS device, as shown in FIG. 1D . In this structure, the gate electrode 104 is disposed on the substrate 100 , and the source/drain electrodes S/D are disposed in the substrate 100 on both sides of the gate electrode 104 . Wherein, the material of the gate electrode 104 may be polysilicon, metal, silicon germanium, or polysilicon containing germanium.

In addition, a gate dielectric layer 102 is disposed on the gate electrode 104 and the substrate 100, and its material may be silicon oxide.

The stress buffer liner 110 is conformably disposed on both sides of the gate electrode 104 and partially extends to the surface of the substrate 100 . The thickness of the stress buffering liner 110 is controlled below 500 angstroms, and its material can be silicon oxide.

Next, the stress layer 118 is provided on the gate electrode 104, the stress buffer liner 110 and the source/drain.S/D, and is in contact with the gate electrode 104 and the stress buffer liner 110, thereby improving the The stress of the channel region 114 in the underlying substrate 100 . Wherein, the stress layer 118 is made of silicon nitride (SiN), silicon oxynitride (SiON), or a laminated layer of silicon nitride (SiN) and silicon oxynitride (SiON).

If the stress layer 118 has tensile stress, the transistors formed by the gate electrode 104 and the source/drain S/D covered under the stress layer 118 are PMOS transistors and NMOS transistors.

If the stress layer 118 has compressive stress, the transistor formed by the gate electrode 104 and the source/drain S/D covering the stress layer 118 is a PMOS transistor.

In addition, between the stress layer 118 and the source/drain S/D, a metal silicide layer 116 is provided to reduce the sheet resistance of the source/drain S/D, which also exhibits appropriate compressive stress and can Improve the performance of PMOS transistors. Usually, a metal silicide layer 116 of the same material is also disposed between the stress layer 118 and the gate electrode 104 .

In addition, an ion implantation process (not shown) can also be used to implant such as argon (Ar) ions or oxygen (O) ions into the stress layer 118, and the operation timing is after the stress layer 118 is formed, and after the ion implantation is completed, then A tempering process at 350° C.˜700° C. is performed to increase the compressive stress of the stress layer 118 , thereby properly adjusting the overall stress in the channel region 114 .

Moreover, the present invention also provides another structure of CMOS components, as shown in FIG. 2F . In this structure, the gate electrode 210 is disposed on the substrate 200 in the active area AA defined by the two shallow trench isolation elements STI', and the source/drain S/D are disposed on both sides of the gate electrode 210 The substrate 200 is attached to the adjacent shallow trench isolation device STI'. Wherein, a conformable first stress layer 205 is disposed in the shallow trench isolation device STI'.

In addition, the material of the gate electrode 210 can be polysilicon, metal, silicon germanium, or polysilicon containing germanium, and a gate dielectric layer 208 is disposed on the gate electrode 210 and the substrate 200, and its material can be silicon oxide.

The stress buffer liner 214 is conformably disposed on both sides of the gate electrode 210 and partially extends to the surface of the substrate 200 . The thickness of the stress buffering liner 214 is controlled below 500 angstroms, and its material can be silicon oxide.

Next, the second stress layer 224 is disposed on the gate electrode 210, the stress buffer liner 214 and the source/drain S/D, and is in contact with the gate electrode 210 and the stress buffer liner 214, by being disposed on the shallow The influence of the first stress layer 205 in the trench isolation device STI′ and the second stress layer 224 disposed on the surface of the gate electrode increases the stress of the channel region 220 in the substrate 200 under the gate electrode 210 . Wherein, the material of the first stress layer 205 and the second stress layer 224 can be silicon nitride (SiN), silicon oxynitride (SiON), or a laminated layer of silicon nitride (SiN) and silicon oxynitride (SiON).

If the second stress layer 224 has tensile stress and the first stress layer 205 has tensile stress, the gate electrode 210 covered under the second stress layer 224 and the transistor composed of source/drain S/D are: PMOS transistor or NMOS transistor.

If the second stress layer 224 has compressive stress and the first stress layer 205 has tensile or compressive stress, the transistor formed by the gate electrode 210 and the source/drain S/D covered under the second stress layer 224 will be is a PMOS transistor.

In addition, between the second stress layer 224 and the source/drain S/D, a metal silicide layer 222 may be provided to reduce the sheet resistance of the source/drain S/D, which may also exhibit proper The compressive stress improves the performance of the PMOS transistor. Usually, a metal silicide layer 222 of the same material is also disposed between the second stress layer 224 and the gate electrode 210 .

In addition, an ion implantation process (not shown) can also be used to implant such as argon (Ar) ions or oxygen (O) ions into the first stress layer 205 and the second stress layer 224, and the operation timing is when the stress layers are formed. Afterwards, after the ion implantation is completed, a tempering process at 350° C. to 700° C. is performed to increase the compressive stress of these stress layers, thereby properly adjusting the overall stress in the channel region 220 .

Manufacturing method:

First embodiment:

1A to 1E are schematic diagrams illustrating a method of manufacturing a CMOS device of the present invention.

First, please refer to FIG. 1A , a substrate 100 is provided, and the substrate 100 has an active area AA. The active area AA is defined by forming an isolation device structure, such as a shallow trench isolation device STI, in the substrate 100 .

Next, transistors are formed for the active area, which can be PMOS transistors and NMOS transistors. As shown in the figure, a gate dielectric layer 102 and a gate electrode 104 are formed on a substrate 100, wherein the material of the gate dielectric layer 102 can be silicon oxide, and the material of the gate electrode 104 can be polysilicon, metal, silicon Germanium or polysilicon containing germanium. The method for forming the gate dielectric layer 102 and the gate electrode 104 is, for example, sequentially depositing a dielectric layer and a conductive layer on the substrate 100, and forming a patterned mask layer (not shown) on the conductive layer. ), then, using the patterned mask layer as a mask, anisotropic etching is performed on the conductive layer and the dielectric layer in sequence to form the gate dielectric layer 102 and the gate electrode 104 as shown in the figure, and then Remove the patterned mask layer.

Afterwards, a shallowly doped region 106 is formed in the active region AA of the substrate 100 on both sides of the gate electrode 104, and its formation method is to implant dopants not covered by the gate electrode 104 and the shallow trench isolation device STI by ion implantation. covered substrate 100.

Next, referring to FIG. 1B , a stress buffer liner 110 is conformally formed on both sides of the gate electrode 104 and partially extends to the surface of the substrate 100 . The thickness of the above-mentioned stress buffering liner 110 is less than 500 angstroms, and its material can be silicon oxide. The stress buffer liner 110 is not only used as a stress buffer, but also used to protect the sidewall of the gate electrode 104 and the region near the channel region 114 . Afterwards, a spacer 108 is formed on the stress buffer liner 110 at both sides of the gate electrode 104 . The above-mentioned material of the spacer 108 can be silicon nitride or a stacked layer of silicon oxide/silicon nitride. Wherein, the method for forming the stress buffer liner 110 and the spacer 108 is, for example, sequentially forming a thin insulating layer and another relatively thin layer on the exposed surfaces of the substrate 100, the gate electrode 104 and the gate dielectric layer 102. thick insulating layer; then, anisotropic etching is used to form a spacer 108 and a stress buffer liner 110 .

Next, a heavily doped region 112 is formed in the active region AA of the substrate 100 that is not covered by the gate electrode 104 and the spacer 108 on both sides of the gate electrode 104. In the substrate 100 covered by the gate electrode 104 , the spacer 108 and the STI. The lightly doped region 106 and the heavily doped region 112 are the source/drain regions S/D of the transistor.

Next, referring to FIG. 1C , the spacer 108 is removed by wet etching or dry etching to expose the stress buffer liner 110 .

Before removing the spacer 108, it further includes performing a self-aligned silicide process to form a metal silicide layer 116 on the surface of the source/drain S/D; or after removing the spacer 108, A self-aligned silicide process is performed to form a metal silicide layer 116 on the surface of the source/drain S/D, as shown in FIG. 1C . In the aforementioned self-aligned silicide process, if the material of the gate electrode 104 is polysilicon, silicon germanium or polysilicon containing germanium, a metal silicide layer 116 is also formed on its surface, as shown in the figure.

1D, after removing the spacer 108 and completing the self-aligned silicide process, a stress layer 118 is covered on the gate electrode 104, the stress buffer liner 110 and the source/drain S/D, and In contact with the gate electrode 104 and the stress buffer liner 110 , thereby increasing the stress of the channel region 114 in the substrate 100 below the gate electrode 104 .

The above-mentioned stress layer 118 can be a compressive stress layer or a tensile stress layer, and its material can be silicon nitride (SiN), silicon oxynitride (SiON), or silicon nitride (SiN) and silicon oxynitride (SiON). The stacked layer has a thickness of about 300-700 Angstroms (A), and its formation method can be plasma-enhanced chemical vapor deposition (PECVD), rapid thermal process chemical vapor deposition (RTCVD), atomic-level chemical vapor deposition method (ALCVD), low pressure chemical vapor deposition (LPCVD).

When the stress layer 118 is a tensile stress layer using a silicon nitride (SiN)/silicon oxynitride (SiON) laminate, the tensile stress of the upper layer is preferably greater than that of the lower layer. At this time, the material on the upper layer of the stack is preferably silicon oxynitride or a silicon-rich nitride layer with a higher silicon content, while the material on the lower layer of the stack is preferably silicon nitride or nitrogen-containing A higher amount of silicon nitride layer (nitrogen-rich nitride).

By controlling the conditions of formation, the stress of the formed film can be adjusted. According to research, the factors that can control the stress include temperature, pressure or process gas ratio. If it is a plasma deposition method, the factors that can control the stress include Plasma power.

Taking the plasma-enhanced chemical vapor deposition method to form the stress layer 118 made of silicon nitride and having compressive stress as an example, the required temperature is approximately between 300° C. and 500° C., and the required pressure is approximately between 1.33× Between 10 ² Pascal (Pa) (1.0 Torr (torr)) and 2.0×10 ² Pa (1.5 Torr), the required plasma power is roughly between 1000 watts (W) and 2000 watts, and the process The gas can be NH ₃ : SiH ₄ , the ratio is about 4-10.

Taking the stress layer 118 formed by rapid thermal process chemical vapor deposition as an example, the material is made of silicon nitride and has tensile stress. The required temperature is approximately between 300° C. and 800° C., and the required pressure is approximately between 2.0× Between 10 ⁴ Pa (150 Torr) and 4.0×10 ⁴ Pa (300 Torr), the process gas can be NH ₃ : SiH ₄ , the ratio is roughly 50-400; or the process gas can be dichlorosilane ( dichlorosilane, SiH ₂ Cl ₂ , DCS for short): NH ₃ , the ratio is roughly 0.1-1.

Taking the formation of the stress layer 118 made of silicon nitride and having compressive stress by the low-pressure chemical vapor deposition method as an example, the required temperature is approximately between 400° C. and 750° C., and the required pressure is approximately between 13.3 Pa (0.1 Torr Between (torr) and 6.7×10 ³ Pa (50 torr), the process gas can be dichlorosilane and NH ₃ , the ratio is roughly 1-300.

If the stress layer 118 has tensile stress, the transistor formed by the gate electrode 104 and the source/drain S/D covered under the stress layer 118 can be a PMOS transistor or an NMOS transistor. In this case, compared with the conventional structure without removing the spacer, the compressive stress of the channel region 114 of the CMOS device of the present invention will be reduced by about 93-128 MPa, thereby improving the migration of electrons and hole carriers in the channel region Rate.

If the stress layer 118 has compressive stress, the transistor formed by the gate electrode 104 and the source/drain S/D covering the stress layer 118 is a PMOS transistor. In this case, compared with the conventional structure without removing the spacers, the compressive stress of the channel region 114 of the CMOS device of the present invention increases by about 93-128 MPa, thereby increasing the mobility of hole carriers in the channel region.

In addition, an ion implantation process (not shown) can also be used to implant such as argon (Ar) ions or oxygen (O) ions into the stress layer 118. The operation timing is after the stress layer 118 is formed, and after the ion implantation is completed, then A tempering process at 350° C.˜700° C. is performed to increase the compressive stress of the stress layer 118 , thereby properly adjusting the overall stress in the channel region 114 .

In addition, the above-mentioned stress layer 118 can also be used as an etching stop layer for the subsequent contact window process.

Then carry out the subsequent process, for example, the inline process. As shown in FIG. 1E , an interlayer dielectric layer 120 is formed on the stress layer 118, and its material is, for example, silicon oxide, borophosphosilicate glass (BPSG), or other similar properties, and the interlayer dielectric layer 120 After planarization, contact openings 122 are formed in the ILD layer 120 and the stress layer 118 by a lithographic etching process. In the etching step of the contact window, the above-mentioned stress layer 118 is used as an etching stop layer. After etching to expose the stress layer 118 in the contact window opening 122, the etching conditions are changed to remove the stress layer in the contact window opening 122. 118 until the component area to be online is exposed.

Second embodiment:

2A to 2G are schematic diagrams illustrating a method for manufacturing a CMOS device according to another embodiment of the present invention.

First, please refer to FIG. 2A , a substrate 200 is provided, the substrate 200 has an active area AA, and the active area AA is defined by forming two trenches 202 in the substrate 200 . Next, a lining layer 204 is respectively formed in the trenches 202 to smooth the surface of the trenches 202 . The lining layer 204 is, for example, a silicon oxide layer formed by thermal oxidation. Then, a first stress layer 205 is conformally formed in the trench 202 and on the substrate 200 and covers the lining layer 204 in the trench 202 . Here, the first stress layer 205 can be formed by referring to the manufacturing method of the stress layer 118 in the aforementioned first embodiment. An insulating material 206 is then deposited on the substrate 200 and filled into the trench 202 .

2B, the insulating material 206 higher than the surface of the substrate 200 is removed by performing a planarization step (not shown) such as a chemical mechanical polishing process, and an insulating layer 206a is left in the trench 202. . Then, an etching step (not shown) is performed to remove part of the first stress layer on the surface of the substrate in the active region AA, and finally a first stress layer 205 conforming to the surface of the trench is left in the trench, and Shallow trench isolation devices STI' for defining different active regions are formed in the trench 202 .

Referring to FIG. 2C , a transistor is then formed in the active area AA, and the transistor can be a PMOS transistor or an NMOS transistor. As shown in the figure, a gate dielectric layer 208 and a gate electrode 210 are formed on the substrate 200, wherein the material of the gate dielectric layer 208 can be silicon oxide, and the material of the gate electrode 210 can be polysilicon, metal, silicon Germanium or polysilicon containing germanium. The method for forming the gate dielectric layer 208 and the gate electrode 210, for example, may be to sequentially deposit a dielectric layer and a conductive layer on the substrate 200, and form a patterned mask layer (not shown) on the conductive layer. shown), then, using the patterned mask layer as a mask, the conductive layer and the dielectric layer are sequentially anisotropically etched to form the gate dielectric layer 208 and the gate electrode 210 as shown in the figure, Then remove the patterned mask layer.

Afterwards, a shallow doped region 212 is formed in the active region AA of the substrate 200 on both sides of the gate electrode 210, and the method of forming it is to implant dopants not covered by the gate electrode 210 and the shallow trench isolation device STI by ion implantation. ' covered substrate 200 .

Next, referring to FIG. 2D , a stress buffer liner 214 is conformally formed on both sides of the gate electrode 210 and partially extends to the surface of the substrate 200 . The thickness of the above-mentioned stress buffering liner 214 is less than 500 angstroms, and its material can be silicon oxide. The stress buffer liner 214 is not only used as a stress buffer, but also used to protect the sidewall of the gate electrode 210 and the region near the channel region 220 . Afterwards, a spacer wall 216 is formed on the stress buffer liner 214 at both sides of the gate electrode 210 . The above-mentioned material of the spacer 216 can be silicon nitride or a stacked layer of silicon oxide/silicon nitride. Wherein, the method for forming the stress buffer liner 214 and the spacer 216 may be, for example, sequentially forming a thin insulating layer and another insulating layer sequentially on the exposed surfaces of the substrate 200, the gate electrode 210 and the gate dielectric layer 208. thicker insulating layer; then, anisotropic etching is used to form a spacer 216 and a stress buffer liner 214 .

Next, a heavily doped region 218 is formed in the active region AA of the substrate 200 that is not covered by the gate electrode 210 and the spacer 216 on both sides of the gate electrode 210. In the substrate 200 covered by the gate electrode 210 , the spacer 216 and the shallow trench isolation device STI′. The lightly doped region 212 and the heavily doped region 218 constitute the source/drain region S/D of the transistor.

Next, referring to FIG. 2E , the spacer 216 is removed by wet etching or dry etching to expose the stress buffer liner 214 .

Before removing the spacer 216, it may further include performing a self-aligned silicide process to form a metal silicide layer 222 on the surface of the source/drain S/D; or after removing the spacer 216 , performing a self-aligned silicide process to form a metal silicide layer 222 on the surface of the source/drain S/D, as shown in FIG. 2E . In the aforementioned self-aligned silicide process, if the material of the gate electrode 210 is polysilicon, silicon germanium, or polysilicon containing germanium, a metal silicide layer 222 is also formed on its surface, as shown in the figure. Here, the metal silicide layer 222 formed at the surface of the source/drain S/D may also exhibit a compressive stress for the channel region 220 .

2F, after removing the spacer 216 and completing the self-aligned silicide process, a second stress layer 224 is covered on the gate electrode 210, the stress buffer liner 214 and the source/drain S/D. , and is in contact with the gate electrode 210 and the stress buffer liner 214 , so as to increase the stress of the channel region 220 in the substrate 200 below the gate electrode 210 .

In addition, an ion implantation process (not shown) can also be used to implant such as argon (Ar) ions or oxygen (O) ions into the first stress layer 205 and the second stress layer 224, and the operation timing is when the stress layers are formed. Afterwards, after the ion implantation is completed, a tempering process at 350° C. to 700° C. is performed to increase the compressive stress of the first and second stress layers, thereby appropriately adjusting the overall stress in the channel region 220 .

In addition, the above-mentioned second stress layer 224 can also be used as an etching stop layer for the subsequent contact window process.

Then carry out the subsequent process, for example, the inline process. As shown in FIG. 2G, an inner layer dielectric layer 226 is formed on the second stress layer 224, and its material is, for example, silicon oxide, borophosphosilicate glass (BPSG), or other materials with similar properties, and the inner layer dielectric layer After the electrical layer 226 is planarized, contact openings 228 are formed in the ILD layer 226 and the second stress layer 224 by a photolithographic etching process. In the etching step of the contact window, the above-mentioned second stress layer 224 is used as an etching stop layer, and after being etched to expose the second stress layer 224 in the contact window opening 228, the etching conditions are changed to remove the second stress layer 224 in the contact window opening 228. The second stress layer 224 until the component area to be connected is exposed.

The above-mentioned first stress layer 205 and second stress layer 224 can be compressive stress layer or tensile stress layer, and their material can be silicon nitride (SiN), silicon oxynitride (SiON), or silicon nitride (SiN) and silicon oxynitride (SiON), the thicknesses of which are about 20-300 angstroms (A) and 300-700 angstroms (A), and the formation method can be plasma-enhanced chemical vapor deposition (PECVD) , Rapid Thermal Chemical Vapor Deposition (RTCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Atomic Level Chemical Vapor Deposition (ALCVD), Low Pressure Chemical Vapor Deposition (LPCVD). When the stress layer (the first stress layer 205 or the second stress layer 224) is a tensile stress layer using silicon nitride (SiN)/silicon oxynitride (SiON) lamination, the tensile stress in the upper layer is better than that in the lower layer The land is big. At this time, the material of the lower layer of the stack is preferably silicon oxynitride or silicon-rich nitride with a higher silicon content, while the material of the upper layer of the stack is preferably silicon nitride or a silicon-rich nitride layer with a higher silicon content. Higher silicon nitride layer (nitrogen-rich nitride).

By controlling the conditions of formation, the stress of the formed film can be adjusted. According to research, the factors that can control the stress include temperature, pressure or process gas ratio. If it is a plasma deposition method, the factors that can control the stress include Plasma power.

Taking the plasma-enhanced chemical vapor deposition method to form the second stress layer 224 made of silicon nitride and having compressive stress as an example, the required temperature is approximately between 300° C. and 500° C., and the required pressure is approximately between Between 1.33×10 ² Pa (1.0 Torr (torr)) and 2.0×10 ² Pa (1.5 Torr), the required plasma power is roughly between 1000 watts (W) and 2000 watts, and the process gas It can be NH ₃ : SiH ₄ , the ratio is roughly 4-10.

Taking the formation of the second stress layer 224 made of silicon nitride and having tensile stress by the rapid thermal process chemical vapor deposition method as an example, the required temperature is approximately between 300° C. and 800° C., and the required pressure is approximately between Between 2.0×10 ⁴ Pa (150 Torr) and 4.0×10 ⁴ Pa (300 Torr), the process gas can be NH ₃ : SiH ₄ , the ratio is roughly 50-400; or the process gas can be dichloro Silane (dichlorosilane, SiH2Cl2, DCS for short): NH ₃ , the ratio is roughly 0.1-1.

Taking the formation of the second stress layer 224 made of silicon nitride and having compressive stress by the low-pressure chemical vapor deposition method as an example, the required temperature is approximately between 400° C. and 750° C., and the required pressure is approximately between 13.3 Pa ( Between 0.1 Torr (torr) and 6.7×10 ³ Pa (50 Torr), the process gas can be DCS:NH ₃ , the ratio is approximately 1-300.

If the second stress layer 224 has tensile stress and the first stress layer 205 has tensile stress, the transistor formed by the gate electrode 210 and the source/drain S/D covering the second stress layer 224 can be PMOS transistors and NMOS transistors. In this case, compared with the conventional structure without removing the spacer, the compressive stress of the channel region 220 of the CMOS device of the present invention is reduced by about 100-900 MPa, thereby improving the migration of electrons and hole carriers in the channel region Rate.

If the second stress layer 224 has compressive stress and the first stress layer 206a has tensile or compressive stress, the transistor formed by the gate electrode 210 and the source/drain S/D covering the second stress layer 224 is a PMOS transistor. In this case, compared with the conventional structure without the spacer removed, the compressive stress of the channel region 220 of the CMOS device of the present invention increases by about 100-900 MPa, thereby increasing the mobility of hole carriers in the channel region.

To sum up, using the structure and method provided by the present invention, the mechanical stress can be concentrated in the channel region, so as to form a transistor with high-speed operation and low energy consumption.

In the process of manufacturing the transistor, before depositing the stress layer, by adding a process of removing the spacer, the stress of the deposited stress layer can be effectively concentrated in the channel region of the transistor. Therefore, the method is applicable to any process that enhances the performance of transistors through local mechanical stress control. In addition, regarding the manufacture of the stress layer mentioned above, according to the different requirements of the P channel and the N channel, stress layers with compressive stress and tensile stress that meet their requirements can be manufactured respectively.

Therefore, the method for forming the stress layer is not limited to the above method, and other processes that can improve the performance of the transistor by controlling the local mechanical stress are applicable to the present invention.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in this art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope defined by the claims.

Claims (47)

1. A CMOS component, characterized in that comprising: a base; a gate electrode, disposed on the substrate; a source/drain disposed in the substrate on both sides of the gate electrode; a stress buffer liner conformably disposed on both sides of the gate electrode and partially extending to the substrate surface, wherein the stress buffer liner has a thickness less than 500 angstroms; and a stress layer, disposed on the gate electrode, the stress buffer liner and the source/drain, and in contact with the stress buffer liner, so as to increase the stress of a channel region in the substrate below the gate electrode . 2. The CMOS device as claimed in claim 1, wherein the material of the stress buffer liner is silicon oxide. 3. The CMOS device as claimed in claim 1, wherein the stress layer is made of silicon nitride, silicon oxynitride, or a stacked layer of silicon nitride and silicon oxynitride. 4. The CMOS device as claimed in claim 1, wherein the stress layer has tensile stress, and the gate electrode and the source/drain covering the stress layer below constitute a PMOS transistor and an NMOS transistor. transistor. 5 . The CMOS device as claimed in claim 1 , wherein the stress layer has compressive stress, and the transistor formed by the gate electrode and the source/drain covering the stress layer is a PMOS transistor. 6. The CMOS device according to claim 1, further comprising a metal silicide layer disposed between the stress layer and the source/drain, and between the stress layer and the gate electrode . 7. A method for manufacturing a CMOS component, characterized in that it comprises: providing a substrate, the substrate has an active region; forming a gate electrode in the active region; forming a lightly doped region in the active region in the substrate on both sides of the gate electrode; conformally forming a stress buffer liner on both sides of the gate electrode and partially extending to the surface of the substrate; forming a spacer on the stress buffer liner on both sides of the gate electrode; A heavily doped region is formed in the active region of the substrate not covered by the gate electrode and the spacer on both sides of the gate electrode, wherein the lightly doped region and the heavily doped region constitute a source /drain region; remove the spacer; and A stress layer is covered on the gate electrode, the stress buffer liner and the source/drain, and is in contact with the stress buffer liner, so as to increase the stress of a channel region in the substrate under the gate electrode. 8. The method of manufacturing a CMOS device as claimed in claim 7, wherein the thickness of the stress buffer liner is less than 500 angstroms. 9. The method of manufacturing a CMOS device as claimed in claim 7, wherein the material of the stress buffer liner is silicon oxide. 10. The method for manufacturing a CMOS device as claimed in claim 7, wherein the material of the stress layer is selected from the group consisting of silicon nitride, silicon oxynitride, and stacked layers of silicon nitride and silicon oxynitride middle. 11. The manufacturing method of CMOS components as claimed in claim 10, wherein the stress layer is formed by plasma-enhanced chemical vapor deposition, rapid thermal process chemical vapor deposition, atomic level chemical vapor deposition or Low pressure chemical vapor deposition method. 12. The manufacturing method of CMOS components as claimed in claim 7, wherein the stress layer has tensile stress, and the gate electrode and the source/drain covering the stress layer below constitute a PMOS transistor transistors and NMOS transistors. 13. The method of manufacturing a CMOS device according to claim 7, wherein the stress layer has a compressive stress, and the gate electrode and the source/drain covering the stress layer are PMOS transistors. . 14. The manufacturing method of the CMOS device as claimed in claim 7, wherein the material of the spacer is silicon nitride, and the method of removing the spacer is wet etching or dry etching. 15. The manufacturing method of CMOS components as claimed in claim 7, further comprising the following steps: forming an interlayer dielectric layer on the stress layer; using the stress layer as an etch stop layer, etching a contact opening in the ILD layer; and The stress layer in the contact opening is removed. 16. A CMOS component, characterized in that it comprises: A base, provided with at least one isolation component, and the isolation component includes a first stress layer; a gate electrode, disposed on the substrate; a source/drain disposed in the substrate on both sides of the gate electrode and contacting the isolation element; a stress buffer liner conformably disposed on both sides of the gate electrode and partially extending to the surface of the substrate; and A second stress layer is arranged on the gate electrode, the stress buffer liner and the source/drain, and is in contact with the stress buffer liner, and the second stress layer and the first stress layer are used to improve the Stress in a channel region in the substrate below the gate electrode. 17. The CMOS device as claimed in claim 16, wherein the thickness of the stress buffer liner is less than 500 angstroms. 18. The CMOS device as claimed in claim 16, wherein the material of the stress buffer liner is silicon oxide. 19. The CMOS device as claimed in claim 16, wherein the material of the first stress layer is silicon nitride, silicon oxynitride, or a stacked layer of silicon nitride and silicon oxynitride. 20. The CMOS device as claimed in claim 16, wherein the material of the second stress layer is silicon nitride, silicon oxynitride, or a stacked layer of silicon nitride and silicon oxynitride. 21. The CMOS device according to claim 20, wherein the laminated layer of silicon nitride and silicon oxynitride is a tensile stress layer, and the upper layer of the laminated layer has a higher tensile stress than the lower layer thereof . 22. The CMOS device as claimed in claim 20, wherein the material of the lower layer is silicon-rich silicon nitride or silicon oxynitride, and the material of the upper layer is silicon nitride or nitrogen-rich silicon nitride. 23. The CMOS device according to claim 16, wherein the second stress layer has tensile stress and the first stress layer has tensile stress, covering the gate electrode and the gate electrode under the second stress layer Source/drain transistors are PMOS transistors and NMOS transistors. 24. The CMOS device according to claim 16, wherein the second stress layer has compressive stress and the first stress layer has tensile or compressive stress, covering the gate electrode under the second stress layer The transistor formed with the source/drain is a PMOS transistor. 25. The CMOS device as claimed in claim 16, further comprising a metal silicide layer disposed between the second stress layer and the source/drain, and the second stress layer and the gate between the electrodes. 26. The CMOS device as claimed in claim 24, further comprising a metal silicide layer disposed between the second stress layer and the source/drain, and between the second stress layer and the gate Between the electrodes, a compressive stress is provided to the PMOS transistor. 27. A method of manufacturing a CMOS component, comprising: provide a base; forming at least one isolation element in the substrate to define an active region, wherein the isolation element contains a first stress layer; forming a gate electrode in the active region; forming a shallow doped region in the substrate on both sides of the gate electrode in the active region and contacting the isolation component; conformally forming a stress buffer liner on both sides of the gate electrode and partially extending to the surface of the substrate; forming a spacer on the stress buffer liner on both sides of the gate electrode; A heavily doped region is formed in the active region of the substrate not covered by the gate electrode and the spacer on both sides of the gate electrode, wherein the shallowly doped region and the heavily doped region form a source/ drain region; remove the spacer; and A second stress layer is covered on the gate electrode, the stress buffer liner and the source/drain, and is in contact with the stress buffer liner, and the second stress layer is connected with the first stress layer Stress is increased in a channel region in the substrate below the gate electrode. 28. The method of manufacturing a CMOS device as claimed in claim 27, wherein the isolation device is a shallow trench isolation device, and the first stress layer is conformally formed in the shallow trench isolation device. 29. The method of manufacturing a CMOS device as claimed in claim 27, wherein the thickness of the stress buffer liner is less than 500 angstroms. 30. The method for manufacturing a CMOS device as claimed in claim 27, wherein the material of the stress buffer liner is silicon oxide. 31. The method of manufacturing a CMOS device according to claim 27, wherein the material of the first stress layer is selected from silicon nitride, silicon oxynitride, and a stack of silicon nitride and silicon oxynitride in the group. 32. The method for manufacturing a CMOS device as claimed in claim 27, wherein the material of the second stress layer is selected from silicon nitride, silicon oxynitride, and a laminated layer of silicon nitride and silicon oxynitride in the group. 33. The manufacturing method of CMOS components as claimed in claim 27, wherein the forming method of the first stress layer is plasma-enhanced chemical vapor deposition, rapid thermal process chemical vapor deposition, atomic level chemical vapor deposition method or low pressure chemical vapor deposition method. 34. The method for manufacturing a CMOS component as claimed in claim 27, wherein the method for forming the second stress layer is plasma-enhanced chemical vapor deposition, rapid thermal process chemical vapor deposition, atomic level chemical vapor deposition method or low pressure chemical vapor deposition method. 35. The method of manufacturing a CMOS device according to claim 27, wherein the second stress layer has tensile stress and the first stress layer has tensile stress, covering the gate under the second stress layer The transistors formed by the polar electrode and the source/drain are PMOS transistors and NMOS transistors. 36. The manufacturing method of a CMOS device according to claim 27, wherein the second stress layer has compressive stress and the first stress layer has tensile or compressive stress, covering the gate under the second stress layer The transistor formed by the pole electrode and the source/drain is a PMOS transistor. 37. The method of manufacturing a CMOS device as claimed in claim 27, wherein the material of the gate electrode is selected from the group consisting of polysilicon, metal, silicon germanium and polysilicon containing germanium. 38. The method of manufacturing a CMOS device as claimed in claim 27, wherein the spacer is made of silicon nitride. 39. The method of manufacturing a CMOS device as claimed in claim 27, wherein the method for removing the spacer is wet etching. 40. The method for manufacturing a CMOS device as claimed in claim 27, wherein the method for removing the spacer is dry etching. 41. The method of manufacturing a CMOS device as claimed in claim 27, further comprising performing a self-aligned silicide process to form a surface of the source/drain before removing the spacer. metal silicide. 42. The method for manufacturing a CMOS device as claimed in claim 27, further comprising performing a self-aligned silicide process to form a surface of the source/drain after removing the spacer. metal silicide. 43. The method of manufacturing a CMOS device as claimed in claim 36, further comprising performing a self-aligned silicide process to form a surface of the source/drain before removing the spacer. metal silicide, wherein the metal silicide provides a compressive stress for the PMOS transistor. 44. The method of manufacturing a CMOS device as claimed in claim 36, further comprising performing a self-aligned silicide process to form a surface of the source/drain after removing the spacer. metal silicide, wherein the metal silicide provides a compressive stress for the PMOS transistor. 45. The method for manufacturing a CMOS component as claimed in claim 27, further comprising the following steps: forming an interlayer dielectric layer on the stress layer; using the stress layer as an etch stop layer, etching a contact opening in the ILD layer; and The stress layer in the contact opening is removed. 46. The method of manufacturing a CMOS device as claimed in claim 27, further comprising an ion implantation process performed on the second stress layer to adjust the overall stress of the channel region. 47. The method for manufacturing a CMOS device as claimed in claim 46, wherein the dopant used in the ion implantation process is argon ions or oxygen ions.

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