CN121727512A - Multipath amplifier circuit with compact transformer - Google Patents

Abstract

A wireless circuit may include a multipath amplifier circuit having a first amplifier on a first path and a second amplifier on a second path. The first path and the second path may be coupled between an input network and an output network. The input network, the output network, and/or the inter-stage matching network may include a transformer circuit. The transformer circuit may include a first transformer on the first path and a second transformer on the second path. The first transformer may overlap the second transformer on the substrate. The first transformer may be orthogonal to the second transformer such that current on the first transformer does not induce current on the second transformer and vice versa. This may be used to minimize the area occupied by the multipath amplifier circuit while also preserving the isolation between the first path and the second path.

Description

Multipath amplifier circuit with compact transformer

The present application claims priority from U.S. patent application Ser. No. 18/895,227, filed 24 at 9 of 2025, and U.S. patent application Ser. No. 18/895,232, filed 24 at 9 of 2025, which are hereby incorporated by reference in their entireties.

Technical Field

The present disclosure relates generally to electronic devices, including electronic devices having wireless communication circuitry.

Background

Electronic devices often have wireless communication capabilities. An electronic device with wireless communication capability has wireless communication circuitry with one or more antennas. Wireless transceiver circuitry in a wireless communication circuit uses antennas to transmit and receive radio frequency signals.

The radio frequency signals transmitted by the antenna are typically fed through an amplifier circuit. Designing a satisfactory power amplifier circuit for an electronic device can be challenging. For example, if careless, the amplifier circuit may not exhibit a sufficient level of performance and may occupy an excessive amount of area in the electronic device.

Disclosure of Invention

The invention discloses an electronic device that may be provided with a wireless circuit. The wireless circuit may include a multipath amplifier circuit. The multipath amplifier circuit may include at least a first amplifier on a first path and a second amplifier on a second path. The first path and the second path may be coupled in parallel between the input network and the output network. The input network, the output network, and/or the inter-stage matching network of the multipath amplifier circuit may comprise a transformer circuit.

The transformer circuit may include a first transformer on the first path and a second transformer on the second path. The first transformer may overlap the second transformer on the substrate. The first transformer may be orthogonal to the second transformer such that current on the first transformer does not induce current on the second transformer and vice versa. The first transformer may include overlapping windings that laterally surround a central opening in the substrate. The second transformer may include overlapping windings having intersections that configure windings in the second transformer to laterally surround the first and second openings. The first and second openings and the intersection may overlap the central opening. The windings of the first transformer may laterally surround the windings of the second transformer. This may be used to minimize the area occupied by the multipath amplifier circuit while also preserving the isolation between the first path and the second path.

An aspect of the present disclosure provides an amplifier circuit. The amplifier circuit may include a first path. The amplifier circuit may include a first amplifier located on the first path. The amplifier circuit may include a first transformer located on the first path and operably coupled to the first amplifier. The amplifier circuit may include a second path. The amplifier circuit may include a second amplifier located on the second path. The amplifier circuit may include a second transformer located on the second path and operably coupled to the second amplifier. The second transformer may overlap with the first transformer. The second transformer may be orthogonal to the first transformer.

An aspect of the present disclosure provides an amplifier circuit. The amplifier circuit may include a first amplifier. The amplifier circuit may include a second amplifier. The amplifier circuit may include a substrate. The amplifier circuit may include a first transformer operably coupled to an output of the first amplifier. The amplifier circuit may include a second transformer operably coupled to an output of the second amplifier. The first transformer may include a first conductive trace located on the substrate and extending laterally around a first opening on the substrate. The second transformer may include a second conductive trace on the substrate. The second conductive trace may include an intersection overlapping the first opening. The second conductive trace may extend laterally around a second opening and a third opening that overlap and are smaller than the first opening.

An aspect of the present disclosure provides a wireless circuit. The wireless circuit may include an antenna. The wireless circuit may include a power amplifier circuit communicatively coupled to the antenna and configured to transmit radio frequency signals using the antenna. The power amplifier circuit may include a signal splitter. The power amplifier circuit may include a signal combiner. The power amplifier circuit may include a first path coupled between the signal splitter and the signal combiner and having a first amplifier. The power amplifier circuit may include a second path coupled in parallel with the first path between the signal splitter and the signal combiner and having a second amplifier. The signal splitter may include a first transformer communicatively coupled to an input of the first amplifier. The signal splitter may include a second transformer communicatively coupled to an input of the second amplifier. The first transformer may laterally surround the second transformer. The first transformer may be orthogonal to the second transformer.

Drawings

Fig. 1 is a diagram of an exemplary electronic device with wireless circuitry, according to some embodiments.

Fig. 2 is a diagram of an exemplary radio circuit including an amplifier circuit, according to some embodiments.

Fig. 3 is a block diagram of an exemplary multipath amplifier circuit according to some embodiments.

Fig. 4 is a block diagram of an exemplary multipath amplifier circuit with multiple amplifier stages according to some embodiments.

Fig. 5 is a circuit diagram of an exemplary transformer circuit that may be included in a multipath amplifier circuit, according to some embodiments.

Fig. 6 is a layout diagram showing different conductive layers of an exemplary transformer circuit that may be included in a multipath amplifier circuit, according to some embodiments.

Fig. 7 includes graphs of operational characteristics of exemplary transformer circuits of the type shown in fig. 5 and 6, according to some embodiments.

Fig. 8 is a circuit diagram of an exemplary transformer circuit that may be included in an output network of a multipath amplifier circuit, according to some embodiments.

Fig. 9 is a layout diagram of an exemplary transformer circuit in an output network of a multipath amplifier circuit according to some embodiments.

Fig. 10-12 include graphs of operational characteristics of exemplary multipath amplifier circuits of the type shown in fig. 8 and 9, according to some embodiments.

Fig. 13 is a block diagram of an exemplary multipath amplifier circuit with parallel transmit paths, according to some embodiments.

Fig. 14 is a block diagram of an exemplary multipath amplifier circuit with parallel transmit and receive paths, according to some embodiments.

Fig. 15 is a circuit diagram of an exemplary multipath amplifier circuit with parallel transmit paths, according to some embodiments.

Fig. 16 is a circuit diagram of an exemplary multipath amplifier circuit with parallel transmit and receive paths, according to some embodiments.

Detailed Description

The electronic device 10 of fig. 1 may be a computing device such as a laptop computer, a desktop computer, a computer monitor including an embedded computer, a tablet computer, a cellular telephone, a media player, or other handheld or portable electronic device, a smaller device such as a wristwatch device, a hanging device, a headset or earpiece device, a device embedded in glasses, goggles, helmets, or other equipment worn on the head of a user (e.g., an augmented reality, virtual reality, or mixed reality head mounted display device), or another wearable or miniature device, a television, a computer display that does not include an embedded computer, a gaming device, a navigation device, an embedded system (such as one in which electronic equipment with a display is installed in a kiosk or automobile), a voice-controlled speaker connected to the wireless internet, a home entertainment device, a remote control device, a game controller, a peripheral user input device, a wireless base station or access point, equipment that implements the functionality of two or more of these devices, or other electronic equipment.

As shown in the functional block diagram of fig. 1, the device 10 may include components located on or within an electronic device housing, such as housing 12. The housing 12 (which may sometimes be referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or a combination of these materials. In some embodiments, some or all of the housing 12 may be formed of a dielectric or other low conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other embodiments, the housing 12 or at least some of the structures making up the housing 12 may be formed from metal elements.

The device 10 may include a control circuit 14. The control circuit 14 may include a memory device, such as the memory device circuit 16. Storage circuitry 16 may include hard drive storage, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid state drive), volatile memory (e.g., static random access memory or dynamic random access memory), and the like. The storage circuitry 16 may include removable storage media and/or storage integrated within the apparatus 10.

The control circuit 14 may include processing circuitry, such as processing circuitry 18. The processing circuitry 18 may be used to control the operation of the device 10. The processing circuitry 18 may include one or more processors, such as microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application specific integrated circuits, central Processing Units (CPUs), graphics Processing Units (GPUs), and the like. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and/or software. The software code for performing operations in the apparatus 10 may be stored on the storage device circuitry 16 (e.g., the storage device circuitry 16 may comprise a non-transitory (tangible) computer-readable storage medium storing the software code). The software code may sometimes be referred to as program instructions, software, data, instructions, or code. Software code stored on the memory device circuit 16 may be executed by the processing circuit 18.

Control circuitry 14 may be used to run software on device 10 such as satellite navigation applications, internet browsing applications, voice Over Internet Protocol (VOIP) telephone call applications, email applications, media playback applications, operating system functions, and the like. To support interaction with external equipment, the control circuit 14 may be used to implement a communication protocol. Communication protocols that may be implemented using control circuitry 14 include Internet protocol, wireless Local Area Network (WLAN) protocol (e.g., IEEE 802.11 protocol, sometimes referred to as) Such asProtocols or other Wireless Personal Area Network (WPAN) protocols, etc. for other short-range wireless communication links, IEEE 802.11ad protocols (e.g., ultra wideband protocols), cellular telephone protocols (e.g., 3G protocols, 4G (LTE) protocols, 3GPP fifth generation (5G) New Radio (NR) protocols, sixth generation (6G) protocols, THz protocols, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., global Positioning System (GPS) protocols, global navigation satellite system (GLONASS) protocols, etc.), antenna-based spatial ranging protocols, optical communication protocols, or any other desired communication protocol. Each communication protocol may be associated with a corresponding Radio Access Technology (RAT) that specifies the physical connection method used to implement the protocol.

The device 10 may include an input-output circuit 20. The input-output circuit 20 may include an input-output device 22. Input-output device 22 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to an external device. The input-output devices 22 may include user interface devices, data port devices, and other input-output components. For example, the input-output devices 22 may include touch sensors, displays (e.g., touch-sensitive displays and/or force-sensitive displays), lighting components (such as displays without touch sensor capabilities), buttons (mechanical, capacitive, optical, etc.), scroll wheels, touch pads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and/or compasses that detect motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to the display to detect pressure applied to the display), and the like. In some configurations, keyboards, headphones, displays, pointing devices (such as touch pads, mice, and joysticks), and other input-output devices may be coupled to device 10 using wired or wireless connections (e.g., some of input-output devices 22 may be peripheral devices coupled to a main processing unit or other portion of device 10 via wired or wireless links).

The input-output circuitry 20 may include wireless circuitry 24 to support wireless communications. The wireless circuitry 24 (sometimes referred to herein as wireless communications circuitry 24) may include one or more antennas. The wireless circuitry 24 may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, radio frequency transmission lines, and/or any other circuitry for transmitting and/or receiving radio frequency signals using an antenna.

The wireless circuitry 24 may transmit and/or receive radio frequency signals within a corresponding frequency band of radio frequencies (sometimes referred to herein as a communication band or simply "band"). The frequency bands processed by wireless circuitry 24 may include Wireless Local Area Network (WLAN) frequency bands (e.g.,(IEEE 802.11) or other WLAN communication bands) such as the 2.4GHz WLAN band (e.g., 2400MHz to 2480 MHz), the 5GHz WLAN band (e.g., 5180MHz to 5825 MHz), the wireless communication system, and the wireless communication system,6E band (e.g., 5925MHz to 7125 MHz),7 Band and/or othersFrequency bands (e.g., 1875MHz to 5160 MHz), wireless Personal Area Network (WPAN) frequency bands such as 2.4GHzBands or other WPAN communication bands, cellular telephone bands (e.g., bands of about 600MHz to about 5GHz, 3G bands, 4G LTE bands, 5G new radio frequency range 1 (FR 1) bands below 10GHz, 5G new radio frequency range 2 (FR 2) bands between 20GHz and 60GHz, etc.), other centimeter or millimeter wave bands between 10GHz and 100GHz, sub-THz bands between about 100GHz and 10THz (e.g., 6G bands), near Field Communication (NFC) bands (e.g., at 13.56 MHz), satellite navigation bands (e.g., GPS bands of 1565MHz to 1610MHz, global navigation satellite system (GLONASS) bands, beidou navigation satellite system (BDS) bands, etc.), ultra Wideband (UWB) bands operating under IEEE 802.15.4 protocols and/or other ultra wideband communication protocols, communication bands under the 3GPP wireless communication standard family, communication bands under the IEEE 802.xx standard family, and/or any other desired band of interest.

Fig. 2 is a diagram showing exemplary components within the wireless circuitry 24. As shown in fig. 2, the radio circuit 24 may include processing circuitry, such as processing circuitry 26, radio Frequency (RF) transceiver circuitry, such as radio frequency transceiver 28, radio frequency front-end circuitry, such as radio frequency front-end module (FEM) 40, and an antenna 42. Processing circuitry 26 may be coupled to transceiver 28 by baseband path 34. Transceiver 28 may be coupled to antenna 42 via radio frequency transmit line path 36. The radio frequency front end module 40 may be disposed on the radio frequency transmit line path 36 between the transceiver 28 and the antenna 42.

In the example of fig. 2, the wireless circuit 24 is illustrated as including only a single transceiver 28, a single front-end module 40, and a single antenna 42 for clarity. In general, the wireless circuitry 24 may include any desired number of transceivers 28, any desired number of front-end modules 40, and any desired number of antennas 42. If desired, the processing circuitry 26 may include a different processing unit (e.g., a processor) coupled to one or more transceivers 28 through respective baseband paths 34. Each transceiver 28 may include a Transmitter (TX) circuit 30 configured to output an uplink signal to an antenna 42, may include a Receiver (RX) circuit 32 configured to receive a downlink signal from the antenna 42, and may be coupled to one or more antennas 42 through respective radio frequency transmit line paths 36. Each radio frequency transmit line path 36 may have a respective front end module 40 disposed thereon. If desired, two or more front end modules 40 may be disposed on the same radio frequency transmit line path 36. One or more of these rf transmit line paths may be implemented without any front-end modules disposed on the rf transmit line path 36 in the wireless circuitry 24, if desired.

The radio frequency transmit line path 36 may be coupled to an antenna feed on the antenna 42. The antenna feed may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The radio frequency transmit line path 36 may have a positive transmit line signal path coupled to a positive antenna feed terminal on the antenna 42. The radio frequency transmit line path 36 may have a grounded transmit line signal path coupled to a grounded antenna feed terminal on the antenna 42. This example is merely illustrative, and in general, the antenna 42 may be fed using any desired antenna feed scheme. If desired, the antenna 42 may have multiple antenna feeds coupled to one or more radio frequency transmit line paths 36.

The radio frequency transmit line path 36 may include a transmit line for routing radio frequency antenna signals within the device 10 (fig. 1). The transmission lines in the device 10 may include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, transmission lines formed from a combination of these types of transmission lines, and the like. The transmit lines in the device 10, such as the transmit lines in the radio frequency transmit line path 36, may be integrated into a rigid printed circuit board and/or a flexible printed circuit board.

When performing wireless transmission, processing circuitry 26 may provide baseband signals to transceiver 28 via baseband path 34. Transceiver 28 may also include circuitry for converting baseband signals received from processing circuitry 26 into corresponding radio frequency signals. For example, transceiver circuitry 28 may include mixer circuitry for up-converting (or modulating) baseband signals to radio frequencies prior to transmission through antenna 42. Transceiver circuitry 28 may also include digital-to-analog converter (DAC) circuitry and/or analog-to-digital converter (ADC) circuitry for converting signals between the digital domain and the analog domain. Transceiver 28 may transmit radio frequency signals through antenna 42 using Transmitter (TX) 30 via radio frequency transmit line path 36 and front end module 40. The antenna 42 may transmit the radio frequency signal to external wireless equipment by radiating the radio frequency signal into free space.

When performing wireless reception, the antenna 42 may receive radio frequency signals from external wireless equipment. The received radio frequency signals may be communicated to transceiver 28 via radio frequency transmit line path 36 and front-end module 40. Transceiver 28 may include circuitry, such as a Receiver (RX) 32, for receiving signals from front-end module 40 and for converting received radio frequency signals to corresponding baseband signals. For example, transceiver 28 may include a mixer circuit for down-converting (or demodulating) a received radio frequency signal to baseband frequency before passing the received signal through baseband path 34 to processing circuit 26.

Front End Module (FEM) 40 may include radio frequency front end circuitry that operates on radio frequency signals communicated (transmitted and/or received) via radio frequency transmit line path 36. For example, FEM 40 may include front-end module (FEM) components such as radio frequency filter circuitry 44 (e.g., low pass filter, high pass filter, notch filter, band pass filter, multiplexing circuitry, diplexer circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more radio frequency switches), radio frequency amplifier circuitry 48 (e.g., one or more power amplifier circuitry 50 and/or one or more low noise amplifier circuitry 52), impedance matching circuitry (e.g., circuitry that helps match the impedance of antenna 42 to the impedance of radio frequency transmission line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and/or switches that adjusts the frequency response of antenna 42), radio frequency coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and/or any other desired circuitry that operates on radio frequency signals transmitted and/or received by antenna 42. Each of the front end module assemblies may be mounted to a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit substrate. The various front-end module components may also be integrated into a single integrated circuit chip, if desired.

Filter circuitry 44, switching circuitry 46, amplifier circuitry 48, and other circuitry may be disposed along radio frequency transmit line path 36, may be incorporated into FEM 40, and/or may be incorporated into antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) may be adjusted (e.g., using control circuitry 14) to adjust the frequency response and wireless performance of antenna 42 over time.

Transceiver 28 may be separate from front-end module 40. For example, transceiver 28 may be formed on another substrate, such as a main logic board of device 10, a rigid printed circuit board, or a flexible printed circuit that is not part of front-end module 40. Although, for clarity, in the example of fig. 1, control circuit 14 is shown separate from wireless circuit 24, wireless circuit 24 may include processing circuitry that forms part of processing circuit 18 and/or storage circuitry that forms part of storage circuitry 16 of control circuit 14 (e.g., portions of control circuit 14 may be implemented on wireless circuit 24). As one example, portions of transceiver 28 (e.g., a host processor on transceiver 28) and/or processing circuitry 26 may form part of control circuitry 14. The control circuitry 14 (e.g., portions of the control circuitry 14 formed on the processing circuitry 26, portions of the control circuitry 14 formed on the transceiver 28, and/or portions of the control circuitry 14 separate from the radio circuitry 24) may provide control signals (e.g., through one or more control paths in the device 10) that control the operation of the front-end module 40.

Transceiver 28 may include processing WLAN communication bands (e.g.,(IEEE 802.11) or other WLAN communication bands) such as the 2.4GHz WLAN band (e.g., 2400MHz to 2480 MHz), the 5GHz WLAN band (e.g., 5180MHz to 5825 MHz), the wireless communication system, and the wireless communication system,6E band (e.g., 5925MHz to 7125 MHz) and/or othersFrequency bands (e.g., 1875MHz to 5160 MHz),7 Band wireless local area network transceiver circuit processing 2.4GHzA Wireless Personal Area Network (WPAN) transceiver circuit that handles cellular telephone bands (e.g., bands of about 600MHz to about 5GHz, 3G bands, 4G LTE bands, 5G new radio frequency range 1 (FR 1) bands below 10GHz, 5G new radio frequency range 2 (FR 2) bands between 20GHz and 60GHz, 6G bands above 100GHz, etc.), near Field Communication (NFC) transceiver circuits that handles near field communication bands (e.g., at 13.56 MHz), satellite navigation receiver circuits that handle satellite navigation bands (e.g., GPS bands of 1565MHz to 1610MHz, global navigation satellite system (GLONASS) bands, beidou navigation satellite system (BDS) bands, etc.), ultra Wideband (UWB) transceiver circuits that handle communications using IEEE 802.15.4 protocols and/or other ultra wideband communication protocols, and/or any other desired radio frequency transceiver circuits for covering any other desired communication band of interest.

The wireless circuitry 24 may include one or more antennas, such as antenna 42. Any desired antenna structure may be used to form the antenna 42. For example, the antenna 42 may be an antenna having a resonating element formed from a loop antenna structure, a patch antenna structure, an inverted-F antenna structure, a slot antenna structure, a planar inverted-F antenna structure, a helical antenna structure, a monopole antenna, a dipole, a mixture of these designs, or the like. The two or more antennas 42 may be arranged in one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter wave frequencies). Parasitic elements may be included in the antenna 42 to adjust antenna performance. The antenna 42 may be provided with a conductive cavity that supports an antenna resonating element of the antenna 42 (e.g., the antenna 42 may be a back cavity antenna such as a back cavity slot antenna).

As described above, the front-end module 40 may include one or more Power Amplifier (PA) circuits 50 in the transmit (uplink) path. The power amplifier 50 (sometimes referred to as a radio frequency power amplifier circuit, a transmit amplifier circuit, or an amplifier circuit) may be configured to amplify radio frequency signals without changing the signal shape, format, or modulation. For example, the power amplifier 50 may be used to provide 10dB gain, 20dB gain, 10dB-20dB gain, less than 20dB gain, more than 20dB gain, or other suitable amount of gain.

In the implementations described herein as examples, one or more of the amplifiers in the wireless circuit 24 may include a multipath amplifier circuit. The multipath amplifier circuit may include a plurality of amplifier paths coupled in parallel between an input path or load and an output path or load. Fig. 3 is a diagram of an exemplary multipath amplifier circuit 54 that may be used in wireless circuit 24. The multipath amplifier circuit 54 of fig. 3 may, for example, form a PA 50 in the front end module 40, a PA in the transceiver 28, an LNA 52 in the front end module 40, an LNA in the transceiver 28, or any other desired radio frequency amplifier elsewhere in the wireless circuit 24.

As shown in fig. 3, the multipath amplifier circuit 54 may be coupled between an input signal path 60 and an output signal path 58. Although referred to herein as input signal path 60 and output signal path 58, input signal path 60 and output signal path 58 may be formed from respective portions of the same signal path in wireless circuit 24 (e.g., may form respective portions of radio frequency transmit line path 36 of fig. 2). The output signal path 58 may be coupled to an output load, such as load 56. The load 56 may be, for example, the antenna 42 (fig. 2), other circuitry in a transmit chain coupled to the antenna 42, or any other desired load in the wireless circuitry 24.

The multipath amplifier circuit 54 may include input circuitry such as an input network 70 (e.g., an input matching network and/or a signal splitter). The input network 70 may have an input terminal (port) coupled to the input signal path 60. The multipath amplifier circuit 54 may include an output circuit, such as an output network 68 (e.g., an output matching network and/or a signal combiner). Output network 68 may have output terminals (ports) coupled to signal path 58. The input terminals of the input network 70 may form inputs to the multipath amplifier circuit 54. The output terminals of the output network 68 may form the outputs of the multipath amplifier circuit 54.

The multipath amplifier circuit 54 may include a set of two or more amplifier paths 62 coupled in parallel between respective output terminals (ports) of an input network 70 and respective input terminals (ports) of an output network 68. The input network 70 may receive radio frequency signals through the input signal path 60. The input network 70 may include signal splitting circuitry (e.g., balanced signal splitters, quadrature hybrid splitting circuitry, matching circuitry, etc.) that splits the radio frequency signal received from the input signal path 60 between the amplifier paths 62. Each amplifier path 62 may include one or more respective amplifiers that amplify the radio frequency signal and provide the amplified radio frequency signal to an output network 68. Output network 68 may include signal combining circuitry (e.g., balanced signal combiner, one or more transformers, balun, matching circuitry, etc.) that combines the amplified radio frequency signals on each amplifier path 62 together (e.g., into a combined radio frequency signal provided to load 56) on output signal path 58. The multipath amplifier circuit 54 may drive the load 56 using the combined radio frequency signal on the output signal path 58.

The amplifier path 62 in the multipath amplifier circuit 54 may include a first amplifier path 62M (also sometimes referred to herein as a main amplifier path 62M or a primary amplifier path 62M). An amplifier, such as amplifier 64, may be disposed on the main amplifier path 62M. The amplifier 64 is also sometimes referred to herein as a main amplifier 64 or a primary amplifier 64. The main amplifier 64 may amplify the radio frequency signal on the main amplifier path 62M.

The amplifier path 62 in the multipath amplifier circuit 54 may also include a second amplifier path 62A (also sometimes referred to herein as an auxiliary amplifier path 62A or a secondary amplifier path 62A) coupled in parallel with the main amplifier path 62M between the input network 70 and the output network 68 (e.g., between the input and output of the multipath amplifier circuit 54). An amplifier such as amplifier 66 may be disposed on auxiliary amplifier path 62A. The amplifier 66 is also sometimes referred to herein as an auxiliary amplifier 66 or a secondary amplifier 66. Auxiliary amplifier 66 may amplify the radio frequency signal on auxiliary amplifier path 62A. In the example of fig. 3, the multipath amplifier circuit 54 is illustrated as including only a single auxiliary amplifier path 62A for clarity. If desired, the multipath amplifier circuit 54 may include a plurality of auxiliary amplifier paths 62A, each auxiliary amplifier path including a different respective auxiliary amplifier 66.

In practice, the output power of each amplifier may increase linearly as a function of the input power until a certain power level is reached, after which the amplifier becomes saturated, and any further increase in input power does not produce a corresponding linear increase in output power. The main amplifier 64 may be configured or tuned to exhibit a linear response for a range of input power levels and/or output power levels that are different from the auxiliary amplifier 66. The main amplifier 64 may, for example, be turned on and used to amplify radio frequency signals received via the input signal path 60 until a certain output power level is reached beyond which the main amplifier may no longer exhibit linear behavior. Once the main amplifier 64 reaches this point, the auxiliary amplifier 66 may be turned on and may help amplify the radio frequency signal to reach a higher power level (e.g., a power level at which the auxiliary amplifier 66 exhibits a linear response).

This may be used to maximize the range of output power over which the multipath amplifier circuit exhibits linear behavior while also ensuring that the multipath amplifier circuit 54 does not occupy more power than is needed, which increases the efficiency of the amplifier circuit. Amplifiers 66 and 64 may be different types of amplifiers optimized for amplifying signals at different power levels and/or with different characteristics, if desired. Amplifiers 66 and/or 64 may include, for example, class a amplifiers, class AB amplifiers, class D amplifiers, class E amplifiers, class F amplifiers, class G amplifiers, class H amplifiers, class I amplifiers, class T amplifiers, or other types of amplifiers.

Two different types of amplifiers 66 and 64 coupled together in this manner using an input network 70 and an output network 68 are sometimes collectively referred to as doherty amplifiers. The multipath amplifier circuit (circuit) 54 is also sometimes referred to herein as a doherty amplifier 54, a doherty amplifier circuit (circuit) 54, or a multipath amplifier 54. Output network 68 is sometimes referred to herein as doherty output network 68 or doherty output circuit 68. The input network 70 is sometimes referred to herein as a doherty input network 70 or doherty input circuit 70.

The multipath amplifier circuit 54 may include one or more transformers integrated into one or more Transformer Circuits (TCs) 72. For example, the input network 70 may include a first transformer circuit 72 (e.g., an input transformer circuit) and the output network 68 may include a second transformer circuit 72 (e.g., an output transformer circuit). The transformer circuit 72 in the input network 70 may, for example, shunt radio frequency signals received through the input signal path 60 onto the main and auxiliary amplifier paths 62M and 62A, and/or may perform impedance matching (e.g., match the input impedance of the amplifier paths 62A and 62M with the impedance of the input signal path 60). The transformer circuit 72 in the output network 68 may, for example, combine radio frequency signals received through the amplifier paths 62A and 62M onto the output signal path 58 (e.g., as a combined signal on the output signal path 58) and/or may perform impedance matching (e.g., match the output impedance of the amplifier paths 62A and 62M with the impedance of the load 56). The multipath amplifier circuit 54 may drive the load 56 using the combined signal on the output signal path 58.

The example of fig. 3 in which amplifier paths 62A and 62M each comprise a single amplifier represents the simplest case and is non-limiting. Amplifier paths 62A and 62M may include multiple amplifier stages, as shown in the example of fig. 4, if desired. As shown in fig. 4, the main amplifier path 62M may include at least two amplifiers 64-1 and 64-2 coupled in series between an input network 70 and an output network 68. Additionally or alternatively, auxiliary amplifier path 62A may include at least two amplifiers 66-1 and 66-2 coupled in series between input network 70 and output network 68. Amplifiers 64-1 and 66-1 may represent a first amplifier stage of multipath amplifier circuit 54, while amplifiers 64-2 and 66-2 represent a second amplifier stage of multipath amplifier circuit 54. If desired, the multipath amplifier circuit 54 may include an impedance matching circuit located between each amplifier stage, such as an inter-stage matching network (ISM) 73 coupled in series between the amplifiers 66-1 and 66-2 and in series between the amplifiers 64-1 and 64-2. ISM 73 may also include transformer circuitry 72 if desired. The transformer circuit 72 in ISM 73 may, for example, match the output impedance of amplifiers 66-1 and 64-1 to the input impedance of amplifiers 66-2 and 64-2. This can be generalized to any desired number of amplifier stages. If desired, the multipath amplifier circuit 54 may include a respective ISM 73 located between each of the stages. The transformer circuit 72 is sometimes referred to herein as a transformer circuit 72.

Each transformer circuit 72 in the multipath amplifier circuit 54 may include at least a first transformer and a second transformer. The first transformer may be coupled to the main amplifier path 72M. The second transformer may be coupled to auxiliary amplifier path 72A. In some implementations, the first transformer and the second transformer do not overlap on an underlying substrate (e.g., a semiconductor substrate, a printed circuit board, etc.). However, implementing the transformer circuit 72 using non-overlapping transformers causes the transformer circuit 72 to occupy an excessive amount of area on the underlying substrate (e.g., twice the area required for a single transformer on a single amplifier path).

In other implementations, a first transformer in the transformer circuit 72 may overlap a second transformer on the underlying substrate. This may reduce the area occupied by the transformer circuit by half relative to implementations in which the first and second transformers in the transformer circuit do not overlap. However, if care is taken, there will be a non-zero coupling coefficient between the overlapping first and second transformers, which may reduce the isolation between the amplifier paths 62 and may cause the multipath amplifier 54 to exhibit an insufficient level of performance. To alleviate these problems, the transformer circuit 72 may include a first transformer and a second transformer that overlap and are orthogonal to each other. The orthogonality of the first and second transformers effectively eliminates electromagnetic coupling between the first and second transformers, thereby maximizing isolation between the amplifier paths.

Fig. 5 is a circuit diagram of an exemplary transformer circuit 72 with quadrature overlap transformers. The transformer circuit 72 of fig. 5 may be included, for example, in the input network 70 (fig. 3 and 4), the output network 68 (fig. 3 and 4), and/or the ISM 73 (fig. 4). As shown in fig. 5, the transformer circuit 72 may include a first transformer 74M disposed on the main amplifier path 62M (fig. 3 and 4). The transformer 74M is also sometimes referred to herein as a primary transformer 74M, a main transformer 74M, or a main amplifier path transformer 74M. The transformer circuit 72 may also include a second transformer 74A disposed on the auxiliary amplifier path 62A (fig. 3 and 4). The transformer 74A is also sometimes referred to herein as a secondary transformer 74A, auxiliary transformer 74A, or auxiliary amplifier path transformer 74A.

The transformer 74M may include a first winding, coil, or inductor, such as the primary winding 80M. The transformer 74M may also include a second winding, coil, or inductor, such as a secondary winding 82M. The secondary winding 82M is electromagnetically coupled to the primary winding 80M with a non-zero magnetic coupling coefficient k (also sometimes referred to herein as a coupling constant k). The primary winding 80M may be coupled to an input port 76M of the transformer 74M (e.g., the primary winding 80M may extend between a first input terminal and a second input terminal of the input port 76M). The secondary winding 82M may be coupled to the output port 78M of the transformer 74M (e.g., the secondary winding 82M may extend between a first output terminal and a second output terminal of the output port 78M).

The input port 76M is communicatively coupled to an output of the main amplifier 64 (e.g., when the transformer circuit 72 is disposed in the output network 68 of fig. 3), the input signal path 60 (e.g., when the transformer circuit 72 is disposed in the input network 70 of fig. 3 and 4), an output of the amplifier 64-1 (e.g., when the transformer circuit 72 is disposed in the ISM 73 of fig. 4), an output of the amplifier 64-2 (e.g., when the transformer circuit is disposed in the output network 68 of fig. 4), or any other signal source. The output port 78M is communicatively coupled to the output signal path 58 (e.g., when the transformer circuit 72 is disposed in the output network 68 of fig. 3 and 4), the input of the main amplifier 64 (e.g., when the transformer circuit 72 is disposed in the input network 70 of fig. 3), the input of the amplifier 64-2 (e.g., when the transformer circuit 72 is disposed in the ISM 73 of fig. 4), the input of the amplifier 64-1 (e.g., when the transformer circuit 72 is disposed in the input network 70 of fig. 4), or any other load.

In the example of fig. 5, input port 76M includes a differential input terminal pair coupled to a differential signal path of multi-path amplifier circuit 54 (e.g., in main amplifier path 62M and/or input signal path 60), and output port 78M includes a differential output terminal pair coupled to a differential signal path of multi-path amplifier circuit 54 (e.g., in main amplifier path 62M and/or output signal path 58). This is illustrative and not limiting. If desired, the input port 76M may be implemented using a single-ended input terminal coupled to a single-ended signal path (e.g., where one end of the primary winding 80M is shorted to a reference potential such as ground), and/or the output port 78M may be implemented using a single-ended output terminal coupled to a single-ended signal path (e.g., where one end of the secondary winding 82M is shorted to a reference potential such as ground).

The transformer 74A may include a first winding, coil, or inductor, such as a primary winding 80A. The transformer 74A may also include a second winding, coil, or inductor, such as a secondary winding 82A. The secondary winding 82A is electromagnetically coupled to the primary winding 80A with a non-zero coupling coefficient k (e.g., the same non-zero coupling coefficient as the primary winding 80M or a different coupling coefficient from the primary winding 80M). The primary winding 80A may be coupled to the input port 76A of the transformer 74A (e.g., the primary winding 80A may extend between a first input terminal and a second input terminal of the input port 76A). The secondary winding 82A may be coupled to the output port 78A of the transformer 74A (e.g., the secondary winding 82A may extend between a first output terminal and a second output terminal of the output port 78A).

The input port 76A is communicatively coupled to an output of the auxiliary amplifier 66 (e.g., when the transformer circuit 72 is disposed in the output network 68 of fig. 3), the input signal path 60 (e.g., when the transformer circuit 72 is disposed in the input network 70 of fig. 3 and 4), an output of the amplifier 66-1 (e.g., when the transformer circuit 72 is disposed in the ISM 73 of fig. 4), an output of the amplifier 66-2 (e.g., when the transformer circuit is disposed in the output network 68 of fig. 4), or any other signal source. The output port 78A is communicatively coupled to the output signal path 58 (e.g., when the transformer circuit 72 is disposed in the output network 68 of fig. 3 and 4), the input of the auxiliary amplifier 66 (e.g., when the transformer circuit 72 is disposed in the input network 70 of fig. 3), the input of the amplifier 66-2 (e.g., when the transformer circuit 72 is disposed in the ISM 73 of fig. 4), the input of the amplifier 66-1 (e.g., when the transformer circuit 72 is disposed in the input network 70 of fig. 4), or any other load.

In the example of fig. 5, input port 76A includes a differential input terminal pair coupled to a differential signal path of multi-path amplifier circuit 54 (e.g., in auxiliary amplifier path 62A and/or input signal path 60), and output port 78A includes a differential output terminal pair coupled to a differential signal path of multi-path amplifier circuit 54 (e.g., in auxiliary amplifier path 62A and/or output signal path 58). This is illustrative and not limiting. If desired, the input port 76A may be implemented using a single-ended input terminal coupled to a single-ended signal path (e.g., where one end of the primary winding 80A is shorted to a reference potential such as ground), and/or the output port 78A may be implemented using a single-ended output terminal coupled to a single-ended signal path (e.g., where one end of the secondary winding 82A is shorted to a reference potential such as ground).

To minimize the area occupied by the transformer circuit 72 and thus by the multipath amplifier circuit 54, the transformer 74M may overlap the transformer 74A (e.g., the windings of the transformer 74A may overlap the windings of the transformer 74M and/or may overlap the openings surrounded by the windings of the transformer 74M, or vice versa). To eliminate electromagnetic coupling between transformers 74A and 74M, this may maximize isolation between transformers and thus between the different amplifier paths, transformer 74A may be orthogonal to transformer 74M. This means that the transformer is laid out and oriented such that the current flowing through the transformer 74M produces a first magnetic field that does not induce current to flow through the transformer 74A and such that the current flowing through the transformer 74A produces a second magnetic field that does not induce current to flow through the transformer 74M despite the fact that the transformer 74M overlaps the transformer 74A on the underlying substrate.

Fig. 6 is a layout diagram illustrating one example of how transformer circuitry 72 may be disposed on an underlying substrate 84 such that transformer 74A is orthogonal to transformer 74M (and vice versa). Substrate 84 may be a semiconductor substrate, a printed circuit board, or another substrate that includes a stack of alternating metallization layers and insulator, dielectric, and/or semiconductor layers.

Portion 86 of fig. 6 illustrates a first set of one or more metallization layers (e.g., one or more metallization layers on a first set of one or more dielectric, semiconductor, or insulator layers of substrate 84) of substrate 84 for forming primary winding 80M of transformer 74M and primary winding 80A of transformer 74A. Portion 88 of fig. 6 illustrates a second set of one or more metallization layers (e.g., one or more metallization layers on a second set of one or more dielectric, semiconductor, or insulator layers of substrate 84) of substrate 84 for forming secondary winding 82M of transformer 74M and secondary winding 82A of transformer 74A. Portion 90 of fig. 6 illustrates the layout of transformer 74M (including both primary winding 80M and secondary winding 82M), and illustrates transformer 74A (including both primary winding 80A and secondary winding 82A) on substrate 84. Portion 94 of fig. 6 illustrates a layout of transformer circuit 72 (e.g., including both transformers 74M and 74A) on substrate 84.

As shown in the upper half of portion 86 of fig. 6, primary winding 80M of transformer 74M may include conductive trace 96 extending between the terminals of input port 76M and laterally around central opening 114. The conductive trace 96 is illustrated in the example of fig. 6 as comprising one complete loop, turn, coil or winding around the central opening 114. This is illustrative, and in general, the conductive trace 96 may include any desired number of loops, turns, coils, or windings around the central opening 114. If desired, the conductive trace 96 may include a center-tapped conductor, contact or terminal, such as center tap 98. The center tap 98 may be disposed, for example, midway between the terminals of the input port 76M. The center tap 98 may be replaced with a tap at other locations along the length of the conductive trace 96 or may be omitted if desired.

As shown in the upper half of portion 88 of fig. 6, secondary winding 82M of transformer 74M may include a conductive trace 100 extending between the terminals of output port 78M and laterally around a central opening 114. The output port 78M may be located at a side or corner of the transformer 74M opposite the input port 76M, or may be at another location (e.g., the same side or corner as the input port 76M). The conductive trace 100 is illustrated in the example of fig. 6 as comprising one complete loop, turn, coil, or winding around the central opening 114. This is illustrative, and in general, the conductive trace 100 may include any desired number of loops, turns, coils, or windings around the central opening 114. As shown in the upper half of portion 90 of fig. 6, the conductive trace 100 of secondary winding 82M may overlap with the conductive trace 96 of primary winding 80M in transformer 74M. If desired, a center tap 98 of the primary winding 80M may extend between the terminals of the output port 78M.

Returning to the lower half of portion 86 of fig. 6, primary winding 80A of transformer 74A may include a conductive trace 102 extending between the terminals of input port 76A. The conductive traces 102 may be arranged in a figure-8 pattern and may cross over themselves at the cross-over points 108 (e.g., using conductive vias extending between multiple metallization layers of the substrate 84) such that the conductive traces 102 extend laterally around both the first and second openings 110, 112. The parallel sections of the conductive traces 102 extending from the intersection 108 may extend parallel to the linear axis 122 and may separate the opening 110 from the opening 112. Openings 110 and 112 may each span an area less than or equal to half the area spanned by central opening 114 of transformer 74M. If desired, the conductive trace 102 may include a center-tapped conductor, contact, or terminal, such as center tap 104. The center tap 104 may be disposed, for example, midway between the terminals of the input port 76A (e.g., extending along a linear axis 124 orthogonal to the axis 122). The center tap 104 may be replaced with a tap at other locations along the length of the conductive trace 102 or may be omitted if desired. Alternatively, if desired, the parallel sections of the conductive traces 102 extending away from the crossover point 108 may extend parallel to the linear axis 124 (e.g., the transformer 74A may be oriented orthogonal to the orientation shown in fig. 6).

As shown in the lower half of portion 88 of fig. 6, secondary winding 82A of transformer 74A may include a conductive trace 106 extending between the terminals of input port 76A. The output port 78A may be located at a side or corner of the transformer 74A opposite the input port 76A, or may be at another location (e.g., the same side or corner as the input port 76A). The conductive traces 106 may be arranged in a figure-8 pattern and may cross over themselves at the cross-over point 120 such that the conductive traces 106 extend laterally around both the openings 110 and 112. The parallel sections of the conductive traces 106 extending from the intersection 120 may extend parallel to the linear axis 122 and may separate the opening 110 from the opening 112. Alternatively, if desired, the parallel sections of the conductive traces 106 extending away from the crossover point 120 may extend parallel to the linear axis 124 (e.g., the transformer 74A may be oriented orthogonal to the orientation shown in fig. 6).

As shown in the lower half of portion 90 of fig. 6, conductive trace 106 of secondary winding 82A may overlap conductive trace 102 of primary winding 80A in transformer 74A. The intersection 120 of the secondary winding 82A may overlap the intersection 108 of the primary winding 80A. If desired, the center tap 104 of the primary winding 80A may extend between the terminals of the output port 78A. As shown in portion 94 of fig. 6, transformer 74A and its conductive traces 102 and 106 may overlap central opening 114 of transformer 74M in transformer circuit 72. Openings 110 and 112 in transformer 74A may overlap respective portions of central opening 114 of transformer 74M. Conductive trace 100 and conductive trace 96 of transformer 74M may extend laterally around conductive traces 102 and 106 of transformer 74A. Input port 76M, input port 76A, output port 78A, and output port 78M may extend from conductive traces 96, 102, 106, and 100, respectively, at different corners of transformer circuit 72 (e.g., to facilitate coupling of signal paths to each of the ports).

During signaling, current may flow along the conductive trace 102 between the input terminals of the input port 76A. The current may induce a corresponding current to flow along the conductive trace 106 between the output terminals of the output port 78A (e.g., due to a non-zero coupling coefficient between the conductive trace 102 and the overlapping conductive trace 106). The current flowing along conductive trace 102 and the current flowing along conductive trace 106 may generate a magnetic field that is oriented in a first direction (e.g., in the direction of arrow 116) within opening 110 and may generate a magnetic field that is oriented in a second direction (e.g., in the direction of arrow 118) opposite the first direction within opening 112. The magnetic field may electromagnetically couple primary winding 80A to secondary winding 82A within transformer 74A.

However, because the magnetic field in opening 110 is opposite (and equal in magnitude) to the magnetic field in opening 112, the magnetic field in opening 110 may cancel the magnetic field in opening 112 from the perspective of surrounding transformer 74M. This causes both primary winding 80A and secondary winding 82A to exhibit a zero coupling coefficient with primary winding 80M and secondary winding 82M of transformer 74M. Thus, current flowing through conductive traces 102 and 106 does not induce current to flow through conductive traces 96 and 100. In contrast, current flowing through conductive traces 96 and 100 does not induce current to flow through conductive traces 102 and 106. In this manner, windings 80A and 82A, and thus transformer 74A, may be orthogonal to windings 80M and 82M, and thus transformer 74M. This orthogonality maximizes isolation between transformers 74A and 74M and between corresponding amplifier paths coupled to each transformer while also allowing transformer circuit 72 to span half the area of transformers 74M and 74A apart on substrate 84.

The example of fig. 6 is illustrative and not limiting. In general, the conductive traces of transformers 74A and 74M may follow any desired path having any desired number of straight sections and/or curved sections, and may have any desired shape including any desired number of straight edges and/or curved edges. Windings 80M, 82M, 80A, and 82A may include any desired number of turns, and may be provided with other relative orientations that maintain orthogonality between transformers. If desired, the transformer circuit 72 may include a third transformer (not shown) that overlaps the transformers 74A and 74M and is orthogonal to both transformers 74A and 74M. The third transformer may, for example, be arranged in a figure 8 pattern similar to transformer 74A, but with parallel sections extending away from the intersection of the third transformer extending parallel to linear axis 124 instead of linear axis 122 (e.g., the third transformer may be rotated 90 degrees relative to transformer 74A). The conductive traces used to form each transformer may be disposed in one, more than one, or any desired number of metallization layers of the substrate 84.

Fig. 7 includes graphs of various performance characteristics of transformer circuit 72. Curve 138 plots the self inductance of primary winding 80M and secondary winding 82M as a function of frequency. Curve 136 plots the self inductance of primary winding 80A and secondary winding 82A as a function of frequency.

Curve 140 plots the quality (Q) factor of secondary winding 82A. Curve 142 plots the Q factor of primary winding 80A. Curve 144 plots the Q factor of secondary winding 82M. Curve 146 plots the Q factor of primary winding 80M. As shown by curves 140-146, each winding may exhibit a relatively high Q factor (e.g., greater than 10-15 across the operating band of the multipath amplifier circuit).

Curve 152 plots the coupling coefficient between primary winding 80A and secondary winding 82A. Curve 150 plots the coupling coefficient between primary winding 80M and secondary winding 82M. Curve 148 plots the coupling coefficient between the windings of transformer 74M and the windings of transformer 74A. As shown by curve 148, the orthogonality of transformers 74A and 74M results in a coupling coefficient between the transformers of zero or near zero (e.g., the operating frequency band across the amplifier circuit, which may include any desired frequency between 0GHz and 60GHz, as an example, is less than or equal to 0.1). This maximizes the isolation between the amplifier paths and thus maximizes the performance of the multipath amplifier circuit 54. As shown by curves 152 and 150, despite the orthogonality between transformers 74M and 74A, there may be sufficient coupling between windings within transformer 74M to pass current from input port 76M to output port 78M, and sufficient coupling between windings within transformer 74A to pass current from input port 76A to output port 78A. The example of fig. 7 is illustrative and not limiting. In practice, the curves 136-152 may have other shapes. The amplifier circuit may amplify signals at any desired frequency in any desired frequency band.

Fig. 8 is a circuit diagram illustrating one example of how transformer circuit 72 may be implemented in output network 68 of fig. 3 and 4. As shown in fig. 8, the output of the main amplifier 64 (modeled as a current source in fig. 8) may be coupled to an input port 76M of a transformer 74M. Shunt capacitance C1 may couple the input terminal of input port 76M to a reference potential such as ground (e.g., for impedance matching, filtering, etc.), if desired. Similarly, the output of auxiliary amplifier 66 (modeled as a current source in fig. 8) may be coupled to an input port 76A of transformer 74A. Shunt capacitance C2 may couple the input terminal of input port 76A to a reference potential such as ground (e.g., for impedance matching, filtering, etc.), if desired.

The output port 78M of the transformer 74M may include a first output terminal 78M-1 and a second output terminal 78M-2. The output terminal 78M-2 may be shorted to a reference potential such as ground. Output terminal 78M-1 may form an output terminal of transformer circuit 72 (e.g., a signal combiner circuit) and may be coupled to load 56 through output signal path 58. The output port 78A of the transformer 74A may include a first output terminal 78A-1 and a second output terminal 78A-2. The output terminal 78A-1 may be shorted to a reference potential such as ground. Output terminal 78A-2 may be coupled to output terminal 78M-1 of transformer 74M, and thus to the output of transformer circuit 72, through capacitor C5. Shunt capacitor C4 may couple output terminal 78A-2 to a reference potential, such as ground, if desired. Shunt capacitor C3 may couple output terminal 78M-1 to a reference potential, such as ground, if desired.

During signaling, the main amplifier 64 may generate a current that flows through the primary winding 80M of the transformer 74M. This current may induce a current on the secondary winding 82M of the transformer 74M (e.g., via a non-zero coupling coefficient shown by curve 150 of fig. 7). At the same time, auxiliary amplifier 66 may generate a current that flows through primary winding 80A of transformer 74A. This current may induce a current on the secondary winding 82A of the transformer 74A (e.g., via a non-zero coupling coefficient shown by curve 152 of fig. 7). The current in secondary winding 82A may be combined with the current in secondary winding 82M via capacitor C5, causing transformer circuit 72 to output the combined current through output terminal 78M-1. Shunt capacitors C4 and C3 and capacitor C5 may perform impedance matching and/or filtering to combine signals from transformers 74A and 74M onto output signal path 58.

Fig. 9 is a layout diagram of the transformer circuit 72 of fig. 8. As shown in fig. 9, the output of the main amplifier 64 may be coupled to a conductive trace 96 of the transformer 74M at the input port 76M. The output of auxiliary amplifier 66 may be coupled to a conductive trace 102 of transformer 74A at input port 76A. Output terminal 78A-1 on conductive trace 106 of transformer 74A may be coupled to ground. Output terminal 78M-2 on conductive trace 100 of transformer 74M may be coupled to ground. Output terminal 78A-2 on conductive trace 106 of transformer 74A may be coupled to ground through capacitor C4 and may be coupled to output terminal 78M-1 on conductive trace 100 of transformer 74M through capacitor C5. Output terminal 78M-1 may be coupled to output signal path 58.

Fig. 10-12 include graphs of various performance characteristics of the multipath amplifier circuit 54 when the transformer circuit 72 of fig. 8 and 9 is provided in the output network 68 (fig. 3 and 4). The curve 156 of fig. 10 plots the output voltage of the auxiliary amplifier 66 as a function of the normalized input drive voltage amplitude. Curve 154 plots the output voltage of the main amplifier 64. Curve 158 plots the real component of the load impedance of the main amplifier 64 as a function of the normalized input drive voltage amplitude. Curve 160 plots the real component of the load impedance of auxiliary amplifier 66. Curve 162 plots the imaginary part of the load impedance of the main amplifier 64. Curve 164 plots the imaginary part of the load impedance of auxiliary amplifier 66. Curve 166 plots the passive efficiency of the circuit as a function of normalized input drive voltage amplitude. As shown by curve 166, the output network may exhibit relatively high passive efficiency, and thus the multipath amplifier circuit may exhibit relatively high efficiency in terms of load modulation, power backoff, and/or voltage amplitude.

Curve 170 of fig. 11 plots the real component of the load impedance of the main amplifier 64 as a function of frequency at the maximum output power level of the main amplifier 64. Curve 172 plots the imaginary part of the load impedance of the main amplifier 64 as a function of frequency at the maximum output power level of the main amplifier 64. Curve 174 plots the real component of the load impedance of auxiliary amplifier 66 as a function of frequency at the maximum output power level of auxiliary amplifier 66. Curve 176 plots the imaginary part of the load impedance of auxiliary amplifier 66 as a function of frequency at the maximum output power level of auxiliary amplifier 66. Curve 178 plots the passive efficiency of the circuit as a function of frequency. As shown by curve 178, the output network may exhibit relatively high passive efficiency, and thus the multipath amplifier circuit 54 may exhibit relatively high efficiency over its operating bandwidth.

Curve 180 of fig. 12 plots the real component of the load impedance of the main amplifier 64 as a function of frequency at a 6dB power back-off level of the main amplifier 64. Curve 182 plots the imaginary part of the load impedance of the main amplifier 64 as a function of frequency at a 6dB power back-off level of the main amplifier 64. Curve 184 plots the passive efficiency of the circuit as a function of frequency. As shown by curve 184, the output network may exhibit relatively high passive efficiency and, thus, the multipath amplifier circuit 54 may exhibit relatively high efficiency over its operating bandwidth. The examples of fig. 10-12 are illustrative and not limiting. In practice, curves 154 through 182 may have other shapes. The amplifier circuit may amplify signals at any desired frequency in any desired frequency band.

Examples of fig. 3 and 4 in which the multipath amplifier circuit 54 includes a plurality of amplifier paths coupled between a signal splitter (e.g., input network 70) and a signal combiner (e.g., output network 68) are illustrative and not limiting. In other words, the multipath amplifier circuit 54 need not be a doherty amplifier with a main amplifier path and one or more auxiliary amplifier paths. More generally, the multipath amplifier circuit 54 may include a plurality of amplifier paths coupled in parallel between any desired input circuit and output circuit.

Fig. 13 illustrates another example in which the multipath amplifier circuit 54 includes multiple parallel transmit paths, such as a first transmit path 186 and a second transmit path 188, that are not split or combined from a single input path onto a single output path. As shown in fig. 13, the transmit path 186 may include a set of one or more amplifiers 196 (e.g., power amplifiers), such as amplifiers 196-1 and 196-2. The transmit path 186 may include a set of one or more amplifiers 198 (e.g., power amplifiers), such as amplifiers 198-1 and 198-2.

The multipath amplifier circuit 54 may include an input matching network 190 on the transmit paths 186 and 188 and coupled to inputs of amplifiers 196-1 and 198-1, may include an ISM 192 on the transmit paths 186 and 188 and coupled between outputs of the amplifiers 196-1 and 198-1 and inputs of the amplifiers 196-2 and 198-2, and/or may include an output matching network 194 on the transmit paths 186 and 188 and coupled to outputs of the amplifiers 196-2 and 198-2. This can be generalized to any desired number of amplifier stages. The input matching network 190, ISM 192, and/or output matching network 194 may each include a corresponding transformer circuit 72 having orthogonal transformers 74A and 74M as shown and described in connection with fig. 5-12 (e.g., where the transmit path 186 forms the main amplifier path of fig. 5-12, and where the transmit path 188 forms the auxiliary amplifier path of fig. 5-12).

Fig. 14 illustrates another example in which a multipath amplifier circuit includes parallel transmit and receive paths. As shown in fig. 14, the transmit path 186 of fig. 13 may be replaced with a receive path such as receive path 202. The receive path 202 may include a set of one or more amplifiers 200 (e.g., low noise amplifiers), such as amplifiers 200-1 and 200-2. The first matching network 191 may be disposed on the transmit path 188 and the receive path 202. ISM 193 may be disposed on transmit path 188 and receive path 202. The second matching network 195 may be disposed on the transmit path 188 and the receive path 202. This can be generalized to any desired number of amplifier stages. Matching networks 191, ISM 193, and/or matching network 195 may each include a corresponding transformer circuit 72 having transformers 74A and 74M in quadrature, as shown and described in connection with fig. 5-12 (e.g., where transmit path 188 forms the main amplifier path of fig. 5-12, and where receive path 202 forms the auxiliary amplifier path of fig. 5-12). The transmit paths 188 and 186 are also sometimes referred to herein as transmit chains. The receive path 202 is sometimes referred to herein as a receive chain 202.

Fig. 15 is a circuit diagram showing an example in which the multipath amplifier circuit 54 of fig. 13 is provided with the transformer circuit 72 in the input matching network 190, ISM 192, and output matching network 194. As shown in fig. 15, the input matching network 190 may include a first transformer circuit 72-1. The transformer circuit 72-1 may include a first transformer 74M located in the transmit path 188 and coupled between the input of the amplifier 198-1 on the transmit path 188 and the input load R _in1. The transformer circuit 72-1 may also include a first transformer 74A located in the transmit path 186 and coupled between the input of the amplifier 196-1 on the transmit path 186 and the input load R _in2. The first transformer 74M in the transformer circuit 72-1 may overlap and be orthogonal to the first transformer 74A in the transformer circuit 72-1. The transmit paths 188 and 186 are illustrated in the example of fig. 15 as differential signal paths, but may be implemented as single ended signal paths if desired.

ISM 192 may include second transformer circuit 72-2. The transformer circuit 72-2 may include a second transformer 74M located on the transmit path 188 and coupled between the output of the amplifier 198-1 and the input of the amplifier 198-2 on the transmit path 188. The transformer circuit 72-2 may also include a second transformer 74A located on the transmit path 186 and coupled between the output of the amplifier 196-1 and the input of the amplifier 196-2 on the transmit path 186. The second transformer 74M in the transformer circuit 72-2 may overlap and be orthogonal to the second transformer 74A in the transformer circuit 72-2.

The output matching network 194 may include a third transformer circuit 72-3. The transformer circuit 72-3 may include a third transformer 74M located in the transmit path 188 and coupled between the output of the amplifier 198-2 and the output load R _L1. The transformer circuit 72-3 may also include a third transformer 74A located in the transmit path 186 and coupled between the output of the amplifier 196-2 and the output load R _L2. The third transformer 74M in the output matching network 194 may overlap and be orthogonal to the third transformer 74A in the transformer circuit 72-3. The transformer circuits 72-1, 72-2, and 72-3 may configure the multipath amplifier circuit 54 to occupy a minimum amount of area in the device 10 while also maximizing isolation between the transmit paths 186 and 188.

Fig. 16 is a circuit diagram showing an example in which the multipath amplifier circuit 54 of fig. 14 is provided with a transformer circuit 72 in the matching network 191, ISM 193, and output matching network 195. As shown in fig. 16, the matching network 191 may include a first transformer circuit 72-4. The transformer circuit 72-4 may include a first transformer 74M located in the transmit path 188 and coupled between the input of the amplifier 198-1 on the transmit path 188 and the input load R _inPA. The transformer circuit 72-4 may also include a first transformer 74A located in the receive path 202 and coupled between the output of the amplifier 200-1 on the receive path 202 and the output load R _outLNA. The first transformer 74M in the transformer circuit 72-4 may overlap and be orthogonal to the first transformer 74A in the transformer circuit 72-4. The transmit path 188 and the receive path 202 are illustrated in the example of fig. 16 as differential signal paths, but may be implemented as single-ended signal paths if desired. Matching network 191 may form an input matching network for transmit path 188 and may form an output matching network for receive path 202.

ISM 193 may include second transformer circuit 72-5. The transformer circuit 72-5 may include a second transformer 74M located on the transmit path 188 and coupled between the output of the amplifier 198-1 and the input of the amplifier 198-2 on the transmit path 188. The transformer circuit 72-5 may also include a second transformer 74A located on the receive path 202 and coupled between the output of the amplifier 200-2 and the input of the amplifier 200-1 on the receive path 202. The second transformer 74M in the transformer circuit 72-5 may overlap and be orthogonal to the second transformer 74A in the transformer circuit 72-5.

The matching network 195 may include a third transformer circuit 72-6. The transformer circuit 72-6 may include a third transformer 74M located in the transmit path 188 and coupled between the output of the amplifier 198-2 and the output load R _LPA. The transformer circuit 72-6 may also include a third transformer 74A located in the receive path 202 and coupled between the input of the amplifier 200-2 and the input load R _inLNA. The third transformer 74M in the transformer circuit 72-6 may overlap and be orthogonal to the third transformer 74A in the transformer circuit 72-6. The matching network 195 may form an input matching network for the receive path 202 and may form an output matching network for the transmit path 188. The transformer circuits 72-4, 72-5, and 72-6 may configure the multipath amplifier circuit 54 to occupy a minimum amount of area in the device 10 while also maximizing isolation between the transmit path 186 and the receive path 202.

As used herein, the term "concurrent" refers to overlapping in time at least partially. In other words, a first event and a second event are referred to herein as being "concurrent" with each other if at least some of the first event occurs concurrently with at least some of the second event (e.g., if at least some of the first event occurs during at least some of the second event, occurs concurrently with at least some of the second event, or occurs when at least some of the second event occurs). The first event and the second event may be concurrent if the first event and the second event are synchronized (e.g., if the entire duration of the first event overlaps in time with the entire duration of the second event), but the first event and the second event may also be concurrent if the first event and the second event are unsynchronized (e.g., if the first event begins before or after the second event begins, if the first event ends before or after the second event ends, or if the first event and the second event do not overlap in part in time). As used herein, the term "at a..once..is synonymous with" concurrent ".

The methods and operations described above in connection with fig. 1-16 may be performed by components of device 10 using software, firmware, and/or hardware (e.g., dedicated circuitry or hardware). The software code for performing these operations may be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more of the components of the device 10 (e.g., the storage circuitry 16 and/or the wireless communication circuitry 24 of fig. 1). The software code may sometimes be referred to as software, data, instructions, program instructions, or code. The non-transitory computer readable storage medium may include a drive, non-volatile memory such as non-volatile random access memory (NVRAM), a removable flash drive or other removable medium, other types of random access memory, and the like. The software stored on the non-transitory computer readable storage medium may be executed by processing circuitry (e.g., processing circuitry in wireless communication circuitry 24, processing circuitry 18 of fig. 1, etc.) on one or more of the components of device 10. The processing circuitry may include a microprocessor, an application processor, a digital signal processor, a Central Processing Unit (CPU), an application specific integrated circuit with processing circuitry, or other processing circuitry.

For one or more aspects, at least one of the components set forth in one or more of the preceding figures may be configured to perform one or more operations, techniques, procedures, or methods set forth in the following embodiments section.

Examples

In the following sections, further exemplary aspects are provided.

Embodiment 1 includes an amplifier circuit comprising a first path, a first amplifier located on the first path, a first transformer located on the first path and operably coupled to the first amplifier, a second path, a second amplifier located on the second path, and a second transformer located on the second path and operably coupled to the second amplifier, wherein the second transformer overlaps the first transformer and is orthogonal to the first transformer.

Embodiment 2 includes the amplifier circuit of embodiment 1, wherein the first transformer optionally includes a first winding and a second winding characterized by a first coupling coefficient, and the second transformer optionally includes a third winding and a fourth winding characterized by a second coupling coefficient.

Embodiment 3 includes the amplifier circuit of embodiment 2, wherein the first winding optionally exhibits a first additional coupling coefficient with the third winding and the fourth winding, the first additional coupling coefficient being less than the first coupling coefficient and the second coupling coefficient, and the second winding optionally exhibits a second additional coupling coefficient with the third winding and the fourth winding, the second additional coupling coefficient being less than the first coupling coefficient and the second coupling coefficient.

Embodiment 4 includes the amplifier circuit of embodiment 2, further optionally comprising a substrate, wherein the first winding optionally includes a first conductive trace on the substrate and extending around a central opening, and the second winding optionally includes a second conductive trace on the substrate, overlapping the first conductive trace, and extending around the central opening.

Embodiment 5 includes the amplifier circuit of embodiment 4 wherein the third winding optionally includes a third conductive trace on the substrate, the third conductive trace optionally including a crossover overlapping the central opening, and the third conductive trace extending around the first and second openings overlapping the central opening.

Embodiment 6 includes the amplifier circuit of embodiment 5 wherein the fourth winding optionally includes a fourth conductive trace on the substrate and overlapping the third conductive trace, the fourth conductive trace optionally including an additional crossover overlapping the crossover of the third conductive trace, and the fourth conductive trace optionally extending around the first and second openings.

Embodiment 7 includes the amplifier circuit of embodiment 6, wherein the first conductive trace optionally laterally surrounds the third conductive trace on the first layer of the substrate.

Embodiment 8 includes the amplifier circuit of embodiment 7, wherein the second conductive trace optionally laterally surrounds the fourth conductive trace on the second layer of the substrate.

Embodiment 9 includes the amplifier circuit of embodiment 6, further optionally comprising a signal splitter coupling an input signal path to the first path and the second path, wherein the signal splitter optionally comprises the first transformer and the second transformer.

Embodiment 10 includes the amplifier circuit of embodiment 6, further optionally comprising a signal combiner coupling the first path and the second path to an output signal path, wherein the signal combiner optionally comprises the first transformer and the second transformer.

Embodiment 11 includes the amplifier circuit of embodiment 10 wherein the first winding is optionally coupled to an output of the first amplifier, the third winding is optionally coupled to an output of the second amplifier, the second winding is optionally extended from a first terminal to a second terminal, the fourth winding is optionally extended from a third terminal to a fourth terminal, the first terminal is optionally coupled to a reference potential, the third terminal is optionally coupled to the reference potential, the second terminal is optionally coupled to the fourth terminal through a capacitor, and the second terminal is optionally coupled to the output signal path.

Embodiment 12 includes the amplifier circuit of embodiment 6, further optionally comprising a third amplifier on the first path, a fourth amplifier on the second path, and an inter-stage matching network on the first path and the second path, wherein the inter-stage matching network optionally comprises the first transformer and the second transformer, the first transformer is coupled between the first amplifier and the third amplifier, and the second transformer is coupled between the second amplifier and the fourth amplifier.

Embodiment 13 includes the amplifier circuit of embodiment 1 wherein the first path optionally includes a transmit path, the first amplifier optionally includes a power amplifier, the second path optionally includes a receive path, and the second amplifier optionally includes a low noise amplifier.

Embodiment 14 includes an amplifier circuit comprising a first amplifier, a second amplifier, a substrate, a first transformer operably coupled to an output of the first amplifier, and a second transformer operably coupled to an output of the second amplifier, wherein the first transformer comprises a first conductive trace on the substrate and extending laterally around a first opening on the substrate, the second transformer comprises a second conductive trace on the substrate, the second conductive trace comprises an intersection overlapping the first opening, and the second conductive trace extends laterally around a second opening and a third opening, the second opening and the third opening overlapping the first opening and being smaller than the first opening.

Embodiment 15 includes the amplifier circuit of embodiment 14, wherein the first conductive trace optionally has a magnetic coupling coefficient with the second conductive trace, the magnetic coupling coefficient being less than or equal to 0.1 across a frequency range of the amplifier circuit.

Embodiment 16 includes the amplifier circuit of embodiment 14, wherein the first transformer optionally includes a third conductive trace on the substrate that overlaps the first conductive trace and extends laterally around the first opening.

Embodiment 17 includes the amplifier circuit of embodiment 16, wherein the second transformer optionally includes a fourth conductive trace on the substrate overlapping the second conductive trace and extending laterally around the second and third openings, the fourth conductive trace having an additional crossover overlapping the crossover of the second conductive trace.

Embodiment 18 includes the amplifier circuit of embodiment 17, wherein the first conductive trace optionally laterally surrounds the second conductive trace on a first layer of the substrate, and wherein the third conductive trace optionally laterally surrounds the fourth conductive trace on a second layer of the substrate.

Embodiment 19 includes the amplifier circuit of embodiment 14 wherein the first conductive trace optionally extends from a first terminal to a second terminal, the second conductive trace optionally extends from a third terminal to a fourth terminal, the first terminal is coupled to a reference potential, the third terminal is coupled to the reference potential, the second terminal is coupled to the fourth terminal through a capacitor, and the second terminal is coupled to an output load of the amplifier circuit.

Embodiment 20 includes a wireless circuit comprising an antenna, and a power amplifier circuit communicatively coupled to the antenna and configured to transmit a radio frequency signal using the antenna, wherein the power amplifier circuit comprises a signal splitter, a signal combiner, a first path coupled between the signal splitter and the signal combiner and having a first amplifier, and a second path coupled in parallel with the first path between the signal splitter and the signal combiner and having a second amplifier, wherein the signal splitter comprises a first transformer communicatively coupled to an input of the first amplifier, the signal splitter comprises a second transformer communicatively coupled to an input of the second amplifier, the first transformer laterally surrounds the second transformer, and the first transformer is orthogonal to the second transformer.

Embodiment 21 includes a circuit. The circuit can include a substrate. The circuit can include a first transformer including a first primary winding formed from a first conductive trace on the substrate and including a first secondary winding formed from a second conductive trace on the substrate. The circuit can include a second transformer including a second primary winding formed from a third conductive trace on the substrate and including a second secondary winding formed from a fourth conductive trace on the substrate, wherein the second conductive trace overlaps the first conductive trace, the fourth conductive trace overlaps the third conductive trace, the first and second conductive traces laterally surround an opening on the substrate, the third and fourth conductive traces overlap the opening, and the third conductive trace includes a crossover.

Embodiment 22 includes the circuit of embodiment 21 wherein the fourth conductive trace optionally includes an additional crossover overlapping the crossover.

Embodiment 23 includes the circuit of embodiment 21, wherein the second conductive trace optionally has a first non-zero magnetic coupling coefficient with the first conductive trace and the fourth conductive trace has a second non-zero magnetic coupling coefficient with the third conductive trace.

Embodiment 24 includes the circuit of embodiment 23, wherein a first magnetic coupling coefficient between the first conductive trace and the third conductive trace is optionally equal to zero and a second magnetic coupling coefficient between the first conductive trace and the fourth conductive trace is equal to zero.

Embodiment 25 includes the circuit of embodiment 24, wherein a third magnetic coupling coefficient between the second conductive trace and the third conductive trace is optionally equal to zero, and a fourth magnetic coupling coefficient between the second conductive trace and the fourth conductive trace is equal to zero.

Embodiment 26 includes the circuit of embodiment 21, wherein the third and fourth conductive traces optionally laterally surround the first and second portions of the opening.

Embodiment 27 includes the circuit of embodiment 26, wherein the current flowing through the third and fourth conductive traces optionally generates a first magnetic field through the first portion of the opening and generates a second magnetic field opposite the first magnetic field and through the second portion of the opening.

Embodiment 28 includes the circuit of embodiment 27 wherein the additional current flowing through the first and second conductive traces optionally generates a third magnetic field parallel to the first magnetic field and passing through the first and second portions of the opening.

Embodiment 29 includes the circuit of embodiment 28 wherein the first conductive trace optionally extends between first input terminals of the first transformer, the third conductive trace optionally extends between second input terminals of the second transformer, and the circuit further optionally includes a first amplifier having a first output coupled to the first input terminals, and a second amplifier having a second output coupled to the second input terminals.

Embodiment 30 includes the circuit of embodiment 29, wherein the first transformer and the second transformer are optionally configured to form a signal combiner for the first amplifier and the second amplifier.

Embodiment 31 includes the circuit of embodiment 28 wherein the second conductive trace optionally extends between first output terminals of the first transformer, the fourth conductive trace optionally extends between second output terminals of the second transformer, and the circuit further optionally includes a first amplifier having a first input coupled to the first output terminals, and a second amplifier having a second input coupled to the second output terminals.

Embodiment 32 includes the circuit of embodiment 31 wherein the first transformer and the second transformer are optionally configured to form a signal splitter for the first amplifier and the second amplifier.

Embodiment 33 includes a wireless circuit comprising a first antenna, a second antenna, a first transmission path communicatively coupled to the first antenna, a second transmission path communicatively coupled to the second antenna, a first transformer positioned on the first transmission path, and a second transformer positioned on the second transmission path, wherein the first transformer laterally surrounds an opening, the second transformer overlaps the opening, the first transformer is configured to generate a first magnetic field through a first portion of the opening, and the second transformer is configured to generate a third magnetic field through a second portion of the opening, the third magnetic field being opposite the second magnetic field.

Embodiment 34 includes the wireless circuit of embodiment 33, wherein the third magnetic field and the second magnetic field are optionally of equal magnitude, the first transformer is optionally comprised of overlapping first and second conductive traces arranged in a circular pattern around the opening, and the second transformer is optionally comprised of overlapping third and fourth conductive traces in a figure-8 pattern within the opening.

Embodiment 35 includes the wireless circuit of embodiment 33, further optionally comprising a first power amplifier having a first input communicatively coupled to the output terminal of the first transformer, and a second power amplifier having a second input communicatively coupled to the output terminal of the second transformer.

Embodiment 36 includes the wireless circuit of embodiment 36, further optionally comprising a first power amplifier having a first output communicatively coupled to an input terminal of the first transformer, and a second power amplifier having a second output communicatively coupled to an input terminal of the second transformer.

Embodiment 37 includes a wireless circuit comprising a first antenna, a second antenna, a transmit path communicatively coupled to the first antenna, a receive path communicatively coupled to the second antenna, a first transformer positioned on the transmit path, and a second transformer positioned on the receive path, wherein the first transformer laterally surrounds the second transformer, the first transformer configured to generate a first magnetic field across the second transformer, and the second transformer configured to generate a second magnetic field across a first portion of the first transformer and configured to generate a third magnetic field across a second portion of the first transformer, the third magnetic field being opposite the second magnetic field.

Embodiment 38 includes the wireless circuit of embodiment 37, wherein the third magnetic field and the second magnetic field are optionally of equal magnitude, the first transformer optionally includes overlapping first and second conductive traces arranged in a circular pattern around the opening, and the second transformer optionally includes overlapping third and fourth conductive traces in a figure-8 pattern within the opening.

Embodiment 39 includes the wireless circuit of embodiment 37, further optionally comprising a power amplifier having an input communicatively coupled to the output terminal of the first transformer, and a low noise amplifier having an output communicatively coupled to the input terminal of the second transformer.

Embodiment 40 includes the wireless circuit of embodiment 37, further optionally comprising a power amplifier having an output communicatively coupled to the input terminal of the first transformer, and a low noise amplifier having an input communicatively coupled to the output terminal of the second transformer.

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The foregoing is illustrative and various modifications may be made to the described embodiments. The foregoing embodiments may be implemented alone or in any combination.

Claims (20)

1. An amplifier circuit, comprising:

A first path;

A first amplifier, the first amplifier being located on the first path;

the first transformer is provided with a first voltage transformer, the first transformer is located on the first path and is operably coupled to the first amplifier;

A second path;

A second amplifier located on the second path, and

A second transformer located on the second path and operably coupled to the second amplifier, wherein

The second transformer overlaps the first transformer, and

The second transformer is orthogonal to the first transformer.

2. The amplifier circuit of claim 1, wherein the first transformer comprises a first winding and a second winding, the first winding and the second winding characterized by a first coupling coefficient, and the second transformer comprises a third winding and a fourth winding, the third winding and the fourth winding characterized by a second coupling coefficient.

3. The amplifier circuit of claim 2, wherein the first winding exhibits a first additional coupling coefficient with the third winding and the fourth winding, the first additional coupling coefficient being less than the first coupling coefficient and the second coupling coefficient, and the second winding exhibits a second additional coupling coefficient with the third winding and the fourth winding, the second additional coupling coefficient being less than the first coupling coefficient and the second coupling coefficient.

4. The amplifier circuit of claim 2, further comprising:

a substrate, wherein

The first winding includes a first conductive trace on the substrate and extending around a central opening, an

The second winding includes a second conductive trace located on the substrate overlapping the first conductive trace and extending around the central opening.

5. The amplifier circuit of claim 4 wherein:

The third winding includes a third conductive trace on the substrate,

The third conductive trace includes an intersection overlapping the central opening, and the third conductive trace extends around the first and second openings overlapping the central opening.

6. The amplifier circuit of claim 5, wherein:

The fourth winding includes a fourth conductive trace on the substrate and overlapping the third conductive trace,

The fourth conductive trace includes an additional crossover overlapping the crossover of the third conductive trace, an

The fourth conductive trace extends around the first opening and the second opening.

7. The amplifier circuit of claim 6, wherein the first conductive trace laterally surrounds the third conductive trace on a first layer of the substrate.

8. The amplifier circuit of claim 7, wherein the second conductive trace laterally surrounds the fourth conductive trace on a second layer of the substrate.

9. The amplifier circuit of claim 6, further comprising:

A signal splitter coupling an input signal path to the first path and the second path, wherein the signal splitter includes the first transformer and the second transformer.

10. The amplifier circuit of claim 6, further comprising:

A signal combiner coupling the first path and the second path to an output signal path, wherein the signal combiner includes the first transformer and the second transformer.

11. The amplifier circuit of claim 10, wherein:

The first winding is coupled to the output of the first amplifier,

The third winding is coupled to the output of the second amplifier,

The second winding extends from a first terminal to a second terminal,

The fourth winding extends from a third terminal to a fourth terminal,

The first terminal is coupled to a reference potential,

The third terminal is coupled to the reference potential,

The second terminal is coupled to the fourth terminal through a capacitor, and

The second terminal is coupled to the output signal path.

12. The amplifier circuit of claim 6, further comprising:

a third amplifier, the third amplifier being located on the first path;

A fourth amplifier, the fourth amplifier being located on the second path; and

An inter-stage matching network located on the first path and the second path, wherein

The inter-stage matching circuit includes the first transformer and the second transformer, the first transformer is coupled between the first amplifier and the third amplifier, and

The second transformer is coupled between the second amplifier and the fourth amplifier.

13. The amplifier circuit of claim 1, wherein the first path comprises a transmit path, the first amplifier comprises a power amplifier, the second path comprises a receive path, and the second amplifier comprises a low noise amplifier.

14. An amplifier circuit, comprising:

a first amplifier;

a second amplifier;

A substrate;

A first transformer operably coupled to an output of the first amplifier, and

A second transformer operably coupled to an output of the second amplifier, wherein

The first transformer includes a first conductive trace on the substrate and extending laterally around a first opening on the substrate,

The second transformer includes a second conductive trace on the substrate,

The second conductive trace includes an intersection overlapping the first opening, and

The second conductive trace extends laterally around a second opening and a third opening that overlap and are smaller than the first opening.

15. The amplifier circuit of claim 14, wherein the first conductive trace has a magnetic coupling coefficient with the second conductive trace that is less than or equal to 0.1 across a frequency range of the amplifier circuit.

16. The amplifier circuit of claim 14, wherein the first transformer includes a third conductive trace on the substrate that overlaps the first conductive trace and extends laterally around the first opening.

17. The amplifier circuit of claim 16, wherein the second transformer includes a fourth conductive trace on the substrate overlapping the second conductive trace and extending laterally around the second opening and the third opening, the fourth conductive trace having an additional crossover overlapping the crossover of the second conductive trace.

18. The amplifier circuit of claim 17, wherein the first conductive trace laterally surrounds the second conductive trace on a first layer of the substrate, and wherein the third conductive trace laterally surrounds the fourth conductive trace on a second layer of the substrate.

19. The amplifier circuit of claim 14, wherein:

the first conductive trace extends from a first terminal to a second terminal,

The second conductive trace extends from a third terminal to a fourth terminal,

The first terminal is coupled to a reference potential,

The third terminal is coupled to the reference potential,

The second terminal is coupled to the fourth terminal through a capacitor, and

The second terminal is coupled to an output load of the amplifier circuit.

20. A wireless circuit, comprising:

Antenna, and

A power amplifier circuit communicatively coupled to the antenna and configured to transmit a radio frequency signal using the antenna, wherein the power amplifier circuit comprises

A signal splitter which is provided with a plurality of signal splitters,

The signal combiner is provided with a signal processing unit,

A first path coupled between the signal splitter and the signal combiner and having a first amplifier, an

A second path coupled in parallel with the first path between the signal splitter and the signal combiner and having a second amplifier, wherein

The signal splitter includes a first transformer communicatively coupled to an input of the first amplifier,

The signal splitter includes a second transformer communicatively coupled to an input of the second amplifier,

The first transformer laterally surrounds the second transformer, and the first transformer is orthogonal to the second transformer.