CN121029106B - Data writing methods, systems, electronic devices, storage media, and program products - Google Patents

Data writing methods, systems, electronic devices, storage media, and program products

Info

Publication number
CN121029106B
CN121029106B CN202511580967.6A CN202511580967A CN121029106B CN 121029106 B CN121029106 B CN 121029106B CN 202511580967 A CN202511580967 A CN 202511580967A CN 121029106 B CN121029106 B CN 121029106B
Authority
CN
China
Prior art keywords
data
target
cache
area
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202511580967.6A
Other languages
Chinese (zh)
Other versions
CN121029106A (en
Inventor
殷军博
宗岗岗
吕玉彬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Metabrain Intelligent Technology Co Ltd
Original Assignee
Suzhou Metabrain Intelligent Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Metabrain Intelligent Technology Co Ltd filed Critical Suzhou Metabrain Intelligent Technology Co Ltd
Priority to CN202511580967.6A priority Critical patent/CN121029106B/en
Publication of CN121029106A publication Critical patent/CN121029106A/en
Application granted granted Critical
Publication of CN121029106B publication Critical patent/CN121029106B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The application discloses a data writing method, a system, electronic equipment, a storage medium and a program product, which relate to the technical field of computers and comprise the following steps: when a write request is received, it is checked whether a target logical address exists in the cache area, if so, old data (i.e., first data) already exists in the cache area, and at this time, the original first data in the cache area is replaced with the target data. The replacement operation occurs at the cache layer, so that the data to be written in the flash memory area cached in the cache area is ensured to be new data (namely target data), the occupation of the cache space by invalid old data is avoided, and the invalid data occupies write resources when being written in the flash memory area, so that the write delay of the valid data is increased.

Description

Data writing method, system, electronic device, storage medium and program product
Technical Field
The present application relates to the field of computer technologies, and in particular, to a data writing method, system, electronic device, storage medium, and program product.
Background
The writing process of the conventional Solid state disk (Solid STATE DRIVE, abbreviated as SSD) is mainly based on a "cache-aggregation-flush" mode, so as to cope with the problem of speed mismatch between the host and the NAND gate memory (Not AND gate Memory Device, abbreviated as NAND) flash memory. Specifically, when the host sends a write request to the SSD, the SSD controller first temporarily stores the data in an internal double data Rate random Access memory (Double Data Rate Random Access Memory, DDR) cache. However, for repeated logic address (Logical Block Addressing, LBA) writing requests, the conventional SSD controller keeps old data in the DDR cache, and writes the old and new data into the NAND flash memory together in a subsequent flushing operation, so that the writing of invalid data occupies the bandwidth of the NAND flash memory and the processing resources of the SSD controller, and there is a technical problem that data cannot be written efficiently.
Disclosure of Invention
The application provides a data writing method, a system, electronic equipment, a storage medium and a program product, which at least solve the technical problem that data cannot be written efficiently in the related technology, and achieve the technical effect of writing data efficiently.
The application provides a data writing method, which comprises the steps of receiving a writing request, wherein the writing request is used for requesting to write target data into a flash memory area included in a solid state disk, determining whether first data exist in a buffer area included in the solid state disk or not based on a target logical address of the target data in the solid state disk, wherein the buffer area is used for buffering data to be written into the flash memory area, the first logical address of the first data in the solid state disk is identical to the target logical address, replacing the first data buffered in the buffer area with the target data when the first data exist in the buffer area, and calling a target central processing unit to write the data buffered in the buffer area into the flash memory area when the target data amount of the data buffered in the buffer area meets a preset condition, wherein the data buffered in the buffer area comprise the target data.
The application further provides a controller, which comprises a receiving module, a determining module and a calling module, wherein the receiving module is used for receiving a writing request, the writing request is used for requesting to write target data into a flash memory area included in a solid state disk, the determining module is used for determining whether first data exist in a cache area included in the solid state disk or not based on a target logic address of the target data in the solid state disk, the cache area is used for caching data to be written into the flash memory area, the first logic address of the first data in the solid state disk is identical to the target logic address, the substituting module is used for substituting the first data cached in the cache area with the target data when the first data exist in the cache area, and the calling module is used for calling a target central processing unit to write the data cached in the cache area into the flash memory area when the target data amount of the data cached in the cache area meets preset conditions, and the data cached in the cache area comprises the target data.
The application also provides a data writing system, which comprises a controller and the solid state disk.
The application also provides electronic equipment, which comprises a memory and a processor, wherein the memory is used for storing a computer program, and the processor is used for realizing the steps of the execution method of any task when executing the computer program.
The application also provides a computer readable storage medium, in which a computer program is stored, wherein the computer program when executed by a processor implements the steps of the execution method of any of the tasks described above.
The application also provides a computer program product comprising a computer program which when executed by a processor performs the steps of the execution method of any of the tasks described above.
According to the application, when a write-in request is received, whether the target logical address exists in the cache area is checked, if so, the target logical address is indicated to have old data (namely first data) resident in the cache area, and at the moment, the original first data in the cache area is replaced by the target data. The replacement operation occurs at the cache layer, so that the data to be written in the flash memory area cached in the cache area is ensured to be new data (namely target data), the occupation of the cache space by invalid old data is avoided, and the invalid data occupies write resources when being written in the flash memory area, so that the write delay of effective data is increased.
Drawings
For a clearer description of embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a hardware block diagram of a mobile terminal according to a data writing method provided by an embodiment of the present application;
FIG. 2 is a flow chart of a method for writing data according to an embodiment of the application;
FIG. 3 is a flow chart of a method for writing data according to an embodiment of the application;
fig. 4 is a schematic structural diagram of a controller according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present application.
It should be noted that in the description of the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "first," "second," and the like in this specification are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The present application will be further described in detail below with reference to the drawings and detailed description for the purpose of enabling those skilled in the art to better understand the aspects of the present application.
The specific application environment architecture or specific hardware architecture upon which execution of a method of writing data depends is described herein in connection with the specific application environment architecture or specific hardware architecture.
The method embodiments provided in the embodiments of the present application may be performed in an SSD controller, a CPU in the SSD controller, or similar computing devices. Taking an example of running on an SSD controller, fig. 1 is a block diagram of a hardware structure of a mobile terminal according to an embodiment of the present application. As shown in fig. 1, the SSD controller may include one or more central processing units (Central Processing Unit, abbreviated as CPU), where the SSD controller interacts with the host through peripheral component interconnect extensions (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, abbreviated as PCIE) or serial advanced technology attachment (SERIAL ADVANCED Technology Attachment, abbreviated as SATA) or serial attached small Computer system interface (SERIAL ATTACHED SMALL Computer SYSTEM INTERFACE, abbreviated as SAS) or universal flash storage (Universal Flash Storage, abbreviated as UFS), and the SSD controller interacts with one or more NAND. It will be appreciated by those skilled in the art that the structure shown in fig. 1 is merely illustrative, and is not limited to the above-described structure of the solid state disk controller. For example, the solid state disk controller may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
An embodiment of the present application provides a data writing method, and fig. 2 is a flowchart of a data writing method according to an embodiment of the present application, as shown in fig. 2, where the flowchart includes the following steps:
step S202, receiving a write request, where the write request is used to request to write target data into a flash memory area included in the solid state disk.
Alternatively, in a computer storage system, a write request refers to an instruction sent from a host (e.g., server, personal computer) to a storage device (e.g., SSD) requesting the storage device to write specific data to its storage medium. Specifically, when an application program or an operating system of the host needs to store target data in the SSD, the host generates a write request, where the write request may include information such as the target data itself, a target logical address, and a data length.
Optionally, the target data is data to be written in the write request.
Alternatively, an SSD is a storage device that uses non-volatile memory (e.g., NAND flash memory) to store data.
Alternatively, in the SSD, the NAND flash memory is organized into a plurality of blocks (blocks), each Block being composed of a plurality of pages (pages). The flash memory area refers to a specific portion of the NAND flash memory in the SSD, and may be a block, a page, or multiple blocks, or multiple pages.
Step S204, determining whether first data exists in a buffer area included in the solid state disk based on a target logical address of the target data in the solid state disk, wherein the buffer area is used for buffering data to be written in the flash memory area, and the first logical address of the first data in the solid state disk is the same as the target logical address.
Alternatively, the target logical address is a logical address required to write target data in a write request sent by the host, and is an address used by the host to access the SSD. Inside the SSD, the LBA and the physical address (Physical Block Addressing, abbreviated as PBA) are mapped through a flash memory conversion layer (Flash Translation Layer, abbreviated as FTL), and the corresponding data is acquired from the LBA-PBA mapping relation in the FTL by a subsequent host read command, wherein the same LBA corresponds to the same PBA in the mapping relation.
Optionally, the buffer area is located in a DDR buffer of the SSD, and is used to buffer data to be written into the NAND flash memory.
Optionally, when an application program or an operating system of the host needs to store the first data in the SSD, the host generates a write request, where the write request may include information such as the first data itself, the first logical address, and the data length. The first data is data which is cached in the cache area and has the first logical address which is the same as the target logical address, wherein the first logical address is a logical address which is required to be written into the first data in a write request sent by the host, and is an address used by the host for accessing the SSD.
Step S206, when the first data exists in the buffer area, replacing the first data buffered in the buffer area with the target data.
Step S208, when the target data amount of the data cached in the cache area meets a preset condition, the target CPU is called to write the data cached in the cache area into the flash memory area, wherein the data cached in the cache area comprises the target data.
Optionally, the target central processor is responsible for managing the data of the cache area and the writing process of the NAND flash memory. For example, when the data in the buffer area reaches a preset condition, the SSD controller may call a target CPU in the CPU therein to execute an instruction for data flushing, and write the data in the buffer into the NAND flash memory.
The execution subject of the steps described above in this embodiment may be a processor of a hardware class or a software class, a proxy device, a management device, or the like. The implementation manner of the above steps may also be a specific processor provided in a terminal, a server, a terminal or a server, or a processor or a processing device provided separately from the terminal or the server, but is not limited thereto.
According to the embodiment of the application, when a write-in request is received, whether the target logical address exists in the cache area is checked, if so, the target logical address is indicated to have old data (namely first data) resident in the cache area, and at the moment, the original first data in the cache area is replaced by the target data. The replacement operation occurs at the cache layer, so that the data to be written in the flash memory area cached in the cache area is ensured to be new data (namely target data), the occupation of the cache space by invalid old data is avoided, and the invalid data occupies write resources when being written in the flash memory area, so that the write delay of effective data is increased.
In an exemplary embodiment, determining whether first data exists in the buffer area included in the solid state disk based on the target logical address of the target data in the solid state disk includes analyzing the write request to obtain an analysis result, determining the target logical address included in the analysis result, and determining whether the first data is cached in the buffer area based on the target logical address and a first index table, where the first index table is used for recording address information of data to be written in the flash memory area cached in the buffer area.
Optionally, when an application program or an operating system of the host needs to save data to the SSD, the host generates a write request, where the write request includes, but is not limited to, information such as the data itself, the LBA, and the data length, and parsing the write request may determine a target logical address included in the write request, where the first data and the target data originate from the same application program or from the same operating system in the host, for example, the first data and the target data are both updated data of the application program a in the host.
Optionally, the address information recorded by the first index table includes, but is not limited to, LBA, static random access memory (Static Random Access Memory, abbreviated as SRAM) cache address, dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) cache address. The first index table may be implemented using a hash table, a linked list, or other efficient data access structure. For example, the first index table adopts a data structure of a hash chain table bucket, supports query efficiency of an O (1) level, allows quick query of whether the data exist or not and the position of the data based on the LBA, ensures that no significant delay is introduced in LBA hit detection, wherein the first index table takes the LBA as a Key (Key) of the hash table, ensures that each LBA corresponds to a unique index entry in the first index table, each index entry comprises a 4k data cache item context data structure pointer, each index entry comprises the LBA, an SRAM cache address and a DRAM cache address, each bucket bit of the hash table serves as a chain table head, the conflicting index entries are sequentially mounted in a node form, the node comprises address information and a next-hop pointer, and meanwhile, the hash chain table bucket depth is set to be the maximum chain table length.
According to the embodiment, the first index table is maintained, so that the space of the cache area can be effectively managed, specific data in the cache area can be rapidly located, blind searching of the whole cache space is avoided, and the purpose of rapidly determining whether the first data is cached in the cache area is achieved.
In one exemplary embodiment, determining whether the first data is cached in the cache area based on the target logical address and a first index table includes determining the target central processing unit from a plurality of central processing units included in the solid state disk based on the target logical address, acquiring the first index table stored in the target central processing unit, and determining whether the first data is cached in the cache area based on the target logical address and the acquired first index table.
Alternatively, the first index table is a data structure maintained by the SSD controller in the DDR cache, where in a high performance SSD the SSD controller may contain multiple CPU cores, each of which is responsible for handling different tasks, each of which may have a separate first index table, which may determine which core to execute the write request based on the logical address in the write request. For example, a SSD controller has 4 cores, each of which manages writing and reading operations of a part of data in a buffer area, respectively, so as to implement parallel processing and increase the data processing speed.
According to the embodiment, each CPU is provided with the independent first index table in the SSD with the multi-core processor, the purpose of writing data cached in the cache area into the flash memory area in parallel is achieved, meanwhile, the target central processing unit can ensure that the same LBA can be processed on one CPU based on the target LBA, and the purpose of avoiding write request processing conflict is achieved.
In an exemplary embodiment, determining the target central processing unit from the plurality of central processing units included in the solid state disk based on the target logical address includes determining the target central processing unit based on a character of a preset bit position in the target logical address, where an identifier of the target central processing unit and the character of the preset bit position conform to a preset association relationship.
In one exemplary embodiment, determining the target central processor based on the character of the preset bit position in the target logical address includes determining a target binary character of the preset bit position in the target logical address, determining a target decimal identification associated with the target binary character from the preset association, and determining a central processor included in the plurality of central processors as the target decimal identification as the target central processor.
Alternatively, in determining the destination cpu, the SSD controller checks the value of a specific bit field (preset bit position) in the destination logical address, which is called a "character". The values of these bit fields can be used to determine which CPU should be responsible for handling write requests for the corresponding LBA. For example, if bit6 and bit7 of the LBA are preset as bit positions, the bit6 and bit7 field values of lba=512 (binary representation 00000001000000000) are 10 (binary), and the corresponding "character" value is 2.
Optionally, the preset association relationship is preset in the SSD controller, and is a mapping relationship between characters of a preset bit position in the LBA and the identifier of the CPU. For example, the preset association may indicate that the value 00 of bit6 and bit7 corresponds to CPU0,01 corresponds to CPU1,10 corresponds to CPU2,11 corresponds to CPU3, thus establishing a mapping from the character at a specific bit position in the LBA to the CPU core identifier.
The present embodiment can quickly determine which CPU is responsible for processing the data of a specific LBA by directly mapping the value of the specific bit in the LBA to the identity of the CPU.
In one exemplary embodiment, determining whether the first data is cached in the cache area based on the target logical address and a first index table includes one of determining that the first data is cached in the cache area when the first logical address identical to the target logical address is recorded in the first index table, and determining that the first data is not cached in the cache area when the first logical address identical to the target logical address is not recorded in the first index table.
In this embodiment, by checking whether the first data with the same logical address as the target data exists in the buffer area, writing of both new and old data into the NAND flash memory can be avoided, the write amplification factor is significantly reduced, meanwhile, the number of invalid erasing times of the NAND flash memory is reduced, the service life of the SSD is prolonged, and in particular, for a four-layer unit (Quadruple LEVEL CELL, abbreviated as QLC) flash memory with limited erasing times.
In an exemplary embodiment, after parsing the write request to obtain a parsing result, the method further includes determining a data length of the target data included in the parsing result, determining a target cache address of the target data in the cache area based on the data length, caching the target data in an area indicated by the target cache address, and recording target address information of the target data in the first index table, wherein the target address information includes the target logical address and the target cache address.
Alternatively, the data length of the target data is the size of the target data, for example, the data length that the host requires to write may be 4KB or 64KB.
Optionally, inside the SSD, the DDR cache is a temporary storage area prior to data writing to the NAND, where the DDR cache includes, but is not limited to, SRAM cache and DRAM cache. The target cache address is a storage location allocated to the target data in the DDR cache. For example, if there is a free area in the DDR cache starting from 0x1000, then the target data may be allocated in the address interval of 0x1000 to 0x1001000, the target cache address is 0x1000, or the target cache address is 0x1000 to 0x10FF.
According to the embodiment, the size of the target data is determined according to the analysis result, the buffer memory space is allocated according to the need, and the waste of buffer memory resources is avoided. And simultaneously, the logical address and the target cache address of the target data are recorded in the first index table in time, so that the possibility of replacing the data in the repeated writing scene is provided.
In an exemplary embodiment, replacing the first data cached in the cache area with the target data includes determining a first cache address corresponding to the first logical address based on a correspondence between the logical address recorded in the first index table and the cache address when the first data is cached in the cache area, and deleting the first data cached in the area indicated by the first cache address.
Optionally, the function of the correspondence between the logical address and the cache address recorded in the first index table is to determine a cache location of the data in the cache area, and a write request corresponding to the data, where the correspondence may be a one-to-one correspondence, for example, the write request a includes data a, the logical address a, the cache address of the data a in the cache area is the cache address a, and the data a-logical address a-cache address a is recorded in the first index table.
Optionally, the target data is cached in the cache area first, so that at least one backup of the target data is ensured. The strategy can protect target data under emergency conditions (such as power failure) and avoid the loss of updated information due to accidents at the moment of deleting the first data. Meanwhile, the target data is cached in the cache area, so that the writing request of the host can be responded immediately, and the user experience is improved.
In this embodiment, the corresponding relationship between the LBA and the cache address is recorded in the first index table, so that the SSD controller can detect the repeated write request in real time, and avoid writing the old data into the NAND flash memory, thereby significantly reducing the write amplification factor and reducing the NAND erasing times. Meanwhile, old data in the cache are replaced in real time, so that waste of cache space is avoided. After deleting the old data, the released cache space can be used for storing new data, and efficient utilization of the cache area is ensured. And by directly replacing data in the cache, the NAND flash memory is prevented from being frequently accessed.
In one exemplary embodiment, replacing the first data cached in the cache area with the target data includes determining a first cache address corresponding to the first logical address based on a correspondence between logical addresses recorded in the first index table and cache addresses, deleting the first data cached in an area indicated by the first cache address, determining a data length of the target data included in the analysis result, determining a target cache address of the target data in the cache area based on the data length, caching the target data in the area indicated by the target cache address, and recording target address information of the target data in the first index table, wherein the target address information includes the target logical address and the target cache address.
According to the embodiment, the first data is deleted first, so that the buffer space can be released immediately, the target data can be directly written into the idle buffer area, the temporary occupation of the buffer space is avoided, and the utilization efficiency of the buffer space is improved. And meanwhile, the first data is deleted firstly, so that the complexity of simultaneously managing the target data and the first data in the cache is reduced. And the first data is deleted and the target data is rewritten, so that only one version of data exists in the cache area at any time, and the consistency and accuracy of the data are enhanced.
In an exemplary embodiment, after deleting the first data cached in the area indicated by the first cache address, the method further includes deleting first address information of the first data recorded in the first index table, where the first address information includes the first logical address and the first cache address, and updating an amount of data cached in the cache area.
Optionally, the amount of data buffered in the buffer area refers to the total size of data currently buffered in the DDR buffer. For example, if there are 5 data blocks in the DDR cache, each of which is 4KB, then the amount of data cached in the cache area is 20KB.
In an exemplary embodiment, after the target address information of the target data is recorded in the first index table, the method further includes updating the amount of data buffered in the buffer area if the first data is not present in the buffer area.
According to the embodiment, the consistency of the first index table and the cache condition in the cache area is ensured by updating the address information in the first index table and the data quantity cached in the cache area, so that the problems of data conflict and inconsistency are avoided.
In one exemplary embodiment, when the target data amount of the data cached in the cache area meets a preset condition, the method comprises the steps of enabling the target central processing unit to write the data cached in the cache area into the flash area, determining a writing threshold value based on a bad block table, wherein the bad block table is used for recording a first storage area with abnormal states included in the flash area, and enabling the target central processing unit to write the data cached in the cache area into a second storage area with normal states included in the flash area when the target data amount reaches the writing threshold value.
Alternatively, the bad block table is a Bitmap table maintained in the SSD, and records the status of data blocks (i.e., bad blocks) that cannot be read and written normally in the flash area, where the bad blocks may be caused by physical defects or excessive erasure of the flash area. When the target data amount reaches or exceeds the write threshold, a flushing operation of the data from the cache area to the delete area will be automatically performed.
Alternatively, the first storage area of the status exception is a data block marked as "status exception" in the flash memory area, typically a bad block that cannot be read or has significantly degraded read/write performance. The second storage area with normal state is a healthy storage block which is not marked as abnormal state and can be read and written normally in the flash memory area, and is a preferred target of data refreshing.
According to the embodiment, the writing threshold ensures that the data to be written is written into the flash memory area only when the data volume of the cache area reaches enough aggregation, so that unnecessary data writing is avoided, the access frequency of the flash memory area is reduced, and the energy consumption of the SSD is reduced.
In an exemplary embodiment, determining the write threshold based on the bad block table includes determining the second storage area based on the first storage area recorded in the bad block table, and determining the write threshold based on a remaining storage space of the second storage area.
Optionally, determining the write threshold based on the remaining storage space of the second storage area includes determining a storage capacity of the remaining storage space and determining the write threshold based on the storage capacity. For example, the storage area of the flash memory includes eight storage blocks, two bad blocks are included, the bad block table is 00100001b, then the write threshold is (8-2) ×4df×4pages=96 pieces of 4k data, DF (i.e., DATA FRAME data frame) is the number of pieces of 4k data included in 16k pages, and pages is the number of pieces of 16k data included in one WL (i.e., world Line) in the QLC.
In an exemplary embodiment, after the target data amount of the data buffered in the buffer area satisfies a preset condition, invoking the target central processing unit to write the data buffered in the buffer area into the flash memory area, the method further includes deleting the data buffered in the buffer area and written into the flash memory area, deleting address information of the data written into the flash memory area recorded in the first index table, updating the data amount buffered in the buffer area, and updating a second index table, wherein the second index table is used for recording a correspondence relationship between a logical address of the data written into the flash memory area and a physical address in the flash memory area.
Optionally, when the target data amount of the data buffered in the buffer area meets a preset condition, the method further includes deleting address information of the data to be written in the flash memory area recorded in the first index table before the target central processing unit is called to write the data buffered in the buffer area into the flash memory area. When the target data amount of the data cached in the cache area meets the preset condition, the target CPU is called to write the data cached in the cache area into the flash memory area, and the method further comprises the steps of deleting the data cached in the cache area and written into the flash memory area, updating the data amount cached in the cache area, and updating a second index table, wherein the second index table is used for recording the corresponding relation between the logical address of the data written into the flash memory area in the solid state disk and the physical address of the data written into the flash memory area. In order to avoid the problem of data consistency caused by data replacement during the writing and the searching efficiency under the conflict in the first index table, the address information of the data to be written in the flash memory area recorded in the first index table is deleted before the writing and the refreshing is started, and the index table resource is released.
Optionally, the second index table may be a logical-to-physical mapping table (Logical To Physical, abbreviated as L2P mapping table) for recording the correspondence between LBAs and PBAs of data in the SSD, during the life cycle of the SSD, the actual physical storage location of the data may change due to mechanisms such as garbage collection, wear leveling, etc., and the second index table ensures that the SSD can accurately find the storage location of the data even if the physical address changes.
Optionally, the PBA is the actual physical storage location of data in the flash memory area inside the SSD. The PBA is related to the physical layout of the flash memory area, which is the direct address for data storage and reading inside the SSD.
According to the embodiment, after the data is successfully written into the flash memory area, the written data in the cache area is deleted, so that the cache space is released, invalid data is prevented from occupying the cache space, meanwhile, after the data which is cached in the cache area and is written into the flash memory area is deleted, the cached data quantity in the cache area is updated, the accurate statistics of the cache service condition is kept, and the mapping from the LBA to the PBA is ensured to be up to date by updating the second index table by the SSD, so that the subsequent data reading and garbage recycling operation is facilitated.
The invention is illustrated below with reference to specific examples:
An embodiment of the present application provides a data writing method, and fig. 3 is a flowchart of a data writing method according to an embodiment of the present application, as shown in fig. 3, where the flowchart includes the following steps:
in step S302, the host sends a write request of target data to the SSD controller.
In step S304, the SSD controller analyzes the write request, and extracts information such as LBA and data length of the target data from the write request.
In step S306, the SSD controller applies for a plurality of 4K cache entry contexts from CACHE ENTRY FREE LIST (i.e. a cache entry free list) according to the data length, for storing information generated during the 4K processing. The buffer manager acceleration engine, which centrally manages the buffer allocation, allocates SRAM/DRAM cache addresses (i.e., target cache addresses) within the SSD while recording SRAM/DRAM into CACHE ENTRY.
In step S308, direct memory access (Direct Memory Access, abbreviated DMA) is then initiated to move the target data from the host side to the DRAM cache area.
In step S310, the logical block address index table (i.e., the first index table) is queried using the LBA of the extracted target data as a key in units of 4k, S312 is executed if there is no index entry (miss) of the LBA in the logical block address index table, and S318 is executed if there is an index entry (hit) of the LBA in the logical block address index table.
In step S312, the target data is written into the process.
In step S314, an index entry related to the address information of the target data is newly added to the logical block address index table, and specifically, a CACHE ENTRY node may be added to the writing context program entry list of the NAND flash memory.
In step S316, the data amount buffered in the DRAM buffer area is updated.
In step S318, the first buffer address of the first data is located.
In step S320, the first data is released in the buffer space of the DRAM, and CACHE ENTRY of the first data is deleted.
In step S322, the first cache address is updated to be the new address, and the first cache address is added in CACHE ENTRY FREE LIST.
In step S324, the data amount buffered in the DRAM buffer is updated.
In step S326, it is determined whether the amount of data buffered in the buffer area is equal to the writing threshold, if yes, S328 is executed, where the writing threshold may be determined based on the storage blocks in the flash memory area with normal status, for example, the storage area of the flash memory includes eight storage blocks, two bad blocks are in the storage area, and the bad block table is 00100001b, then the writing threshold is (8-2) ×4df×4pages=96 pieces of 4k data, DF is the number of 4k data included in 16k page, and pages is the number of 16k data included in one WL in QLC.
In step S328, deleting the logical address node of the data to be written in the logical block address index table, in order to avoid the problem of data consistency caused by data replacement during the writing and the searching efficiency under the conflict in the logical block address index table, deleting CACHE ENTRY items of the data to be written in the logical block address index table before the writing and the refreshing are started, and releasing the index table resources.
In step S330, the data to be written in the DRAM cache area is written into the NAND flash memory (i.e., flash memory area). Alternatively, step S328 may be performed after writing the NAND flash memory, that is, after writing the data to be written in the DRAM cache area into the NAND flash memory, deleting CACHE ENTRY entries in the index table.
In step S332, the written data is released in the buffer space of the DRAM after the completion of the writing.
In step S334, the L2P mapping table (i.e. the second index table) is updated to ensure that the subsequent read request of the host correctly hits the latest data.
In the repeated LBA writing scene, the embodiment can avoid old data from being written into the NAND flash memory, and the write amplification factor is reduced by 50% -80%. For example, in the high frequency repetitive writing scenarios such as database update and log rotation, the write amplification factor of the conventional scheme is usually 2-4, but the present embodiment can reduce it to 1.2-1.5, which is close to the theoretical optimal value. Meanwhile, the reduction of the write amplification coefficient directly reduces the invalid erasing times of the NAND flash memory, improves the bandwidth utilization rate of the NAND flash memory and reduces the SSD power consumption.
From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment.
The embodiment of the application also provides a controller, as shown in fig. 4, including:
A receiving module 402, configured to receive a write request, where the write request is used to request writing of target data into a flash memory area included in a solid state disk;
A determining module 404, configured to determine, based on a target logical address of the target data in the solid state disk, whether first data exists in a cache area included in the solid state disk, where the cache area is used to cache data to be written into the flash memory area, and the first logical address of the first data in the solid state disk is the same as the target logical address;
A replacing module 406, configured to replace, when the first data exists in the cache area, the first data cached in the cache area with the target data;
And a calling module 408, configured to call a target central processing unit to write the data cached in the cache area into the flash memory area when the target data amount of the data cached in the cache area meets a preset condition, where the data cached in the cache area includes the target data.
In an exemplary embodiment, the determining module 404 includes a first parsing sub-module configured to parse the write request to obtain a parsing result, a first determining sub-module configured to determine the target logical address included in the parsing result, and a second determining sub-module configured to determine, based on the target logical address and a first index table, whether the first data is cached in the cache area, where the first index table is configured to record address information of the data to be written in the flash memory area cached in the cache area.
In an exemplary embodiment, the second determining submodule includes a first determining unit configured to determine the target central processing unit from a plurality of central processing units included in the solid-state hard disk based on the target logical address, a first obtaining unit configured to obtain the first index table stored in the target central processing unit, and a second determining unit configured to determine whether the first data is cached in the cache area based on the target logical address and the obtained first index table.
In an exemplary embodiment, the first determining unit includes a first determining subunit, configured to determine, based on a character of a preset bit position in the target logical address, the target central processing unit, where an identifier of the target central processing unit and the character of the preset bit position conform to a preset association relationship.
In an exemplary embodiment, the first determining subunit includes a first determining slave subunit configured to determine a target binary character of a preset bit position in the target logical address, a second determining slave subunit configured to determine, from the preset association relationship, a target decimal identifier associated with the target binary character, and a third determining slave subunit configured to determine, as the target central processor, a central processor that is included in the plurality of central processors and is identified as the target decimal identifier.
In an exemplary embodiment, the second determining submodule includes one of a third determining unit configured to determine that the first data is cached in the cache area when the first logical address identical to the target logical address is recorded in the first index table, and a fourth determining unit configured to determine that the first data is not cached in the cache area when the first logical address identical to the target logical address is not recorded in the first index table.
In an exemplary embodiment, the determining module 404 further includes a third determining submodule configured to determine a data length of the target data included in the analysis result after analyzing the write request to obtain the analysis result, a fourth determining submodule configured to determine a target cache address of the target data in the cache area based on the data length, a first cache submodule configured to cache the target data in the area indicated by the target cache address, and a first recording submodule configured to record target address information of the target data in the first index table, where the target address information includes the target logical address and the target cache address.
In an exemplary embodiment, the replacing module 406 includes a fifth determining submodule configured to determine, when the first data is cached in the cache area, a first cache address corresponding to the first logical address based on a correspondence between the logical address and the cache address recorded in the first index table, and a first deleting submodule configured to delete the first data cached in the area indicated by the first cache address.
In one exemplary embodiment, the replacing module 406 includes a sixth determining submodule configured to determine a first cache address corresponding to the first logical address based on a correspondence between a logical address recorded in the first index table and a cache address, and delete the first data cached in an area indicated by the first cache address, and a seventh determining submodule configured to determine a data length of the target data included in the analysis result, determine a target cache address of the target data in the cache area based on the data length, cache the target data in the area indicated by the target cache address, and record target address information of the target data in the first index table, wherein the target address information includes the target logical address and the target cache address.
In an exemplary embodiment, the replacing module 406 further includes a first deleting sub-module configured to delete the first data cached in the area indicated by the first cache address, and then delete first address information of the first data recorded in the first index table, where the first address information includes the first logical address and the first cache address, and a first updating sub-module configured to update the data amount cached in the cache area.
In an exemplary embodiment, the determining module 404 further includes a second updating sub-module configured to update the amount of data buffered in the buffer area if the first data is not present in the buffer area.
In an exemplary embodiment, the invoking module 408 includes a first writing sub-module configured to determine a writing threshold based on a bad block table, where the bad block table is used to record a first storage area with abnormal status included in the flash memory area, and a second writing sub-module configured to invoke, when the target data amount reaches the writing threshold, the target central processing unit to write the data cached in the cache area into a second storage area with normal status included in the flash memory area.
In an exemplary embodiment, the first writing sub-module includes a fifth determining unit configured to determine the second storage area based on the first storage area recorded in the bad block table, and a sixth determining unit configured to determine the writing threshold based on a remaining storage space of the second storage area.
In one exemplary embodiment, the controller further includes a first deleting module configured to delete data written in the flash memory area cached in the cache area after the target central processing unit is called to write the data cached in the cache area into the flash memory area when the target data amount of the data cached in the cache area satisfies a preset condition, a second deleting module configured to delete address information of the data written in the flash memory area recorded in the first index table and update the data amount cached in the cache area, and a first updating module configured to update a second index table configured to record a correspondence relationship between a logical address of the data written in the flash memory area in the solid state disk and a physical address in the flash memory area.
The description of the features in the embodiment corresponding to the controller may refer to the related description of the embodiment corresponding to the execution method of the task, which is not described in detail herein.
The embodiment of the application also provides a data writing system which comprises a controller and the solid state disk.
In one exemplary embodiment, the system further comprises a plurality of central processing units, wherein the plurality of central processing units comprise target processors.
An embodiment of the application also provides an electronic device comprising a memory in which a computer program is stored and a processor arranged to run the computer program to perform the steps of the write method embodiment of any of the data described above.
An embodiment of the application also provides a computer readable storage medium having a computer program stored therein, wherein the computer program is configured to perform the steps of the writing method embodiment of any of the data described above when run.
In an exemplary embodiment, the computer readable storage medium may include, but is not limited to, a U disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, etc. various media in which a computer program may be stored.
Embodiments of the present application also provide a computer program product comprising a computer program which, when executed by a processor, implements the steps of the method embodiment of writing any of the data described above.
Embodiments of the present application also provide another computer program product comprising a non-volatile computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the write method embodiment of any of the above data.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The task execution method provided by the application is described in detail above. The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.

Claims (19)

1.一种数据的写入方法，其特征在于，包括：1. A method for writing data, characterized in that it includes: 接收写入请求，其中，所述写入请求用于请求将目标数据写入固态硬盘中包括的闪存区域中；Receive a write request, wherein the write request is used to request that target data be written to a flash memory area included in the solid-state drive; 基于所述目标数据在所述固态硬盘中的目标逻辑地址，确定所述固态硬盘中包括的缓存区域中是否存在第一数据，其中，所述缓存区域用于缓存待写入所述闪存区域中的数据，所述第一数据在所述固态硬盘中的第一逻辑地址与所述目标逻辑地址相同；Based on the target logical address of the target data in the solid-state drive, it is determined whether first data exists in the cache area included in the solid-state drive, wherein the cache area is used to cache data to be written to the flash memory area, and the first logical address of the first data in the solid-state drive is the same as the target logical address; 在所述缓存区域中存在所述第一数据的情况下，将所述缓存区域中缓存的所述第一数据替换为所述目标数据；If the first data exists in the cache area, the first data cached in the cache area will be replaced with the target data; 在所述缓存区域缓存的数据的目标数据量满足预设条件时，调用目标中央处理器将所述缓存区域缓存的数据写入至所述闪存区域中，其中，所述缓存区域缓存的数据中包括所述目标数据；When the target amount of data cached in the cache area meets a preset condition, the target central processing unit is invoked to write the data cached in the cache area to the flash memory area, wherein the data cached in the cache area includes the target data; 将所述缓存区域中缓存的所述第一数据替换为所述目标数据，包括：在所述缓存区域中缓存有所述第一数据的情况下，基于第一索引表中记录的逻辑地址与缓存地址的对应关系，确定与所述第一逻辑地址对应的第一缓存地址，并删除所述第一缓存地址所指示的区域中缓存的所述第一数据，其中，所述第一索引表用于记录所述缓存区域中缓存的待写入所述闪存区域中的数据的地址信息；确定解析结果中包括的所述目标数据的数据长度，基于所述数据长度，确定所述目标数据在所述缓存区域中的目标缓存地址，将所述目标数据缓存至所述目标缓存地址所指示的区域中，以及，在所述第一索引表中记录所述目标数据的目标地址信息，其中，所述目标地址信息包括所述目标逻辑地址以及所述目标缓存地址，所述解析结果是解析所述写入请求得到的。Replacing the first data cached in the cache region with the target data includes: when the first data is cached in the cache region, determining a first cache address corresponding to the first logical address based on the correspondence between logical addresses and cache addresses recorded in a first index table, and deleting the first data cached in the region indicated by the first cache address, wherein the first index table is used to record address information of data to be written to the flash memory region cached in the cache region; determining the data length of the target data included in the parsing result, determining the target cache address of the target data in the cache region based on the data length, caching the target data in the region indicated by the target cache address, and recording the target address information of the target data in the first index table, wherein the target address information includes the target logical address and the target cache address, and the parsing result is obtained by parsing the write request. 2.根据权利要求1所述的方法，其特征在于，基于所述目标数据在所述固态硬盘中的目标逻辑地址，确定所述固态硬盘中包括的所述缓存区域中是否存在第一数据，包括：2. The method according to claim 1, characterized in that, determining whether first data exists in the cache region included in the solid-state drive based on the target logical address of the target data in the solid-state drive includes: 确定所述解析结果中包括的所述目标逻辑地址；Determine the target logical address included in the parsing result; 基于所述目标逻辑地址和所述第一索引表，确定所述缓存区域中是否缓存有所述第一数据。Based on the target logical address and the first index table, determine whether the first data is cached in the cache area. 3.根据权利要求2所述的方法，其特征在于，基于所述目标逻辑地址和第一索引表，确定所述缓存区域中是否缓存有所述第一数据，包括：3. The method according to claim 2, characterized in that, determining whether the first data is cached in the cache region based on the target logical address and the first index table includes: 基于所述目标逻辑地址，从所述固态硬盘中包括的多个中央处理器中确定出所述目标中央处理器；Based on the target logical address, the target central processing unit is determined from the plurality of central processing units included in the solid-state drive; 获取所述目标中央处理器中存储的所述第一索引表；Obtain the first index table stored in the target central processing unit; 基于所述目标逻辑地址和获取的所述第一索引表，确定所述缓存区域中是否缓存有所述第一数据。Based on the target logical address and the obtained first index table, determine whether the first data is cached in the cache area. 4.根据权利要求3所述的方法，其特征在于，基于所述目标逻辑地址，从所述固态硬盘中包括的多个中央处理器中确定目标中央处理器，包括：4. The method according to claim 3, characterized in that, determining the target central processing unit from among the plurality of central processing units included in the solid-state drive based on the target logical address includes: 基于所述目标逻辑地址中预设比特位置的字符，确定所述目标中央处理器，其中，所述目标中央处理器的标识与所述预设比特位置的字符符合预设关联关系。The target central processing unit is determined based on the character at a preset bit position in the target logical address, wherein the identifier of the target central processing unit and the character at the preset bit position conform to a preset association relationship. 5.根据权利要求4所述的方法，其特征在于，基于所述目标逻辑地址中预设比特位置的字符，确定所述目标中央处理器包括：5. The method according to claim 4, characterized in that determining the target central processing unit based on the character at a preset bit position in the target logical address includes: 确定所述目标逻辑地址中预设比特位置的目标二进制字符；Determine the target binary character at a preset bit position in the target logical address; 从所述预设关联关系中确定出与所述目标二进制字符关联的目标十进制标识；The target decimal identifier associated with the target binary character is determined from the preset association relationship; 将所述多个中央处理器中包括的标识为所述目标十进制标识的中央处理器确定为所述目标中央处理器。The central processing unit (CPU) among the plurality of CPUs that is identified by the target decimal identifier is determined as the target CPU. 6.根据权利要求2所述的方法，其特征在于，基于所述目标逻辑地址和第一索引表，确定所述缓存区域中是否缓存有所述第一数据，包括以下之一：6. The method according to claim 2, characterized in that, determining whether the first data is cached in the cache region based on the target logical address and the first index table includes one of the following: 在所述第一索引表中记录有与所述目标逻辑地址相同的所述第一逻辑地址的情况下，确定所述缓存区域中缓存有所述第一数据；If the first logical address, which is the same as the target logical address, is recorded in the first index table, it is determined that the first data is cached in the cache area. 在所述第一索引表中未记录有与所述目标逻辑地址相同的所述第一逻辑地址的情况下，确定所述缓存区域中未缓存所述第一数据。If the first logical address that is the same as the target logical address is not recorded in the first index table, it is determined that the first data is not cached in the cache area. 7.根据权利要求2所述的方法，其特征在于，在解析所述写入请求，得到解析结果之后，所述方法还包括：7. The method according to claim 2, characterized in that, after parsing the write request and obtaining the parsing result, the method further includes: 确定所述解析结果中包括的所述目标数据的数据长度；Determine the data length of the target data included in the parsing result; 基于所述数据长度，确定所述目标数据在所述缓存区域中的目标缓存地址；Based on the data length, determine the target cache address of the target data in the cache area; 将所述目标数据缓存至所述目标缓存地址所指示的区域中；The target data is cached in the region indicated by the target cache address; 在所述第一索引表中记录所述目标数据的目标地址信息，其中，所述目标地址信息包括所述目标逻辑地址以及所述目标缓存地址。The target address information of the target data is recorded in the first index table, wherein the target address information includes the target logical address and the target cache address. 8.根据权利要求7所述的方法，其特征在于，将所述缓存区域中缓存的所述第一数据替换为所述目标数据，包括：8. The method according to claim 7, characterized in that replacing the first data cached in the cache region with the target data includes: 在所述缓存区域中缓存有所述第一数据的情况下，基于所述第一索引表中记录的逻辑地址与缓存地址的对应关系，确定与所述第一逻辑地址对应的第一缓存地址；When the first data is cached in the cache area, the first cache address corresponding to the first logical address is determined based on the correspondence between the logical address and the cache address recorded in the first index table. 删除所述第一缓存地址所指示的区域中缓存的所述第一数据。Delete the first data cached in the region indicated by the first cache address. 9.根据权利要求1或8所述的方法，其特征在于，删除所述第一缓存地址所指示的区域中缓存的所述第一数据之后，所述方法还包括：9. The method according to claim 1 or 8, characterized in that, after deleting the first data cached in the region indicated by the first cache address, the method further includes: 删除所述第一索引表中记录的所述第一数据的第一地址信息，其中，所述第一地址信息包括所述第一逻辑地址以及所述第一缓存地址；Delete the first address information of the first data recorded in the first index table, wherein the first address information includes the first logical address and the first cache address; 更新所述缓存区域中缓存的数据的数据量。Update the amount of data cached in the cache area. 10.根据权利要求7所述的方法，其特征在于，在所述第一索引表中记录所述目标数据的目标地址信息之后，所述方法还包括：10. The method according to claim 7, characterized in that, after recording the target address information of the target data in the first index table, the method further includes: 在所述缓存区域中不存在所述第一数据的情况下，更新所述缓存区域中缓存的数据的数据量。If the first data is not present in the cache area, update the amount of data cached in the cache area. 11.根据权利要求1所述的方法，其特征在于，在所述缓存区域缓存的数据的目标数据量满足预设条件时，调用目标中央处理器将所述缓存区域缓存的数据写入至所述闪存区域中，包括：11. The method according to claim 1, characterized in that, when the target data amount of the data cached in the cache region meets a preset condition, the target central processing unit is invoked to write the data cached in the cache region to the flash memory region, comprising: 基于坏块表确定写入阈值，其中，所述坏块表用于记录所述闪存区域中包括的状态异常的第一存储区域；The write threshold is determined based on a bad block table, wherein the bad block table is used to record the first storage area with abnormal state included in the flash memory area; 在所述目标数据量达到所述写入阈值的情况下，调用目标中央处理器将所述缓存区域缓存的数据写入至所述闪存区域中的包括的状态正常的第二存储区域中。When the target data volume reaches the write threshold, the target central processing unit is invoked to write the data cached in the cache area to the second storage area in the flash memory area that is in a normal state. 12.根据权利要求11所述的方法，其特征在于，基于坏块表确定写入阈值，包括：12. The method according to claim 11, characterized in that determining the write threshold based on the bad block table includes: 基于所述坏块表中记录的所述第一存储区域，确定所述第二存储区域；The second storage area is determined based on the first storage area recorded in the bad block table; 基于所述第二存储区域的剩余存储空间，确定所述写入阈值。The write threshold is determined based on the remaining storage space in the second storage area. 13.根据权利要求2所述的方法，其特征在于，在所述缓存区域缓存的数据的目标数据量满足预设条件时，调用目标中央处理器将所述缓存区域缓存的数据写入至所述闪存区域之后，所述方法还包括：13. The method according to claim 2, characterized in that, after calling the target central processing unit to write the data cached in the cache region to the flash memory region when the target data amount of the data cached in the cache region meets the preset conditions, the method further includes: 删除所述缓存区域中缓存的已写入所述闪存区域中的数据；Delete the data cached in the cache area that has already been written to the flash memory area; 删除所述第一索引表中记录的已写入所述闪存区域中的数据的地址信息，并更新所述缓存区域中缓存的数据的数据量；Delete the address information of the data already written to the flash memory area recorded in the first index table, and update the amount of data cached in the cache area; 更新第二索引表，其中，所述第二索引表用于记录已写入所述闪存区域中的数据在所述固态硬盘中的逻辑地址与在所述闪存区域中的物理地址之间的对应关系。Update the second index table, wherein the second index table is used to record the correspondence between the logical address of the data written into the flash memory area in the solid-state drive and the physical address in the flash memory area. 14.一种控制器，其特征在于，包括：14. A controller, characterized in that it comprises: 接收模块，用于接收写入请求，其中，所述写入请求用于请求将目标数据写入固态硬盘中包括的闪存区域中；A receiving module is configured to receive a write request, wherein the write request is used to request that target data be written to a flash memory area included in the solid-state drive; 确定模块，用于基于所述目标数据在所述固态硬盘中的目标逻辑地址，确定所述固态硬盘中包括的缓存区域中是否存在第一数据，其中，所述缓存区域用于缓存待写入所述闪存区域中的数据，所述第一数据在所述固态硬盘中的第一逻辑地址与所述目标逻辑地址相同；The determining module is used to determine whether first data exists in a cache area included in the solid-state drive based on the target logical address of the target data in the solid-state drive, wherein the cache area is used to cache data to be written to the flash memory area, and the first logical address of the first data in the solid-state drive is the same as the target logical address; 替换模块，用于在所述缓存区域中存在所述第一数据的情况下，将所述缓存区域中缓存的所述第一数据替换为所述目标数据；A replacement module is configured to replace the first data cached in the cache area with the target data if the first data already exists in the cache area. 调用模块，用于在所述缓存区域缓存的数据的目标数据量满足预设条件时，调用目标中央处理器将所述缓存区域缓存的数据写入至所述闪存区域中，其中，所述缓存区域缓存的数据中包括所述目标数据；The calling module is used to call the target central processing unit to write the data cached in the cache area to the flash memory area when the target data amount of the data cached in the cache area meets the preset conditions, wherein the data cached in the cache area includes the target data; 所述替换模块，包括：第六确定子模块，用于在所述缓存区域中缓存有所述第一数据的情况下，基于第一索引表中记录的逻辑地址与缓存地址的对应关系，确定与所述第一逻辑地址对应的第一缓存地址，并删除所述第一缓存地址所指示的区域中缓存的所述第一数据，其中，所述第一索引表用于记录所述缓存区域中缓存的待写入所述闪存区域中的数据的地址信息；第七确定子模块，用于确定解析结果中包括的所述目标数据的数据长度，基于所述数据长度，确定所述目标数据在所述缓存区域中的目标缓存地址，将所述目标数据缓存至所述目标缓存地址所指示的区域中，以及，在所述第一索引表中记录所述目标数据的目标地址信息，其中，所述目标地址信息包括所述目标逻辑地址以及所述目标缓存地址，所述解析结果是解析所述写入请求得到的。The replacement module includes: a sixth determining submodule, configured to, when the first data is cached in the cache area, determine a first cache address corresponding to the first logical address based on the correspondence between logical addresses and cache addresses recorded in a first index table, and delete the first data cached in the area indicated by the first cache address, wherein the first index table is used to record address information of data to be written to the flash memory area cached in the cache area; and a seventh determining submodule, configured to determine the data length of the target data included in the parsing result, determine the target cache address of the target data in the cache area based on the data length, cache the target data in the area indicated by the target cache address, and record the target address information of the target data in the first index table, wherein the target address information includes the target logical address and the target cache address, and the parsing result is obtained by parsing the write request. 15.一种数据的写入系统，其特征在于，包括：15. A data writing system, characterized in that it comprises: 权利要求14所述的控制器，以及，所述固态硬盘。The controller of claim 14, and the solid-state drive. 16.根据权利要求15所述的系统，其特征在于，还包括：16. The system according to claim 15, characterized in that it further comprises: 多个中央处理器，其中，所述多个中央处理器中包括目标处理器。Multiple central processing units, wherein the multiple central processing units include a target processor. 17.一种电子设备，其特征在于，包括：17. An electronic device, characterized in that it comprises: 存储器，用于存储计算机程序；Memory, used to store computer programs; 处理器，用于执行所述计算机程序时实现如权利要求1至13任一项所述数据的写入方法的步骤。A processor, configured to implement the steps of the data writing method as described in any one of claims 1 to 13 when executing the computer program. 18.一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有计算机程序，其中，所述计算机程序被处理器执行时实现如权利要求1至13任一项所述数据的写入方法的步骤。18. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the data writing method as described in any one of claims 1 to 13. 19.一种计算机程序产品，包括计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求1至13任一项所述数据的写入方法的步骤。19. A computer program product comprising a computer program, characterized in that, when the computer program is executed by a processor, it implements the steps of the data writing method as described in any one of claims 1 to 13.
CN202511580967.6A 2025-10-31 2025-10-31 Data writing methods, systems, electronic devices, storage media, and program products Active CN121029106B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202511580967.6A CN121029106B (en) 2025-10-31 2025-10-31 Data writing methods, systems, electronic devices, storage media, and program products

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202511580967.6A CN121029106B (en) 2025-10-31 2025-10-31 Data writing methods, systems, electronic devices, storage media, and program products

Publications (2)

Publication Number Publication Date
CN121029106A CN121029106A (en) 2025-11-28
CN121029106B true CN121029106B (en) 2026-01-27

Family

ID=97773000

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202511580967.6A Active CN121029106B (en) 2025-10-31 2025-10-31 Data writing methods, systems, electronic devices, storage media, and program products

Country Status (1)

Country Link
CN (1) CN121029106B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119597218A (en) * 2024-11-25 2025-03-11 曙光信息产业股份有限公司 Data write-back method, device, equipment and medium

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107220001A (en) * 2017-05-18 2017-09-29 记忆科技(深圳)有限公司 A kind of solid state hard disc cache implementing method and solid state hard disc
CN107402890B (en) * 2017-07-24 2020-10-02 华中科技大学 A data processing method and system based on solid state disk array and cache
CN108920096A (en) * 2018-06-06 2018-11-30 深圳忆联信息系统有限公司 A kind of data storage method of SSD, device, computer equipment and storage medium
CN110008142A (en) * 2019-04-16 2019-07-12 苏州浪潮智能科技有限公司 Storing data management method, device, equipment and computer readable storage medium
CN113392036B (en) * 2020-03-11 2024-02-02 深圳星火半导体科技有限公司 Solid-state memory and data writing method and device thereof
CN115756327B (en) * 2022-11-22 2025-07-25 郑州云海信息技术有限公司 Solid state disk, data writing method and device thereof, host and storage medium
CN118535094A (en) * 2024-05-27 2024-08-23 山东云海国创云计算装备产业创新中心有限公司 Solid state disk cache management method, device, equipment and storage medium
CN121680730A (en) * 2024-09-25 2026-03-17 平头哥(上海)半导体技术有限公司 Data writing method, storage device and data writing system
CN118897655B (en) * 2024-09-29 2025-01-28 苏州元脑智能科技有限公司 Data request processing method, device, computer equipment and storage medium

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119597218A (en) * 2024-11-25 2025-03-11 曙光信息产业股份有限公司 Data write-back method, device, equipment and medium

Also Published As

Publication number Publication date
CN121029106A (en) 2025-11-28

Similar Documents

Publication Publication Date Title
CN108804350B (en) A memory access method and computer system
US20200117368A1 (en) Method for achieving data copying in ftl of solid state drive, system and solid state drive
CN115168259B (en) A data access method, device, device and computer-readable storage medium
US20130091331A1 (en) Methods, apparatus, and articles of manufacture to manage memory
US10635356B2 (en) Data management method and storage controller using the same
CN110413211B (en) Storage management method, electronic device, and computer-readable medium
WO2017041570A1 (en) Method and apparatus for writing data to cache
CN110147331A (en) Cache data processing method, system and readable storage medium
CN110674051A (en) Data storage method and device
US11436150B2 (en) Method for processing page fault by processor
US11782854B2 (en) Cache architecture for a storage device
CN106354664A (en) Solid state disk data transmission method and device
CN113407120A (en) Mapping table management method and device based on HMB and computer equipment
US20260023689A1 (en) Systems, methods, and apparatus for accessing data in versions of memory pages
CN108664217B (en) A caching method and system for reducing write performance jitter of solid state disk storage system
US20260093620A1 (en) Fast lba/pba table rebuild by skipping read of metadata of lba bin that is not mapped
CN110968527B (en) FTL provided caching
EP4033346B1 (en) Affinity-based cache operation for a persistent storage device
CN120687382A (en) Memory access method and electronic device
US20250117333A1 (en) Data processing method and apparatus, electronic device, and computer-readable storage medium
CN121029106B (en) Data writing methods, systems, electronic devices, storage media, and program products
CN110968525B (en) FTL provided cache, optimization method and storage device thereof
WO2025021047A1 (en) Command processing method, log processing method, and storage device
US12105968B2 (en) Systems, methods, and devices for page relocation for garbage collection
CN111796757A (en) A kind of solid state hard disk cache area management method and device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant