CN120166754A

CN120166754A - LDMOS device and manufacturing method thereof

Info

Publication number: CN120166754A
Application number: CN202510404167.2A
Authority: CN
Inventors: 肖莉红; 刘世振
Original assignee: Rongxin Semiconductor Ningbo Co ltd
Current assignee: Rongxin Semiconductor Ningbo Co ltd
Priority date: 2025-04-01
Filing date: 2025-04-01
Publication date: 2025-06-17

Abstract

An LDMOS device and a manufacturing method thereof, the LDMOS device comprising: a semiconductor substrate; a body region, a drift region, a source region in the body region, and a drain region in the drift region formed in the semiconductor substrate; at least two shallow trench isolation structures formed in the drift region, the tops of the at least two shallow trench isolation structures being higher than the surface of the semiconductor substrate, and a dielectric layer being formed between the parts of the at least two shallow trench isolation structures higher than the surface of the semiconductor substrate; and a gate structure, the gate structure comprising a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, the gate structure extending laterally from the body region to the drift region and at least partially covering the shallow trench isolation structure. The LDMOS structure has a relatively high breakdown voltage.

Description

LDMOS device and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to an LDMOS device and a manufacturing method thereof.

Background

The lateral diffusion metal oxide semiconductor (LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR, LDMOS) adopts double diffusion technology, and sequentially diffuses boron and phosphorus twice in the same window, and the channel length can be accurately determined by the difference of the lateral junction depths of the two impurity diffusion times. The LDMOS device is mainly used for a power integrated circuit and has the advantages of high breakdown voltage, high switching speed, compatibility with complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) device processes and the like.

For LDMOS devices, on-resistance (Rdson) and breakdown voltage (BVdss) are the two most important parameters. The smaller the on-resistance, the stronger the driving capability of the LDMOS device, and the larger the breakdown voltage, the higher the reliability of the LDMOS device. It is generally desirable for LDMOS devices to have a small on-resistance and a large breakdown voltage. The shallow trench isolation (Shallow Trench Isolation, STI) structure is formed in the drift region of the LDMOS device, so that the electric field distribution of the drift region can be optimized, the electric field peak is reduced, and the local breakdown caused by electric field concentration in the drift region is avoided. However, the junction between the gate dielectric layer and the top of the STI sidewall is still prone to early breakdown, resulting in a reduced breakdown voltage of the LDMOS device.

Disclosure of Invention

In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In view of the problems existing at present, an aspect of an embodiment of the present invention provides an LDMOS device, where the LDMOS device includes:

A semiconductor substrate;

a body region formed in the semiconductor substrate, a drift region, and a source region in the body region and a drain region in the drift region;

At least two shallow trench isolation structures formed in the drift region, the top of the at least two shallow trench isolation structures being higher than the surface of the semiconductor substrate, and a dielectric layer being formed between portions of the at least two shallow trench isolation structures higher than the surface of the semiconductor substrate, and

The grid structure comprises a grid dielectric layer and a grid electrode layer positioned on the grid dielectric layer, and the grid structure transversely extends from the body region to the drift region and at least partially covers the shallow trench isolation structure.

In one embodiment, the gate structure at least partially covers the dielectric layer.

In one embodiment, the gate structure is stepped in shape, with a top of the gate structure above the shallow trench isolation structure being higher than a top of the gate structure above the body region and the drift region.

In one embodiment, the at least two shallow trench isolation structures have rounded top corners and/or the shallow trench isolation structures have rounded bottom corners.

Another aspect of the embodiments of the present invention provides a method for manufacturing an LDMOS device, where the method includes:

Providing a semiconductor substrate;

Forming a drift region in the semiconductor substrate;

forming at least two shallow trenches in the drift region;

Filling isolation materials in the at least two shallow trenches to form at least two shallow trench isolation structures, wherein the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate;

Forming a dielectric layer between the at least two shallow trench isolation structures and a part higher than the surface of the semiconductor substrate, and forming a gate dielectric layer on the semiconductor substrate and the shallow trench isolation structures;

Forming a gate electrode layer on the gate dielectric layer;

The gate electrode layer and the gate dielectric layer are patterned to form a gate structure extending laterally from the body region to the drift region and at least partially covering the shallow trench isolation structure.

In one embodiment, the forming at least two shallow trenches in the drift region includes:

Sequentially forming a hard mask layer and a photoresist layer on the semiconductor substrate;

Sequentially etching the hard mask layer and the semiconductor substrate based on the photoresist layer to form openings corresponding to the at least two shallow trenches in the hard mask layer and form the at least two shallow trenches in the semiconductor substrate;

Filling isolation materials in the at least two shallow trenches to form at least two shallow trench isolation structures, wherein the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, and the method comprises the following steps:

forming an isolation material filling the shallow trench and the opening;

and removing the hard mask layer to obtain the at least two shallow trench isolation structures with tops higher than the surface of the semiconductor substrate.

In one embodiment, after forming the at least two shallow trenches and before filling the at least two shallow trenches with isolation material, the method further comprises:

And carrying out smooth treatment on the top angles and/or the bottom angles of the at least two shallow grooves.

In one embodiment, the rounding the top and/or bottom corners of the at least two shallow trenches includes:

laterally etching the hard mask layer to enlarge the opening and expose the top angle of the shallow trench;

and executing an isotropic dry etching process to smooth the top angle and the bottom angle.

In one embodiment, the forming a dielectric layer between the at least two shallow trench isolation structures and a portion of the semiconductor substrate above the surface of the semiconductor substrate, and forming a gate dielectric layer on the semiconductor substrate and the shallow trench isolation structures, includes:

And performing a thermal oxidation process on the surface of the semiconductor substrate to obtain the dielectric layer and the gate dielectric layer.

Yet another aspect of embodiments of the present invention provides a semiconductor device comprising a CMOS device comprising a shallow trench isolation structure having rounded top corners and/or rounded bottom corners, and an LDMOS device as described above.

The embodiment of the invention also provides an electronic device, which comprises the semiconductor device.

According to the LDMOS device provided by the invention, at least two shallow trench isolation structures are arranged in the drift region, so that breakdown voltage can be improved without increasing on-resistance, the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, the thickness of insulating materials below the gate structure is increased, the electric field strength at the junction of the gate structure and the shallow trench isolation structure is reduced, breakdown at the junction is avoided, and the breakdown voltage of the LDMOS device is further improved.

Drawings

The following drawings are included to provide an understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and their description to explain the principles of the invention.

In the accompanying drawings:

Fig. 1 is a schematic cross-sectional view showing an LDMOS device according to the related art;

fig. 2 is a schematic flow chart of a method for manufacturing an LDMOS device according to an embodiment of the present invention;

Fig. 3A to 3G are schematic cross-sectional views of an LDMOS device according to a specific embodiment of the present invention, which is obtained by sequentially performing the steps of the method for manufacturing an LDMOS device;

fig. 4 shows a schematic cross-sectional view of a CMOS device in a semiconductor device according to an embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention.

It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Currently, in order to improve the breakdown voltage of an LDMOS device, a gate field plate structure is generally adopted. The conventional gate field plate structure has three kinds of Step-oxide structures, silicon local oxidation isolation (Local Oxidation of Silicon, LOCOS structures) and STI structures. As shown in fig. 1, the LDMOS device based on the STI structure includes a semiconductor substrate 100, a drift region 101 formed in the semiconductor substrate 100, and a body region 102 adjacent to the drift region 101, a body contact region 103 and a source region 104 are formed in the body region 102, a shallow trench isolation structure 106 and a drain region 105 are formed in the drift region 101, and the drain region 105 is formed on a side of the shallow trench isolation structure 106 remote from the source region 104. A gate structure is also formed on the semiconductor substrate 100, the gate structure including a gate dielectric layer 107 and a gate electrode layer 108, and the gate structure partially covers the shallow trench isolation structure 106. The body region is used as a channel region for controlling on and off of the LDMOS device, the drift region is used for bearing high voltage of the LDMOS device, and the effective length of the drift region is increased by the groove isolation filling structure, so that breakdown voltage of the LDMOS device is improved.

The main disadvantage of the LDMOS device shown in fig. 1 is that the junction of the gate dielectric layer and the top of the sidewall of the trench isolation filling structure is prone to early breakdown, resulting in a reduced breakdown voltage of the LDMOS device. In order to increase the breakdown voltage, one way is to reduce the ion implantation dose of the drift region or to reduce the size of the drift region surrounding the trench insulation filling structure, but both methods result in an increase of the on-resistance of the LDMOS device. Meanwhile, increasing the width of the shallow trench isolation structure cannot further increase the breakdown voltage of the LDMOS device.

In view of the foregoing technical problems, an embodiment of the present invention provides an LDMOS device and a method for manufacturing the same. Next, a method for manufacturing an LDMOS device according to an embodiment of the invention will be described in detail with reference to fig. 2 to 3G, wherein fig. 2 is a schematic flowchart illustrating a method for manufacturing an LDMOS device according to an embodiment of the invention, and fig. 3A and 3G are cross-sectional views illustrating a device obtained by implementing a method for manufacturing an LDMOS device according to an embodiment of the invention.

First, step S201 is performed, and as shown in fig. 3A, a semiconductor substrate 300 is provided.

Illustratively, the material of the semiconductor substrate 300 includes, but is not limited to, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, or is silicon-on-dielectric (SOI), silicon-on-dielectric (SSOI), silicon-germanium-on-dielectric (S-SiGeOI), silicon-germanium-on-dielectric (SiGeOI), and germanium-on-dielectric (GeOI).

Illustratively, the semiconductor substrate 300 has first conductivity type dopant ions, which may be P-type dopant ions or N-type dopant ions. When the LDMOS is formed into an N-type LDMOS device, the first conduction type is P-type, and when the LDMOS is formed into a P-type LDMOS device, the first conduction type is N-type. The following description will mainly take the first conductivity type as P-type as an example.

Next, step S202 is performed to form a drift region 301 in the semiconductor substrate 300.

Illustratively, the semiconductor substrate 300 may also be subjected to a second conductivity type dopant ion implantation prior to forming the drift region 301 to form a well region, illustratively having N-type dopant ions.

Next, a drift region 301 having dopant ions of the second conductivity type, such as N-type dopant ions, is formed in the well region. The doping concentration of the drift region 301 is low, thus enabling the LDMOS device to withstand higher voltages.

Next, step S203 is performed to form at least two shallow trenches in the drift region 301. Illustratively, at least two shallow trenches have the same width and depth. The number of the shallow trenches may be two or more, and may be specifically set according to the process requirements. Illustratively, shallow trenches may also be formed prior to the drift region 301.

Specifically, first, as shown in fig. 3B, a hard mask layer 302 is formed on a semiconductor substrate 300. The material of the hard mask layer 302 may include one or more combinations of nitride, oxide, oxynitride, fluorine-containing silicon dioxide FSG, carbon-doped silicon oxide, and the like. Methods of forming the hard mask layer 302 include, but are not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and the like. In one example, the hard mask layer includes a silicon oxide layer and a silicon nitride layer sequentially formed on the semiconductor substrate 300.

Next, a photoresist layer 303 is formed on the hard mask layer 302, and the hard mask layer 302 and the semiconductor substrate 300 are sequentially etched based on the photoresist layer 303 to form an opening in the hard mask layer 302 and a shallow trench under the opening in the semiconductor substrate 300.

Specifically, a photoresist layer 303 is first spin-coated on the hard mask layer 302, and the photoresist layer 303 is exposed and developed, so that at least two windows, each corresponding to a shallow trench, are formed in the photoresist layer 303, as shown in fig. 3B. Thereafter, an anisotropic dry etching process is performed using the photoresist layer 303 as a mask, thereby forming at least two openings in the hard mask layer 302 under the window, and etching the semiconductor substrate 300 exposed by the openings to form at least two shallow trenches, as shown in fig. 3C. Then, the photoresist layer may be removed by ashing or the like, and cleaning and drying processes may be performed.

The shallow trench formed based on the etching process has sharp top angles and sharp bottom angles, and an electric field peak is easy to form at the shallow trench, so that the breakdown voltage of the LDMOS device is reduced. To avoid this problem, the top and/or bottom corners of the shallow trenches may be rounded so that the electric field distribution at the corners is optimized, as shown in fig. 3D.

In one example, the top and/or bottom corners of the shallow trench may be rounded using an isotropic dry etch process. Specifically, first, the hard mask layer 302 is laterally etched to enlarge an opening formed in the hard mask layer 302 and expose the top corners of the shallow trench, and then, an isotropic dry etching process is performed to smooth the top and bottom corners of the shallow trench. In the process of executing the isotropic dry etching process, O ₂ and CF ₄ plasmas can be adopted, and bias voltage is not applied, so that the plasmas bombard the bottom of the shallow trench in different directions, and the top angle and the bottom angle of the shallow trench are smoothly processed.

When the hard mask layer 302 includes a stack of a plurality of different materials, only the hard mask material layer adjacent to the semiconductor substrate 300 may be laterally etched, thereby exposing the top corners of the shallow trenches thereunder, without reducing the thickness of the hard mask layer, and ensuring that the subsequently formed shallow trench isolation structures have a desired height. For example, when the hard mask layer 302 includes a silicon oxide layer and a silicon nitride layer formed in sequence, the silicon oxide layer may be laterally etched with a dilute hydrofluoric acid solution to expose the semiconductor substrate 300 under the silicon oxide layer, with a simple process and without affecting the thickness of the silicon nitride layer above.

Next, step S204 is performed to form an isolation material in the at least two shallow trenches to form at least two shallow trench isolation structures 304, wherein the top of the at least two shallow trench isolation structures 304 is higher than the surface of the semiconductor substrate 300.

Specifically, first, as shown in fig. 3E, an isolation material is deposited to fill at least two shallow trenches in the semiconductor substrate 300 and to fill openings formed in the hard mask layer 302 over the shallow trenches. The isolation material may include at least one of silicon dioxide, silicon nitride, ethyl orthosilicate, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, silicon oxynitride, and other insulating materials. The deposition process includes, but is not limited to, a chemical vapor deposition (Chemical Vapor Deposition, CVD) process. Because the shallow trench in the embodiment of the invention has narrower width and larger depth-to-width ratio compared with the conventional shallow trench, the isolation material can be deposited by adopting a high-density plasma chemical vapor deposition (HIGH DENSITY PLASMA-Chemical Vapor Deposition, HDP-CVD) process so as to avoid generating cavities during filling. Next, a planarization process is performed to remove the isolation material over the hard mask layer 302, which may include a Chemical Mechanical Polishing (CMP) process.

Thereafter, as shown in fig. 3F, the hard mask layer 302 is removed, so as to obtain a shallow trench isolation structure 304, wherein the top of the shallow trench isolation structure 304 is higher than the surface of the semiconductor substrate. For example, a wet etch process may be used to remove the hard mask layer 302, with a fill material filling the opening in the hard mask layer 302 constituting the portion of the shallow trench isolation structure 304 above the semiconductor substrate 300. Thus, the shallow trench isolation structure 304 above the semiconductor substrate 300 can be obtained based on the existing hard mask layer without adding additional processes.

Next, step S205 is performed, as shown in fig. 3G, to form a dielectric layer 305 between at least two portions of the shallow trench isolation structure 304 above the surface of the semiconductor substrate 300, and to form a gate dielectric layer 306 on the semiconductor substrate 300 and the shallow trench isolation structure 304.

Illustratively, a thermal oxidation process may be employed to oxidize the surface of the semiconductor substrate 300, thereby simultaneously forming the dielectric layer 305 and the gate dielectric layer 306. Specifically, the semiconductor substrate 300 may be exposed to oxygen or water vapor at a high temperature of 800-1100 ℃ to react silicon with oxygen to form silicon dioxide. The thermal oxidation process can be used to produce high quality gate dielectric layer 306 and dielectric layer 305, and can avoid the problem of incomplete filling of dielectric layer 305 that may occur in the deposition process. The dielectric layer 305 may connect the portions of the at least two shallow trench isolation structures 304 higher than the surface of the semiconductor substrate 300 into a whole, which together have the effects of increasing the thickness of the dielectric layer and increasing the breakdown voltage.

Next, step S206 is performed to form a gate electrode layer 307 on the gate dielectric layer 306. Specifically, the gate electrode layer 307 may be formed by performing a deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and the material of the gate electrode layer 307 may include a conductive material such as polysilicon or metal. Since a portion of the gate electrode layer 307 is formed over the shallow trench isolation structure 304, the top of the gate electrode layer 307 over the shallow trench isolation structure 304 is higher than the top of the gate electrode layer 307 over the semiconductor substrate 300, so that the gate electrode layer 307 takes on a stepped shape.

Next, step S207 is performed to pattern the gate electrode layer 307 and the gate dielectric layer 306 to form a gate structure. Specifically, a mask layer may be formed on the gate electrode layer 307, and the gate electrode layer 307 and the gate dielectric layer 306 may be etched based on the mask layer to obtain a stepped gate structure. Spacers 308 may be formed on both sides of the gate structure to protect the sidewalls of the gate structure.

After forming the gate structure, step S208 is performed to form a body region 309 in the semiconductor substrate 300, the body region 309 having dopant ions of the first conductivity type, such as P-type dopant ions. A body region 309 is arranged in the semiconductor substrate 300 alongside the drift region 301, the gate structure also covering part of the body region 309 to form a channel region in operation. It should be noted that the body 309 may be formed prior to the gate structure or prior to the shallow trench.

Next, step S209 is performed to form a drain region 312 in the drift region 301 and a source region 310 in the body region 309. In addition, a body contact region 311 may also be formed in body 309. Wherein drain region 312 is located on a side of shallow trench isolation structure 304 remote from body region 309 and body contact region 311 is located on a side of source region 310 remote from drift region 301. The body contact region 311 has doping ions of the first conductivity type, the source region 310 and the drain region 312 have doping ions of the second conductivity type, for example, the body contact region 311 has P-type doping ions, the source region 310 and the drain region 312 have N-type doping ions, and the source region 310, the drain region 312, and the body contact region 311 have a higher doping concentration. After forming source region 310 and drain region 312, a high temperature anneal process is performed to form a graded doping profile with the previously implanted dopant ions.

Thus far, the process steps performed by the method for manufacturing an LDMOS device according to the embodiment of the first aspect of the invention are completed, and it will be understood that the method for manufacturing an LDMOS device of the present embodiment may include not only the above steps, but also other steps as needed before, during or after the above steps, which are included in the scope of the method for manufacturing an LDMOS device of the present embodiment.

According to the manufacturing method of the LDMOS device, at least two shallow trench isolation structures are arranged in the drift region, so that breakdown voltage can be improved without increasing on-resistance, the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, thickness of insulating materials below the gate structure is increased, electric field strength at the junction of the gate structure and the shallow trench isolation structures is reduced, breakdown at the junction is avoided, and breakdown voltage of the LDMOS device is further improved.

The embodiment of the invention also provides an LDMOS device, which can be prepared by the method in the previous embodiment, but is not limited to the method.

In the following, the LDMOS device of the present invention will be described and illustrated in detail, but for avoiding repetition, only the same components and structures as in the previous embodiments will be briefly described, and a specific explanation and description thereof will be given with reference to the description in the first embodiment.

Specifically, as shown in fig. 3G, the LDMOS device of the embodiment of the invention comprises a semiconductor substrate 300, a body region 309 formed in the semiconductor substrate 300, a drift region 301, a source region 310 located in the body region 309 and a drain region 312 located in the drift region 301, at least two shallow trench isolation structures 304 formed in the drift region 301, the tops of the at least two shallow trench isolation structures 304 being higher than the surface of the semiconductor substrate 300 and a dielectric layer 305 formed between the portions of the at least two shallow trench isolation structures 304 higher than the surface of the semiconductor substrate 300, and a gate structure comprising a gate dielectric layer 306 and a gate electrode layer 307 located on the gate dielectric layer 306, the gate structure self-body region 309 extending laterally to the drift region 301 and at least partially covering the shallow trench isolation structures 304.

Further, the gate structure at least partially covers the dielectric layer 305.

Further, the gate structure is stepped in shape, with the top of the gate structure above the shallow trench isolation structure 304 being higher than the top of the gate structure above the body 309 and drift 301 regions.

Further, the shallow trench isolation structure 304 has rounded top corners and/or the shallow trench isolation structure 304 has rounded bottom corners.

The LDMOS device is provided with at least two shallow trench isolation structures in the drift region, so that breakdown voltage can be improved without increasing on-resistance, the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, the thickness of insulating materials below the gate structure is increased, the electric field strength at the junction of the gate structure and the shallow trench isolation structure is reduced, breakdown at the junction is avoided, and the breakdown voltage of the LDMOS device is further improved.

Another aspect of the embodiments of the present invention provides a semiconductor device including the LDMOS device and the CMOS device described above. As shown in fig. 4, the CMOS device includes a semiconductor substrate 400, at least two transistor structures 401 formed in the semiconductor substrate, and a shallow trench isolation structure 402 between the at least two transistor structures 401, the shallow trench isolation structure having rounded top corners and/or rounded bottom corners. Each transistor structure 401 includes at least a source region, a drain region between the semiconductor substrates 400, and a gate structure over the semiconductor substrate 400 between the source region and the drain region.

The semiconductor device may be a BCD (Bipolar-CMOS-DMOS) device, i.e. a semiconductor device combining Bipolar, CMOS and DMOS (double diffused metal oxide semiconductor) transistors on a single chip. The CMOS is mainly used for controlling logic operation, and the LDMOS is mainly used for voltage withstanding, gain, linearity, heat dissipation and the like.

In a CMOS device, if the top and bottom corners of the shallow trench isolation structure are sharp corners, electric field spikes are easily induced, and carrier mobility is reduced, so that the threshold voltage (Vth) of the CMOS device is reduced, and even a "double-peak effect" (Hump Effect) of the device is caused, which leads to dew point problems and output errors of the semiconductor, and further causes termination failure, so that the reliability of the whole circuit is affected. The embodiment of the invention sets the shallow trench isolation structure of the CMOS device to have smooth top angles and/or smooth bottom angles, so that the problems can be avoided. Illustratively, the shallow trench isolation structure of the CMOS device and the shallow trench isolation structure of the LDMOS device are formed simultaneously, and the top angle and/or the bottom angle of the shallow trench isolation structure and the shallow trench isolation structure of the LDMOS device can be rounded by the same isotropic dry etching process.

The embodiment of the invention also provides an electronic device which comprises the semiconductor device, and the semiconductor device can be prepared according to the method.

The electronic device of the embodiment may be any electronic product or apparatus such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, MP3, MP4, PSP, and the like, and may also be any intermediate product including a circuit. The electronic device provided by the embodiment of the invention has better performance due to the use of the semiconductor device.

The present invention has been illustrated by the above-described embodiments, but it should be understood that the above-described embodiments are for purposes of illustration and description only and are not intended to limit the invention to the embodiments described. In addition, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications are possible in light of the teachings of the invention, which variations and modifications are within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. An LDMOS device, characterized in that the LDMOS device comprises:

A semiconductor substrate;

2. The LDMOS device of claim 1, wherein the gate structure at least partially covers the dielectric layer.

3. The LDMOS device of claim 1, wherein the gate structure is stepped in shape with a top of the gate structure above the shallow trench isolation structure being higher than a top of the gate structure above the body region and the drift region.

4. The LDMOS device of claim 1, wherein the at least two shallow trench isolation structures have rounded top corners and/or the at least two shallow trench isolation structures have rounded bottom corners.

5. A method of fabricating an LDMOS device, the method comprising:

Providing a semiconductor substrate;

Forming a drift region in the semiconductor substrate;

forming at least two shallow trenches in the drift region;

Forming isolation materials in the at least two shallow trenches to form at least two shallow trench isolation structures, wherein the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate;

Forming a gate electrode layer on the gate dielectric layer;

patterning the gate electrode layer and the gate dielectric layer to form a gate structure;

Forming a body region in the semiconductor substrate, wherein the gate structure extends from the body region to the drift region transversely and at least partially covers the shallow trench isolation structure;

a source region is formed in the body region and a drain region is formed in the drift region.

6. The method of manufacturing of claim 5, wherein the forming at least two shallow trenches in the drift region comprises:

Forming isolation materials in the at least two shallow trenches to form at least two shallow trench isolation structures, wherein tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, and the method comprises the following steps:

Depositing an isolation material to fill the shallow trenches and the openings;

7. The method of manufacturing of claim 6, wherein after forming the at least two shallow trenches, before forming isolation material in the at least two shallow trenches, the method further comprises:

8. The method of manufacturing according to claim 7, wherein the rounding of the top and/or bottom corners of the at least two shallow trenches comprises:

9. The method of manufacturing of claim 5, wherein forming a dielectric layer between portions of the at least two shallow trench isolation structures above the surface of the semiconductor substrate, and forming a gate dielectric layer over the semiconductor substrate and the shallow trench isolation structures, comprises:

10. A semiconductor device comprising a CMOS device comprising a shallow trench isolation structure having rounded top corners and/or rounded bottom corners, and an LDMOS device according to any of claims 1-4.