CN119806544B - Binary translation method, binary translation device, electronic equipment and readable storage medium - Google Patents

Abstract

This application discloses a binary translation method, apparatus, electronic device, and readable storage medium. The method includes: obtaining the translation result of each basic block from the translator's cache; when executing an instruction in the translation result, if it is determined that the currently executed instruction is a target instruction with a memory alignment exception, remapping is performed based on a first memory access address included in the target instruction to generate a second memory access address, and the memory slice corresponding to the first memory access address is configured as inaccessible; and a memory access operation is performed on the second memory access address to access the data at the second memory access address. This method can solve the problem in the prior art of unconditionally stopping the execution of all other threads, which affects the efficiency of source program instruction translation execution.

Description

Binary translation method, device, electronic device and readable storage medium

Technical Field

The present application belongs to the field of computer technology, and specifically relates to a binary translation method, device, electronic device, and readable storage medium.

Background Art

Binary translation converts instructions from one instruction set architecture (ISA) into instructions from another ISA. When the host platform translates instructions from the client platform, if the memory access address corresponding to the processing instruction does not meet the access alignment requirements supported by the host platform, the host platform typically splits an unaligned memory access operation into multiple aligned memory access operations. However, if this approach is used to simulate atomic instructions in the client, the multiple memory access operations cannot meet the atomicity requirements of the instruction and are often interrupted by other threads or processes during the operation.

In the related art, in the above situation, in order to avoid being interrupted by other threads or processes during the operation, it is usually adopted to stop other threads when executing this instruction to ensure the atomicity of the atomic instruction in the client when it is executed after translation. However, using this method to unconditionally stop the execution of all other threads will affect the efficiency of the translation and execution of the source program instructions.

Summary of the Invention

The present application aims to provide a binary translation method, device, electronic device and readable storage medium, which at least solves the problem in the prior art of unconditionally stopping the execution of all other threads, thereby affecting the efficiency of the translation and execution of source program instructions.

In order to solve the above technical problems, this application is implemented as follows:

In a first aspect, an embodiment of the present application provides a binary translation method, comprising:

Get the translation result of each basic block from the translator's cache;

When executing an instruction in the translation result, if it is determined that the currently executed instruction is a target instruction with a memory access alignment exception, remapping is performed according to a first memory access address included in the target instruction to generate a second memory access address, and a memory slice corresponding to the first memory access address is configured as inaccessible;

A memory access operation is performed on the second memory access address to access data at the second memory access address.

In a second aspect, an embodiment of the present application further provides a binary translation device, comprising:

A first acquisition module is used to obtain the translation result of each basic block from the cache of the translator;

a generating module configured to, when executing an instruction in the translation result, if it is determined that the currently executed instruction is a target instruction with a memory access alignment exception, remap the instruction according to a first memory access address included in the target instruction to generate a second memory access address, and configure a memory slice corresponding to the first memory access address as inaccessible;

An execution module is configured to execute a memory access operation on the second memory access address to access data at the second memory access address.

In a third aspect, an embodiment of the present application further provides an electronic device comprising a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the method described in the first aspect.

In a fourth aspect, an embodiment of the present application further provides a readable storage medium, which, when the instructions in the readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method described in the first aspect.

In summary, in the binary translation method of the present application, the memory access address of the memory slice can be remapped according to the first memory access address with a memory access alignment exception, and the non-aligned memory access can be converted into a memory access operation based on the new address (the second memory access address). In this way, the entire memory access process can be executed as an atomic operation, avoiding interference from other threads or processes; and the memory slice corresponding to the first memory access address is configured as inaccessible. This solution does not need to stop other threads, but solves the memory alignment problem by remapping the memory. Other threads that are not involved in data operations in the first memory slice can continue to execute unaffected tasks, reducing unnecessary thread blocking and scheduling overhead, thereby improving the overall execution efficiency, the concurrency performance of the entire system, and the efficiency of source program instruction translation and execution.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a flowchart of a binary translation method provided in an embodiment of the present application;

FIG2 is a schematic diagram of a binary translation method provided in an embodiment of the present application;

FIG3 is a schematic diagram of another binary translation method provided in an embodiment of the present application;

FIG4 is a block diagram of a binary translation device provided in an embodiment of the present application;

FIG5 is a block diagram of an electronic device according to an exemplary embodiment;

Fig. 6 is a block diagram of an electronic device according to an exemplary embodiment.

DETAILED DESCRIPTION

The binary memory access provided by the embodiment of the present application is described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

Before introducing the binary translation method, apparatus, electronic device, and readable storage medium provided by this application, we first introduce the application scenarios involved in each embodiment of this application. This application can be applied to the scenario of running the translation result on the target architecture platform, where the translation result is the target program after the source program corresponding to the source architecture platform is translated by the translator.

Currently, hardware designs based on different instruction set architectures (ISAs) support many different instructions, resulting in incompatibility between executable files compiled for one ISA and other platforms. Binary translation technology can translate source programs from one ISA platform to run on a target architecture, depending on the ISA platform.

The source program is an application developed based on a source architecture platform (client architecture platform). That is, the source program is a program developed based on a first instruction set architecture, and therefore, the source program can run normally on the client architecture platform. The target architecture platform (host architecture platform) is the machine platform to which the source program is desired to be ported. The source program can be run on the client architecture platform using source binary code. If it is desired to run the source program on the target architecture platform, the source binary code corresponding to the source program needs to be translated into target binary code. The target binary code is an executable code (or host code) based on a second instruction set architecture, so that the target binary code can be run on the target architecture platform. That is, the source program can be run in a binary translation environment in the target architecture platform using binary translation technology.

Atomic instructions in source programs are a special type of instruction whose execution is indivisible (atomic). In multi-threaded or multi-processor systems, atomic instructions ensure that their operations are not interrupted during execution, thereby avoiding race conditions and data consistency issues. The number of operands supported by atomic instructions depends on the instruction type and the characteristics of the processor architecture. Some architectures only support atomic instructions of up to 64 bits (8 bytes), while others support atomic instructions of up to 128 bits (16 bytes). For example, the cmpxchg16b instruction in x86-64 can support atomic instructions of up to 128 bits (16 bytes).

Due to the architectural differences between the host platform and the client platform, when the host platform translates the client platform's instructions, if the memory access address corresponding to the instruction does not meet the access alignment requirements supported by the host platform, a memory alignment exception will occur in the host platform. In this way, the consistency of the running results after translating the client platform's instructions to the host platform cannot be guaranteed, which in turn affects the accuracy of the source program instruction translation.

In order to ensure the consistency of the running results after translating the instructions of the client platform to the host platform, an unaligned memory access operation is usually split into multiple aligned memory access operations for execution. However, if this method is used to simulate the atomic instructions in the client, in a multi-threaded or multi-process concurrent environment, the multiple memory access operations after the split cannot meet the atomicity of the instructions and will be interrupted by other threads or processes during the operation, resulting in incorrect execution results of the final operation combination.

In the related art, in the above situation, in order to avoid being interrupted by other threads or processes during the operation, and to avoid being observed by other threads or processes in the intermediate state or out-of-order results, it is usually adopted to stop other threads when executing this instruction to ensure the atomicity of the atomic instruction in the client when it is executed after translation. However, using this method to unconditionally stop the execution of all other threads will affect the efficiency of the translation and execution of the source program instructions.

In order to solve the above problems, the present application provides a binary translation method, device, electronic device and readable storage medium, which can remap the memory access address of the memory slice according to the first memory access address with memory access alignment exception, and convert the non-aligned memory access into a memory access operation based on the new address (second memory access address). In this way, the entire memory access process can be executed as an atomic operation, avoiding interference from other threads or processes; and the memory slice corresponding to the first memory access address is configured as inaccessible. This solution does not need to stop other threads, but solves the memory alignment problem by remapping the memory. Other threads that do not involve data operations in the first memory slice can continue to execute unaffected tasks, reducing unnecessary thread blocking and scheduling overhead, thereby improving overall execution efficiency, improving the concurrency performance of the entire system and the efficiency of source program instruction translation and execution.

The method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

FIG1 is a flowchart of a binary translation method provided by this embodiment, comprising the following steps:

Step 101: Obtain the translation result of each basic block from the cache of the translator.

In this step, during the execution of multiple basic blocks included in the source program, the translation result of each basic block can be obtained from the cache of the translator.

The source program may represent an application developed based on a source architecture platform (client architecture platform). Specifically, the source program is developed based on a first instruction set architecture and includes multiple basic blocks. A basic block is a sequence of instructions executed sequentially within the source program. After reading the binary file, the translator translates and executes the source program at the basic block level.

First, when it is necessary to run the source program developed based on the source architecture platform on the target architecture platform, the source architecture instructions in each basic block included in the source program can be translated into target architecture instructions in real time based on the instructions actually executed on the basic block.

For example, the source architecture platform can be represented as an x86 architecture platform, the target architecture platform can be represented as another architecture platform, and the binary program can be represented as an x86 program. When an x86 program developed based on the x86 architecture platform is run on another architecture platform, instructions in a basic block in the x86 program can be translated.

For example, a basic block instruction included in an x86 program can be represented as follows:

MOV EAX,5; assign the immediate value 5 to the EAX register;

MOV EBX,3; assign the immediate value 3 to the EBX register;

ADD EAX,EBX; Add the values of EAX and EBX and store the result in EAX;

MOV DWORD PTR [0x1000],EAX; stores the value of EAX to the memory address [0x1000].

Since the register naming and instruction format of the instruction set of another architecture platform are different from those of x86, the general registers of the other architecture platform can be set to a0, a1, etc. When translating the basic block instructions into instructions that can be executed on the other architecture platform, the translation results corresponding to the basic block can be expressed as follows:

li a0,5; load the immediate value 5 into the a0 register;

li a1,3; load the immediate value 3 into the a1 register;

add a0,a0,a1; add the values of a0 and a1 and store the result in a0;

sd a0,0x1000; stores the value of a0 to memory address 0x1000.

The translated instruction sequence can be used as the translation result of the basic block instructions included in the x86 program, and the translated instruction sequence can be stored in the cache. When the basic block is executed, the translation result of the basic block can be obtained from the cache.

Step 102: When executing the instruction in the translation result, if it is determined that the currently executed instruction is a target instruction with a memory access alignment exception, remapping is performed according to the first memory access address included in the target instruction to generate a second memory access address, and the memory slice corresponding to the first memory access address is configured as inaccessible.

The second memory access address is an address obtained by remapping the memory area determined according to the first memory access address.

Given that different architectures have different memory address alignment requirements for their supported instructions, the x86 architecture has relatively relaxed memory address alignment requirements. For example, the x86 architecture allows unaligned memory accesses. Although unaligned accesses can result in performance degradation, especially when crossing cache line or memory page boundaries, atomic instructions using the LOCK prefix, such as LOCK XADD (for atomic swap-add operations in multiprocessor environments) or LOCK CMPXCHG (for atomic compare-and-swap operations in multiprocessor environments), guarantee atomicity even when the target address is unaligned. On the other hand, atomic instructions on other architectures, after binary translation, have memory address alignment requirements. The memory address of an atomic operation must be aligned to a natural data boundary, meaning 4-byte alignment for 32-bit data and 8-byte alignment for 64-bit data. If the target address of an atomic instruction is unaligned, an unaligned access exception is thrown, causing a program crash or undefined behavior.

In addition, the number of operands supported by atomic instructions depends on the type of instruction and the characteristics of the processor architecture. Some architectures only support atomic instructions of up to 64 bits (8 bytes), such as the RISC-V architecture (reduced instruction set architecture), while some architectures support atomic instructions of up to 128 bits (16 bytes), such as the cmpxchg16b instruction in x86-64 (an instruction used to perform 16-byte (128-bit) compare and exchange operations in the x86-64 architecture), which can support atomic instructions of up to 128 bits (16 bytes). When translating x86-64-based instructions to the RISC-V architecture for execution, although memory address alignment can be guaranteed in some cases, there are still cases where the atomicity of instructions under the translated RISC-V architecture cannot be guaranteed.

For example, when translating x86-64-based instructions to the RISC-V architecture, you can define a structure so that the starting address of each data member is an integer multiple of its size. For example, if a structure contains a 4-byte integer and an 8-byte double-precision floating-point number, place the 4-byte integer first, ensuring its address is a multiple of 4, and the 8-byte double-precision floating-point number at the end, ensuring its address is a multiple of 8. This way, memory accesses naturally meet RISC-V's alignment requirements.

In summary, when executing the instruction sequence of the basic block in the source program, when the maximum bit width of the atomic instruction that the host machine can support is smaller than the instruction bit width included in the instructions of the source program in the client to be executed, it can be considered that there is a memory access alignment exception in the target instruction to be executed; or when the memory access address alignment regulations of the atomic instructions under the host machine architecture are stricter than the memory access address alignment regulations of the atomic instructions under the client architecture, it can also be considered that there is a memory access alignment exception in the target instruction to be executed.

For example, in one possible implementation, in order to ensure the atomicity of atomic instructions during execution, unaligned memory access operations can be split into multiple aligned memory access operations for execution. For example, in a 32-bit system, to read a 32-bit (4-byte) integer starting from memory address 0x1001, since the starting address is not a multiple of 4, this is an unaligned memory access operation. In this case, the offset of the unaligned address relative to the 4-byte alignment boundary can be calculated. If the offset is greater than 0, the data can be split into two parts for reading. One part is the bytes from the unaligned address to the next alignment boundary, and the other part is the bytes required in the next aligned block. If the address is already aligned, the 4-byte data is read directly.

Alternatively, in another possible implementation, to ensure the atomicity of atomic instructions during execution, when the maximum bit width of atomic instructions supported by the host machine is smaller than the instruction bit width of the source program to be executed on the client machine, execution is performed using a spin lock combined with multiple atomic operations. For example, in the case of RISC-V emulating x86-64's 128-bit atomic swap or accumulation operations, atomic instructions supported by the host machine (such as RISC-V's 64-bit atomic instructions) are used in a loop, performing atomic operations on different parts of the target data in each attempt. During the operation, a spin lock is used to ensure that only one thread can operate on the target data at a time. For example, when implementing a 128-bit atomic swap of data, the upper and lower 64 bits of the data are first read, and then atomic compare-and-swap instructions are used to swap the upper and lower 64 bits. If any of these operations fail, the entire process is restarted. Thus, through multiple attempts and synchronization mechanisms, the atomicity of the final operation is ensured.

However, in a concurrent multi-threaded or multi-process environment, since the multiple memory access operations are not atomic, they can be interrupted by other running threads or processes during the access process, resulting in incorrect execution of the combined operations. For example, in a 32-bit system, a 32-bit integer is read from address 0x1001. This is split into two parts: the part from 0x1001 to 0x1003 and the part starting at 0x1004. If another thread or process modifies the data in the corresponding memory area during the access, the final read data will not be a coherent and correct 32-bit integer. If thread A performs an unaligned memory access split operation, first reading the data at 0x1001-0x1003, thread B then modifies the data at 0x1004, and thread A then reads the data starting at 0x1004, the 32-bit integer obtained by thread A will be incorrect, resulting in a memory access alignment exception.

In the present application, when it is determined that the currently executed instruction is a target instruction with a memory access alignment exception, remapping can be performed based on the first memory access address included in the target instruction to generate a corresponding second memory access address, and the memory slice corresponding to the first memory access address can be configured as inaccessible.

In this embodiment, it may be first determined that the currently executed instruction is a target instruction with a memory access alignment exception.

Optionally, during the execution of instructions, the system will check each instruction involving memory access. The checking method is usually to calculate the memory access address of the instruction modulo the number of alignment bytes of the corresponding data type, and to determine whether the alignment requirements are met by comparing the memory access address of the instruction with the data type involved in the instruction. If the result is not zero, it means that the memory access address does not meet the alignment requirements. At this time, this instruction is the target instruction with a memory access alignment exception. For example, for a 32-bit integer access instruction, if its memory access address modulo 4 is not 0, it means that the address is not an integer multiple of 4, that is, the address is not accessed in a 4-byte aligned manner, and it can be determined that the instruction has a memory access alignment exception.

Optionally, the initial memory access address included in the target instruction can be obtained based on the address type of the first memory access address included in the target instruction; then the memory slice corresponding to the initial memory access address is remapped to obtain the mapped second memory access address.

In one possible implementation, the first memory access address included in the target instruction is the initial memory access address included in the corresponding instruction in the basic block of the target instruction before translation, wherein the initial memory access address is an access address of the non-aligned memory access address type; then the initial memory access address can be directly translated in an aligned manner to obtain a target instruction including the initial memory access address. In this case, the first memory access address in the target instruction is consistent with the initial memory access address.

For example, when running an x86 program developed based on the x86 architecture platform on the RISC-V architecture platform, the instruction sequence based on x86-64 can be expressed as follows:

mov eax,0x1003;Assume that the data address is stored in register eax;

mov ebx,[eax]; read 32-bit data from unaligned address to register ebx;

inc ebx; add 1 to the data;

mov [eax],ebx; write the modified data back to the unaligned address;

Among them, 0x1003 is the initial memory access address. Since the ideal alignment address of 32-bit data is a multiple of 4, 0x1003 is unaligned. Then the initial memory access address 0x1003 can be directly translated according to the alignment method to obtain the target instruction sequence under the RISC-V architecture, which is expressed as follows:

li a0,0x1003;Store address 0x1003 into register a0;

lw t0,0(a0); read 32-bit data from aligned address 0x1000 to register t0;

;Extract the data corresponding to 0x1003 through logical operation;

andi t1,t0,0x000000FF; Assume that t1 is used to store the data that is ultimately needed;

addi t1,t1,1; add 1 to the data;

;Build the complete 32-bit data for writing back;

slli t2,t1,24;

or t0,t0,t2; Assume t2 is a temporary register;

sw t0,0(a0); write the modified data back to address 0x1003;

From the above instruction sequence, we can see that the first memory access address (i.e., 0x1003) is consistent with the initial memory access address. We can simulate the operation on the unaligned address 0x1003 by performing logical operations on the data read from the aligned address 0x1000.

In another possible implementation, the first memory access address included in the target instruction is a pre-set preset unaligned memory access address. This is because the instruction corresponding to the target instruction in the basic block before translation includes an initial memory access address whose instruction bit width is greater than the maximum bit width supported by the host architecture. Although the memory access address alignment can be guaranteed in some cases, there are cases where the atomicity of the host instruction cannot be guaranteed after translation. Therefore, in this case, the preset unaligned memory access address can be stored in a preset register, and the instruction including the preset unaligned memory access address can be written to the corresponding instruction position obtained after the current translated instruction is translated. In this way, the characteristic that the preset unaligned memory access address can trigger the execution stop signal can be utilized to enable the subsequent steps of this application to ensure the atomicity of the translated instruction.

For example, when translating x86-64-based instructions to the RISC-V architecture, you can define a structure so that the starting address of each data member is an integer multiple of its size. For example, if a structure contains a 4-byte integer and an 8-byte double-precision floating-point number, place the 4-byte integer first, ensuring its address is a multiple of 4, and the 8-byte double-precision floating-point number at the end, ensuring its address is a multiple of 8. This way, memory accesses naturally meet RISC-V's alignment requirements.

In summary, in the case of the above method, the first memory access address included in the target instruction can correspond to different address types. Specifically, the address type of the first memory access address included in the target instruction can be determined by determining whether the first memory access address satisfies the preset instruction template. The preset instruction template includes different instruction address types. When the first memory access address satisfies the first type in the preset instruction template, the address type of the first memory access address can be a preset unaligned memory access address. The preset unaligned memory access address is first an unaligned instruction. On this basis, the preset unaligned memory access address is also a fixed string of codes pre-set by the R&D personnel. For example, the unaligned memory access address can be set to 0x1003 in advance. That is to say, when the specific value of the memory access address included in the instruction is determined to be 0x1003, it can be determined that the first memory access address is the preset unaligned memory access address.

Accordingly, if the first memory access address satisfies the second type of the preset instruction template, the address type of the first memory access address may be an unaligned memory access address. An unaligned memory access address refers to a memory access operation in which the starting address of the access is not an integer multiple of the size of the accessed data type. For example, in a system requiring 4-byte alignment, if a 4-byte integer is to be accessed, its starting address should normally be a multiple of 4 (such as 0, 4, 8, etc.). If the starting address is 1, 2, or 3, which is not a multiple of 4, it is considered an unaligned memory access address.

When the address type of the first memory access address included in the target instruction is a preset unaligned memory access address, the memory access address stored in the register may be first obtained, and then the memory access address stored in the register may be used as the initial memory access address included in the target instruction. The target instruction is a stop instruction including the preset unaligned memory access address written at a corresponding instruction location obtained after translating the currently translated instruction, and the memory access address is the memory address included in the currently translated instruction.

And when it is determined that the address type of the first memory access address included in the target instruction is a non-aligned memory access address, the first memory access address is directly used as the initial memory access address included in the target instruction.

Then, for the two address types of the first memory access address, namely the preset non-aligned memory access address and the non-aligned memory access address, the memory slice corresponding to the initial memory access address may be remapped to obtain the mapped second memory access address.

Optionally, the memory capacity of the memory slice corresponding to the initial memory access address may be obtained first.

For example, the size of the free memory area to be allocated may be determined according to the size of data to be accessed by the memory area corresponding to the initial memory access address.

For example, in a system with a 4KB page size (2^12 bytes), assume that the process's current initial memory access address is 0x00001200 and needs to access 3KB of continuous data starting at this address. Since the page size is 4KB, the 3KB of data does not cross the page boundary and remains within the page with virtual page number 1. Therefore, the size of the free memory segment to be allocated is determined to be one page.

The cache can then be searched for a free memory slice that includes the memory capacity.

Alternatively, a system call function provided by the operating system (such as the mremap function of the system call for remapping a memory area in a Linux system) may be used to search for a free memory area that includes the memory capacity.

For example, first, the first starting address of the memory slice corresponding to the initial memory access address and the memory size of the memory slice corresponding to the initial memory access address can be obtained, and then the flag of the remapping behavior can be determined, wherein the flag is used to control the behavior of the remapping function mremap. Common flags include the MREMAP_MAYMOVE flag and the MREMAP_FIXED flag. The MREMAP_MAYMOVE flag is used to allow the operating system to move the mapping area to a new address. If this flag is not specified, the operating system cannot expand the mapping area at the original address, and the mremap remapping will fail; and the MREMAP_FIXED flag is used to indicate that the new mapping address will be specified by the additional parameter new_address (address parameter).

Specifically, if the MREMAP_MAYMOVE flag is set when using the mremap function, the mapping area (i.e., the memory slice corresponding to the initial memory access address) can be moved to the free memory slice, and if the MREMAP_FIXED flag is set when using the mremap function, the new mapping address (i.e., the second starting address of the free memory slice) can be specified by an additional parameter (new_address). When specifying a new mapping address, the mremap function can be called to move the memory slice corresponding to the initial memory access address to the free memory slice based on the memory size of the memory slice corresponding to the initial memory access address and the first starting address of the memory slice corresponding to the initial memory access address.

In one possible implementation, when the MREMAP_FIXED flag is specified, an additional parameter (new_address) may be used to specify a new mapping address (ie, the second starting address of the free memory area).

In another possible implementation, when the MREMAP_MAYMOVE flag is specified, the operating system will try to find a sufficiently large continuous free memory block at another location and copy the data of the original mapping area to the new location. At this time, the new starting address will be the second starting address of the free memory area found by the operating system.

In some embodiments, the memory access address of the free memory slice refers to an address generated after the memory slice corresponding to the initial memory access address is remapped to the corresponding memory slice in order to correctly access data in the remapped memory slice.

In this step, before generating the memory access address of the free memory slice, it is necessary to determine that the free memory slice has been successfully mapped. Specifically, it can be determined that the free memory slice has been successfully mapped by determining that the mremap operation has been successfully completed and the second starting address of the valid free memory slice has been obtained.

For example, you can check the return value of the mremap function to determine whether the mapping operation has been completed successfully. When the mremap function call is successful, it returns the starting address of the remapped memory area (that is, the second starting address of the free memory segment). When it fails, it returns MAP_FAILED (usually defined as (void *)-1). Therefore, you can check the return value to determine whether the operation is successful. If the second starting address of the returned free memory segment is not equal to MAP_FAILED, it means that the mremap mapping operation is successful, and the memory segment corresponding to the initial memory access address is remapped and successfully mapped to the free memory segment. At this time, you can continue to use the new mapping area free memory segment. Otherwise, if the second starting address of the returned free memory segment is equal to MAP_FAILED, it means that the mremap mapping operation failed, indicating that the remapping operation of the memory segment corresponding to the initial memory access address failed.

When it is determined that the free memory area has been successfully mapped, a memory access address of the free memory area may be generated.

For example, first, the offset of the memory address to be accessed relative to the first starting address can be determined, where the first starting address is the starting address of the memory slice corresponding to the initial memory address; then the second starting address of the free memory slice can be added to the offset to obtain the memory address of the free memory slice, and the memory address of the free memory slice is the second memory address.

In some embodiments, when the memory slice corresponding to the initial memory access address is remapped, the first starting address of the memory slice corresponding to the initial memory access address may be mapped to the second starting address of the free memory slice.

For example, on a system with a page size of 4KB (or 2^12 bytes), a process has the following initial virtual address to physical address mapping:

Assume that the process's current initial memory access address is 0x00001200, and it needs to access 3KB of continuous data starting at this address. Since the page size is 4KB, the 3KB of data does not cross the page boundary and remains within the page with virtual page number 1. Now, suppose that the system needs to adjust the virtual address range of this data, for example, mapping it to the new virtual address range 0x00008000-0x00008FFF.

First, by looking up the mapping relationship, we can know that the physical page frame number corresponding to the current virtual page number 1 is 5. Then, a new mapping entry is added to the page table, and the virtual page number corresponds to the new virtual address range (here the new virtual page number can be set to 8, corresponding to the virtual address 0x00008000-0x00008FFF), and it is mapped to the original physical page frame number 5; at the same time, since the mapping of the original virtual address range 0x00001000-0x00001FFF to the physical page frame number 5 is no longer needed, the mapping entry can be deleted from the page table (or marked as invalid).

In this way, when the process subsequently accesses an address in the new virtual address range 0x00008000-0x00008FFF, the memory management unit (MMU) will correctly map it to the physical address 0x00005000-0x00005FFF based on the updated page table, thereby achieving remapping of the virtual address based on the data size corresponding to the initial memory access address (without crossing pages) without changing the physical page.

Through the above operations, the system can complete the remapping of the virtual address according to the data size corresponding to the initial memory access address without changing the physical page, so that the process can access the data on the original physical page through the new virtual address range.

It should be noted that after generating the corresponding second memory access address based on the first memory access address included in the target instruction, the memory area corresponding to the first memory access address can be configured as inaccessible. This can prevent other threads of the program from accessing the first memory access address when the program logic shifts to using the newly generated second memory access address for data access, thereby avoiding reading or writing erroneous data, causing program crashes, data corruption, and other problems. For example, in a complex multi-threaded program, different threads share memory resources. If the old memory access address area is not set to inaccessible, a thread may mistakenly operate on the area, resulting in data inconsistency.

Specifically, when other threads of the program access the first memory access address, if the operating system recognizes that the first memory access address is inaccessible due to the execution of the scheme included in this application, it will provide an access error signal for the first memory access address so that other threads of the program can trigger the access error signal when accessing the first memory access address. When the operating system detects the access error signal, it can control the other threads of the program to be in a stop waiting state, and continue to access the first memory access address periodically until the access error signal is no longer triggered and the first memory access address is accessed normally.

In this way, the present application can generate a corresponding second memory access address based on the first memory access address included in the target instruction, and configure the memory slice corresponding to the first memory access address as inaccessible. In this way, during the execution process, only the current instruction execution logic can operate on the memory data corresponding to the first memory access address included in the target instruction, and other instruction execution logics involving the corresponding memory data in the target instruction cannot operate. In this way, the data competition problem caused by different instruction execution logics operating on the same data at the same time can be avoided.

For example, each thread has its own address space or a clear access range within the shared address space. When a thread is remapped to a second memory address for memory access due to a memory alignment exception, its operation is performed within its own memory access permissions and range, and will not interfere with other threads' normal access to other memory addresses. For example, in a multi-threaded database management system, a thread encounters a memory alignment exception when processing a data query and remaps the address to access data, while other threads may be inserting or updating data at other memory addresses. The memory access between them is independent of each other and does not affect each other, so there is no need to stop other threads.

Since only the current instruction execution logic can operate the data corresponding to the second memory access address, the consistency of the data can be ensured when it is accessed and modified, so that the program will not produce erroneous results due to the interference of multiple execution logics when processing these data. There is no need to stop the continued execution of other instruction execution logics. Other threads that do not involve the first memory access address data operation can continue to execute unaffected tasks, thereby avoiding unnecessary thread blocking and improving the concurrency performance of the entire system and the efficiency of source program instruction translation and execution.

By adopting the above technical solution, the multi-threaded program can handle the changes in the memory access address status in an orderly manner, which not only ensures that there will be no blind operation when the address is inaccessible, but also ensures that normal access can be restored in time when the address becomes available again.

Step 103: Perform a memory access operation on the second memory access address to access data at the second memory access address.

By adopting the above technical solution, the memory access address of the memory slice can be remapped according to the first memory access address with memory access alignment exception, and the non-aligned memory access can be converted into a memory access operation based on the new address (the second memory access address). In this way, the entire memory access process can be executed as an atomic operation, avoiding interference from other threads or processes; and the memory slice corresponding to the first memory access address is configured as inaccessible. This solution does not need to stop other threads, but solves the memory alignment problem by remapping the memory. For other threads that are not involved in data operations in the first memory slice, they can continue to execute unaffected tasks, reducing unnecessary thread blocking and scheduling overhead, thereby improving the overall execution efficiency, improving the concurrency performance of the entire system and the efficiency of source program instruction translation and execution.

FIG2 is a flowchart of a binary translation method provided in an embodiment of the present application, comprising the following steps:

Step 201 : Translate each basic block included in the source program in the client, and translate the instructions included in each basic block into instructions corresponding to the host architecture.

The source program may represent an application developed based on a source architecture platform (client architecture platform). That is, the source program is a program developed based on a first instruction set architecture and includes a plurality of basic blocks, where a basic block refers to a sequence of instructions executed sequentially in the source program.

First, when it is necessary to run the source program developed based on the source architecture platform on the target architecture platform, the source architecture instructions in each basic block included in the source program can be translated into target architecture instructions in real time based on the instructions actually executed on the basic block.

For example, for instructions in each basic block, the guest instructions may be mapped to host instructions according to the instruction set manuals of the guest and host machines.

Specifically, the opcode of the client instruction can be first converted to the opcode of the host instruction. For example, the ADD instruction of the client corresponds to the ADD instruction of the host.

The operands of the guest instructions can then be converted. The operands are operands used to process the instructions, and may include registers, memory addresses, and immediate values. The conversion can be performed based on the host's register naming rules and memory access methods.

For example, register operands vary depending on the instruction set architecture. Different instruction set architectures typically have different register names and numbers. For example, the ARM architecture has general-purpose registers such as R0-R15, while the x86 architecture has general-purpose registers such as EAX, EBX, ECX, and EDX. Therefore, a register mapping table can be established to map guest register names to host register names, thereby obtaining register operands in host instructions. Regarding memory operands, different architectures have different memory access methods (such as endianness and alignment requirements), as well as different memory address representation and calculation methods. For example, some architectures use big-endian byte order, while others use little-endian byte order. Some architectures also have strict address alignment requirements for memory accesses. Therefore, if the guest and host have different endianness, endian conversion may be required during memory read and write operations. Furthermore, if the guest and host have different memory address representation and calculation methods, the memory address in the guest instruction can be adjusted according to the host's memory address calculation rules. For example, some architectures require adding the value of a base register or performing an offset calculation to the memory address.

After translating the opcode and operands of the guest instructions, control flow processing of the instruction sequence can proceed. For jump and branch instructions, it is necessary to ensure that the translated instructions correctly implement the same control flow logic. For example, the guest's JMP instruction (jump instruction) must be translated into the corresponding jump instruction on the host, and the target address must be correctly translated.

When the above operation flow is adopted, the instructions included in each basic block can be translated into instructions corresponding to the host machine architecture.

Step 202: Obtain the encoding length of the memory access address in the instruction currently translated by the translator.

In this step, since different instruction set architectures have different instruction encoding formats, the currently translated instruction can be parsed according to the specification of the instruction set corresponding to the current client architecture to determine the location and encoding method of the memory access address in the instruction. After parsing the instruction, the field representing the memory access address is found. The location and length of this field vary depending on the architecture, so once the memory access address field is determined, the encoding length of the memory access address can be directly identified.

For example, take an x86 memory access instruction 0x8B 0x0D 0x12 0x34 0x56 0x78 as an example. This is a MOV instruction used to move data from memory to a register.

For 0x8B, this opcode usually corresponds to the MOV instruction, which moves the value of one operand to another operand.

For 0x0D, the binary representation is 00001101, where Mod = 00, Reg = 001, and R/M = 101. According to the combination of Mod and R/M, this indicates that a 32-bit offset is used to calculate the memory address. Reg = 001 usually corresponds to register ECX, which means that the target register is ECX.

For 0x12 0x34 0x56 0x78, it means the offset is 0x78563412. Then, when the encoding length of "0x8B 0x0D 0x12 0x34 0x56 0x78" is obtained, it can be determined that the encoding length of the initial memory access address in this instruction is 32 bits (4 bytes).

Step 203: When the encoding length is greater than or equal to the encoding length corresponding to the host architecture, it is determined that a memory access alignment exception exists in the currently translated instruction.

The encoding length corresponding to the host architecture refers to the memory address encoding length specified by the architecture of the target computer system running the translated instructions. This is determined by the architecture's hardware design and memory management mechanisms. For example, in the 32-bit x86 architecture, 32-bit encoding is typically used to represent memory addresses, while in the 64-bit x86-64 architecture, 64-bit encoding is used.

When the encoding length of the memory address included in the currently translated instruction is greater than or equal to the encoding length corresponding to the host architecture, such as the x86-64 instruction cmpxchg16b (which performs a 16-byte (128-bit) compare-and-swap operation), atomic instructions of up to 128 bits (16 bytes) can be supported. When translating x86-64 instructions to the RISC-V architecture, there are cases where the atomicity of the translated RISC-V instructions cannot be guaranteed.

Step 204: Store the initial memory access address included in the currently translated instruction in a predetermined preset register.

In this step, if it is determined that the currently translated instruction has a memory access alignment exception, the memory access address included in the currently translated instruction may be stored in a predetermined preset register.

Registers are high-speed storage units within the CPU (processor) that can be quickly accessed by the CPU. Storing the memory address in a register allows the CPU to quickly retrieve the address, facilitating the subsequent generation of stop instructions and execution of related operations.

Step 205 : Writing a stop instruction including a preset non-aligned memory access address into the translation result at the corresponding instruction position obtained after the currently translated instruction is translated.

The purpose of the stop instruction is to interrupt the normal execution flow of the program at a specific moment. By setting its memory access address to a preset non-aligned memory access address, the system's handling mechanism for non-aligned memory access can be used to trigger an exception.

In this step, after storing the memory access address included in the currently translated instruction in the register, a stop instruction may be generated. The memory access address corresponding to the stop instruction is a preset non-aligned memory access address. When the translation result is executed, the stop instruction is executed. When the preset non-aligned memory access address is accessed, an execution stop signal is triggered. The execution stop signal is a SIGBUS signal (bus error signal). When the SIGBUS signal is triggered, execution of the translation result may be stopped.

Considering that some host architectures require memory access address alignment, if the memory access address included in the current translated instruction has a memory access alignment anomaly, when executing the translated instruction sequence on these host architectures, if the corresponding instruction after the current instruction is directly executed, the host architecture system will not forcibly terminate the program and will continue to execute subsequent instructions. However, in this case, the program will perform calculations based on incorrect memory data, resulting in incorrect results.

Therefore, when there is a memory access alignment exception in the memory access address included in the currently translated instruction, a stop instruction including the preset non-aligned memory access address can be written at the corresponding instruction position obtained after the translation of the currently translated instruction. In this way, when these host architectures execute the translated instruction sequence, the stop instruction is synchronously executed at the translated instruction position, and the normal execution process of the program is terminated to avoid the program from performing calculations based on erroneous memory data, thereby preventing erroneous results.

Step 206: Use the stop instruction as the target instruction.

Step 207 : When the address type of the memory access address in the currently translated instruction is a non-aligned memory access address, it is determined that the currently translated instruction has a memory access alignment exception.

In this step, it is first detected whether the memory access address included in the currently translated instruction is a non-aligned memory access address.

For example, during instruction translation, the system checks each instruction involving memory access. This check typically involves calculating the instruction's memory access address modulo the number of bytes aligned for the corresponding data type. If the result is non-zero, it indicates that the memory access address is unaligned, and the instruction is the target of a memory access alignment exception.

For example, for an instruction accessing a 32-bit integer, if the memory access address modulo 4 is not 0, it means that the address is not an integer multiple of 4, that is, the address is not accessed in a 4-byte aligned manner, and it can be determined that the instruction has a memory access alignment exception.

Then, when it is detected that the memory access address included in the currently translated instruction is a non-aligned memory access address, it is determined that the currently translated instruction has a memory access alignment exception.

Step 208: Translate the currently translated instruction to obtain the target instruction.

In this step, the currently translated instruction may be translated according to a translation method for memory access address alignment to obtain the target instruction including a non-aligned memory access address.

Considering that some host architectures, while requiring memory access address alignment, still have some degree of support for unaligned memory accesses, when encountering instructions with memory access alignment exceptions, the hardware can automatically handle unaligned accesses. For example, it can split a single unaligned memory access into multiple aligned memory access operations, reading or writing data from different memory blocks, and then recombining them.

Therefore, the currently translated instruction may continue to be translated according to the translation method of memory access address alignment to obtain the target instruction including the non-aligned memory access address.

Although the target instruction obtained here still includes non-aligned memory access addresses, when these host architectures execute the translated instruction sequence, they can directly execute the instructions corresponding to the current instruction after translation. The program will not stop immediately due to memory alignment exceptions during execution. However, due to the process of multiple accesses and data combinations, the results of data reading or writing will be erroneous, affecting the correctness of the program.

However, in combination with the implementation method of step 102 in the present application, the problem here can be eliminated. This is because the present application can generate a corresponding second memory access address based on the first memory access address included in the target instruction, and configure the memory slice corresponding to the first memory access address to be inaccessible. In this way, during the execution process, only the current instruction execution logic can operate on the memory data corresponding to the first memory access address included in the target instruction, and other instruction execution logics involving the corresponding memory data in the target instruction cannot operate. In this way, the data competition problem caused by different instruction execution logics operating on the same data at the same time can be avoided.

For example, each thread has its own address space or a clear access range division within the shared address space. When a thread is remapped to a second memory access address for memory access due to a memory alignment exception, its operation is performed within its own memory access rights and range, and will not interfere with other threads' normal access to other memory addresses. For example, in a multi-threaded database management system, a thread encounters a memory alignment exception when processing a data query and remaps the address to access data, while other threads may be inserting or updating data at other memory addresses. The memory access between them is independent of each other and does not affect each other, so there is no need to stop these threads that are inserting or updating data at other memory addresses.

Since only the current instruction execution logic can operate the data corresponding to the second memory access address, the consistency of the data can be ensured when it is accessed and modified, so that the program will not produce erroneous results due to the interference of multiple execution logics when processing these data. There is no need to stop the continued execution of other instruction execution logics. Other threads that do not involve the first memory access address data operation can continue to execute unaffected tasks, thereby avoiding unnecessary thread blocking and improving the concurrency performance of the entire system and the efficiency of source program instruction translation and execution.

FIG3 is another binary translation method provided in an embodiment of the present application, comprising the following steps:

Step 301: Obtain the translation result of each basic block from the cache of the translator.

In this step, the implementation method can be shown in the implementation method of the above step 101, and the specific implementation steps are not repeated here.

Step 302: During the execution of the instructions in the translation result, synchronously detect an execution stop signal.

In this step, the current instruction in the translation result may be executed, and then an execution stop signal may be detected during the execution process.

During instruction execution, various exceptions, such as memory access errors and divide-by-zero errors, can occur. These often trigger corresponding stop-execution signals. By detecting these signals, the program can promptly detect and respond to errors, facilitating debugging and problem location. For example, when a memory alignment exception triggers a SIGBUS (bus error) signal, the program can capture and handle it accordingly, preventing a program crash.

For example, during the execution of the current instruction in the translation result, if an execution stop signal is triggered due to various abnormal situations, a tool and mechanism for monitoring the execution status of the program can be used to detect the execution stop signal.

For example, during debugging, a debugger (such as GDB) may be used to monitor the execution of a program to receive an execution stop signal.

In some embodiments, during the execution of instructions, the system will check each instruction involving memory access. The checking method is usually to calculate the memory access address of the instruction modulo the number of alignment bytes of the corresponding data type. If the result is not zero, it means that the memory access address does not meet the alignment requirements. At this time, this instruction is the target instruction with a memory access alignment exception. Or when checking each instruction involving memory access, if the bit width of the memory access address in the instruction is greater than the maximum bit width supported by the host architecture, it means that the memory access address cannot be addressed and accessed in a normal and effective manner under the host architecture, which means that under the memory management and access rules of the host architecture, the address that the instruction attempts to access exceeds the range allowed by the architecture, which means that the instruction is a target instruction with a memory access alignment exception.

For example, for an instruction accessing a 32-bit integer, if the modulo 4 of the memory access address is not 0, it is determined that the instruction has a memory access alignment exception.

For example, the guest architecture uses 64-bit encoding to represent memory addresses, while the host architecture is 32-bit and can only process 32-bit memory addresses. When the memory address in the guest instruction exceeds the range that can be represented by 32 bits, the host cannot correctly process the address, causing alignment issues. Similarly, the instruction can be determined to have a memory alignment exception.

Then, when the execution stop signal is detected, if it is determined that the stop instruction that triggers the execution stop signal is an instruction with a memory access alignment exception, steps 303 to 312 are executed.

In some embodiments, when the execution stop signal is detected, the stop instruction that generates the execution stop signal can be first obtained; if it is determined that the stop instruction that triggers the execution stop signal is an instruction without a memory alignment exception, the associated function corresponding to the stop instruction can be obtained and executed, thereby also achieving the effect of stopping the execution of the translation result.

Therefore, when the execution stop signal is detected, if it is determined that the stop instruction that triggers the execution stop signal is an instruction without a memory access alignment exception, step 313 is executed.

In the case where it is determined that the address type of the first memory access address included in the target instruction is a preset non-aligned memory access address, executing steps 303, 304, and 306-312;

In the case where it is determined that the address type of the first memory access address included in the target instruction is an unaligned memory access address, executing steps 305-312;

Step 303: Obtain a memory access address in a preset register.

In this step, when it is determined that the address type of the first memory access address included in the target instruction is a preset non-aligned memory access address, the memory access address stored in the register can be obtained.

The preset unaligned memory access address is a pre-set address that does not comply with the system memory alignment rules. The purpose of the execution stop signal is to interrupt the normal execution flow of the program at a specific moment. The memory access address stored in the register is the memory access address included in the corresponding instruction in the source program before the instruction at the target instruction location is translated.

Considering that the first memory access address included in the target instruction is a pre-set preset unaligned memory access address, this is because the instruction bit width of the initial memory access address included in the corresponding instruction in the basic block of the target instruction before translation is greater than the maximum bit width supported by the host architecture. Although the memory access address alignment can be guaranteed in some cases, there are cases where the atomicity of the host instruction cannot be guaranteed after translation. Therefore, in this case, the preset unaligned memory access address can be stored in a register, and the instruction including the preset unaligned memory access address can be written to the corresponding instruction position obtained after the current translated instruction is translated. In this way, the characteristic that the preset unaligned memory access address can trigger the execution stop signal can be utilized to enable the subsequent steps of this application to ensure the atomicity of the translated instruction.

In program design, if an instruction including the preset non-aligned memory access address is executed, an execution stop signal can be proactively triggered. When the execution stop signal is detected and it is found that the memory access address of the target instruction is the preset non-aligned memory access address, it indicates that the program has encountered an expected exception. The memory access address stored in the register can be obtained from the register according to the expected set steps.

Step 304: Use the memory access address as the initial memory access address in the target instruction.

Optionally, the memory access address stored in the register is used as the initial memory access address included in the target instruction.

In this step, during the execution of the instruction, when an execution stop signal is detected and it is determined that the target instruction that triggers the signal contains a preset non-aligned memory access address, the memory access address in the target instruction is replaced with the memory access address stored in the register, wherein the target instruction is a stop instruction including a preset non-aligned memory access address written at the corresponding instruction position obtained after the currently translated instruction is translated. The stop instruction of the preset non-aligned memory access address adopts the stop instruction adopted in the embodiment shown in Figure 2. In this way, it can be ensured that the memory access address that the corresponding instruction in the source program itself needs to access is adopted in the subsequent execution steps. By obtaining and using the correct memory access address, the consistency of the program logic can be guaranteed, so that the program can complete various tasks as expected by the developer.

Step 305: Use the first memory access address as the initial memory access address in the target instruction.

In this step, when it is determined that the address type of the first memory access address included in the target instruction is a non-aligned memory access address, the first memory access address can be directly used as the initial memory access address included in the target instruction.

Step 306: Obtain the memory capacity of the memory area corresponding to the initial memory access address.

For example, the size of the free memory area to be allocated may be determined according to the size of data to be accessed by the memory area corresponding to the initial memory access address.

For example, in a system with a 4KB page size (2^12 bytes), assume that the process's current initial memory access address is 0x00001200 and needs to access 3KB of continuous data starting at this address. Since the page size is 4KB, the 3KB of data does not cross the page boundary and remains within the page with virtual page number 1. Therefore, the size of the free memory segment to be allocated is determined to be one page.

In this embodiment, the memory capacity corresponding to the memory data is obtained in the following manner:

Method 1: Analyze instruction opcodes;

The opcode of an instruction defines the specific operation to be performed by the instruction. Different opcodes have different requirements for data access methods and data capacity.

If the opcode is a load instruction, you need to further examine the instruction's operands to determine whether it is loading a byte, a word (usually 2 bytes), a doubleword (usually 4 bytes), or a larger data type. For example, on some architectures, the LOADB instruction indicates a byte load, while LOADW indicates a word load. Alternatively, if the opcode is a store instruction, the size of the data to be stored can be determined from the opcode. For example, STOREQ indicates a store of an 8-byte quadword.

Method 2: Consider operands and addressing modes;

The operands and addressing modes of the instruction can provide more information about the memory address and data capacity.

If an instruction contains an immediate operand, it indicates the offset or length of the data to be accessed. For example, the instruction LOAD R1, [R2 + #4] loads data from the address obtained by adding 4 to the value of register R2. The 4 here is the offset, and the data type must be considered to determine the capacity of the data to be loaded.

In register indirect addressing mode, the register value is the memory address to be accessed. The instruction context and other relevant information are required to determine the data range to be accessed. For example, if register R3 points to the first address of an array, the instruction LOAD R4, [R3] loads the first element of the array. The data type of the array element is required to determine the data capacity to be loaded.

Step 307: Search the cache for a free memory area including the memory capacity.

Alternatively, a system call function provided by the operating system (such as the mremap function of the system call for remapping a memory area in a Linux system) may be used to search for a free memory area that includes the memory capacity.

For example, first, the first starting address of the memory slice corresponding to the initial memory access address and the memory size of the memory slice corresponding to the initial memory access address can be obtained, and then the flag of the remapping behavior can be determined, wherein the flag is used to control the behavior of the remapping function mremap. Common flags include the MREMAP_MAYMOVE flag and the MREMAP_FIXED flag, wherein the MREMAP_MAYMOVE flag is used to allow the operating system to move the mapping area to a new address. If this flag is not specified, the operating system cannot expand the mapping area at the original address, and the mremap remapping will fail; and the MREMAP_FIXED flag is used to indicate that the new mapping address will be specified by the additional parameter new_address (address parameter).

Specifically, if the MREMAP_MAYMOVE flag is set when using the mremap function, the mapping area (i.e., the memory slice corresponding to the initial memory access address) can be moved to the free memory slice, and if the MREMAP_FIXED flag is set when using the mremap function, the new mapping address (i.e., the second starting address of the free memory slice) can be specified by an additional parameter (new_address). When specifying a new mapping address, the mremap function can be called to move the memory slice corresponding to the initial memory access address to the free memory slice based on the memory size of the memory slice corresponding to the initial memory access address and the first starting address of the memory slice corresponding to the initial memory access address.

In one possible implementation, when the MREMAP_FIXED flag is specified, an additional parameter (new_address) may be used to specify a new mapping address (ie, the second starting address of the free memory area).

In another possible implementation, when the MREMAP_MAYMOVE flag is specified, the operating system will try to find a sufficiently large continuous free memory block at another location and copy the data of the original mapping area to the new location. At this time, the new starting address will be the second starting address of the free memory area found by the operating system.

Step 308: Obtain a first starting address of the memory area corresponding to the initial memory access address, and obtain a second starting address of the free memory area.

For example, the memory area corresponding to the initial memory access address is in pages, with a page size of 4KB (i.e., 2 ¹² bytes). Assuming the initial memory access address is 0x10023, to obtain the first starting address of the memory area corresponding to the initial memory access address, you can calculate it by dividing the address by the page size. For example, page number = 0x10023 ÷ 4KB = 4 (the division here is integer division). The first starting address = 4 × 4KB = 0x10000. In other words, the starting address of the memory area (page) containing address 0x10000 is 0x10000.

When obtaining the second starting address of the free memory segment, a free memory linked list can be first determined. The linked list nodes store the starting address and size of each free memory segment. When a free memory segment needs to be allocated, the linked list is traversed to find a free memory segment of the appropriate size. For example, if a node in the linked list represents a free memory segment with a size of 8KB and a starting address of 0x20000, then 0x20000 is the second starting address of the free memory segment we obtained.

Step 309: Calculate the offset of the initial memory access address relative to the first start address.

The offset represents the distance between the initial memory access address and the start address within the memory slice to which it belongs. This offset can be obtained by subtracting the first start address from the initial memory access address.

For example, assuming the first starting address is 0x10000 and the initial memory access address is 0x10023, the offset = initial memory access address - first starting address = 0x10023 - 0x10000 = 0x23.

Step 310: Add the offset to the second starting address to obtain a memory access address for the free memory area.

The memory access address of the free memory slice refers to an address generated after the memory slice corresponding to the initial memory access address is remapped to the corresponding memory slice in order to correctly access data in the remapped memory slice.

In this step, before generating the memory access address of the free memory slice, it is necessary to determine that the free memory slice has been successfully mapped. Specifically, it can be determined that the free memory slice has been successfully mapped by determining that the mremap operation has been successfully completed and the second starting address of the valid free memory slice has been obtained.

For example, you can check the return value of the mremap function to determine whether the mapping operation has been completed successfully. If the mremap function call is successful, it will return the starting address of the remapped memory area (that is, the second starting address of the free memory segment). If it fails, it will return MAP_FAILED (usually defined as (void *)-1). Therefore, you can check the return value to determine whether the operation is successful. If the second starting address of the returned free memory segment is not equal to MAP_FAILED, it means that the mremap mapping operation is successful, indicating that the memory segment corresponding to the initial memory access address has been remapped and successfully mapped to the free memory segment. At this time, you can continue to use the new mapping area free memory segment. Otherwise, if the second starting address of the returned free memory segment is equal to MAP_FAILED, it means that the mremap mapping operation failed, indicating that the remapping operation of the memory segment corresponding to the initial memory access address failed.

When it is determined that the free memory area has been successfully mapped, a memory access address of the free memory area may be generated.

For example, first, the offset of the memory address to be accessed relative to the first starting address can be determined, where the first starting address is the starting address of the memory slice corresponding to the initial memory access address; then the second starting address of the free memory slice can be added to the offset to obtain the memory address of the free memory slice.

For example, assuming the first starting address is 0x10000 and the initial memory access address is 0x10023, the offset is calculated to be 0x10023 - 0x10000 = 0x23. Furthermore, the second starting address of the free memory segment is known to be 0x20000. Therefore, the memory access address of the free memory segment = the second starting address + the offset = 0x20000 + 0x23 = 0x20023.

Step 311: Use the memory access address of the free memory area as the remapped second memory access address.

Step 312: Perform a memory access operation on the second memory access address to access data at the second memory access address.

In this step, if the target instruction that triggers the execution stop signal, the corresponding pre-translation instruction in the pre-translation basic block is an atomic read operation, and the data can be re-read from the second memory access address and then stored in the destination register of the pre-translation instruction.

For example, each thread has its own address space or a clear access range within the shared address space. When a thread is remapped to a second memory address for memory access due to a memory alignment exception, its operation is performed within its own memory access permissions and range, and will not interfere with other threads' normal access to other memory addresses. For example, in a multi-threaded database management system, a thread encounters a memory alignment exception when processing a data query and remaps the address to access data, while other threads may be inserting or updating data at other memory addresses. The memory access between them is independent of each other and does not affect each other, so there is no need to stop other threads.

If the target instruction that triggers the execution stop signal has a corresponding pre-translation instruction in the pre-translation basic block that is an atomic write operation, data can be obtained from the source register of the pre-translation instruction and then written using the second memory access address.

Specifically, when writing data into the destination register of the pre-translation instruction, or when writing data using the second memory access address, the characteristics of the signal processing flow of the operating system are utilized.

When a stop signal is triggered, the operating system kernel places the register context of the target instruction that triggered the signal in a section of memory accessible to user mode. The user program can access this register context from the parameters of the signal handler function. For example, the ucontext_t structure in the signal handler function parameters in Linux can be used to obtain register context information. When the signal handler function completes, the kernel restores the register values in this section of memory to the hardware registers.

Therefore, this application can take advantage of the characteristics of the signal processing function and use ucontext_t to replace the host machine instruction that triggered the exception to complete the read and write operations. After completing the read and write, the original memory address is restored to end the signal processing process and continue to execute the next instruction that triggered the exception.

Step 313: Obtain the associated function corresponding to the stop instruction, and execute the associated function respectively.

For example, when a binary program based on the x86 architecture is translated and run on the host architecture, the memory access address included in the target instruction can be set to 0xFFFF0000, which is a 4-byte aligned address that meets the alignment requirements of the int type and corresponds to a physical memory page that is not allocated to the current process. Under the x86 architecture, virtual addresses need to be mapped to actual physical memory pages before they can be accessed. When an attempt is made to access an address that does not have a valid physical memory mapping, the hardware will detect this error and trigger a SIGBUS signal. When the x86 binary program is translated to the host architecture, the host's memory management mechanism cannot correctly handle the mapping of this virtual address, resulting in an error.

In this implementation, during the program execution of the translation result, if an execution stop signal is detected and the memory access address included in the target instruction is obtained and is set to 0xFFFF0000, the memory access address is a 4-byte aligned address, which meets the alignment requirement of the int type, but corresponds to a physical memory page that is not allocated to the current process. This situation will trigger the execution stop signal, so the associated function corresponding to the memory access address 0xFFFF0000 can be found and executed in the program, that is, jumping to the error handler to respond to the current stop signal.

Specifically, the stop instruction can trigger a stop execution signal, and the processing function corresponding to the stop execution signal includes specific processing steps. Therefore, when the stop instruction is an instruction that does not include a memory access address with a memory access alignment exception, the execution steps corresponding to the processing function corresponding to the stop instruction can be obtained, and the execution steps included in the processing function can be executed.

In this embodiment, since each signal usually has a corresponding processing function in the program, the stop execution signal is also associated with a specific processing function. The processing function includes a series of specific operation steps. These steps define the subsequent execution operations of the program after receiving the stop execution signal. For example, it may include saving the current program running status, cleaning up resources, closing related connections, and other operations.

For example, you can define a processing function called handle_stop_signal, which can include a series of operation steps for processing the program after receiving the stop execution signal. The specific operation steps are as follows:

S1. Save the current program running status;

The data packet number currently being processed, processing progress and other information can be saved to a log file for subsequent recovery.

S2. Clean up resources;

The memory space, buffer and other resources occupied by the thread can be released.

S3. Close the relevant connection;

You can close the connection with the network server to avoid resource waste and data leakage.

Optionally, in a data processing program, the stop instruction can be used to end the execution of a thread under specific conditions. When it is detected that the stop instruction is an instruction that does not include a memory access address with a memory access alignment exception, the processing function corresponding to the stop instruction can be executed. The function includes execution steps such as saving unprocessed data and closing thread resources.

For example, when the program detects a stop instruction, it can determine whether the memory access address of the instruction has an alignment exception. Assume that there is a thread dedicated to processing TCP packets. When a stop instruction is received and the memory access address of the instruction does not have an alignment exception, the processing function corresponding to the stop instruction is executed. The specific steps are as follows:

T1. Save unprocessed data;

The remainder of the TCP packet currently being processed can be saved to a temporary file for later reprocessing.

T2. Close thread resources;

You can terminate the thread and release the CPU and memory resources occupied by the thread.

Furthermore, a mapping table (such as a dictionary or array) can be used to store the association between the memory access address without a memory alignment exception and the corresponding error handling function. When a stop signal is detected and the memory access address without a memory alignment exception of the stop instruction is obtained, the corresponding error handling function is found and executed by querying the mapping table.

For example, using Python programming code as an example, the dictionary error_handler_mapping can be used to store the mapping between the memory access address of the memory alignment exception and the error handling function. After obtaining the memory access address of the memory alignment exception of the stop instruction, the in operator is used to check whether the memory access address of the memory alignment exception does not exist in the dictionary. If so, the corresponding function is called.

In the example of C language programming code, a structure called ErrorHandlerMapping is defined to store the memory address and corresponding function pointer for memory alignment exceptions, and an array called error_handler_mappings is used to store all mappings. This way, the array can be traversed to find the item that matches the stop instruction and call the corresponding function.

In this way, execution stop signals from different sources can be handled flexibly, ensuring that the program can respond and handle correctly in various situations.

In summary, in the binary translation method of the present application, the memory access address of the memory slice can be remapped according to the first memory access address with a memory access alignment exception, and the non-aligned memory access can be converted into a memory access operation based on the new address (the second memory access address). In this way, the entire memory access process can be executed as an atomic operation, avoiding interference from other threads or processes; and the memory slice corresponding to the first memory access address is configured as inaccessible. This solution does not need to stop other threads, but solves the memory alignment problem by remapping the memory. Other threads that are not involved in data operations in the first memory slice can continue to execute unaffected tasks, reducing unnecessary thread blocking and scheduling overhead, thereby improving the overall execution efficiency, the concurrency performance of the entire system, and the efficiency of source program instruction translation and execution.

FIG4 is a block diagram of a binary translation device provided in an embodiment of the present application. As shown in FIG4 , the device 400 includes:

A first acquisition module 401 is configured to acquire the translation result of each basic block from the cache of the translator;

A generating module 402 is configured to, when executing an instruction in the translation result, if it is determined that the currently executed instruction is a target instruction with a memory access alignment exception, remap the target instruction according to a first memory access address included in the target instruction to generate a second memory access address, and configure a memory slice corresponding to the first memory access address as inaccessible;

The execution module 403 is configured to execute a memory access operation on the second memory access address to access data at the second memory access address.

Optionally, the generation module 402 is used to synchronously detect an execution stop signal during the execution of the instructions in the translation result; when the execution stop signal is detected, if it is determined that the stop instruction that triggers the execution stop signal is an instruction with a memory access alignment exception, then the currently executed instruction is the target instruction, so that the execution of the translation result is stopped.

Optionally, the generation module 402 is configured to obtain an initial memory access address in the target instruction according to the address type of the first memory access address; and remap the memory slice corresponding to the initial memory access address to obtain the second memory access address.

Optionally, the generation module 402 is used to obtain the memory access address in the preset register when the address type is a preset non-aligned memory access address; the target instruction is a stop instruction including the preset non-aligned memory access address written at the corresponding instruction position obtained after the translation of the currently translated instruction, and the memory access address is the memory access address included in the currently translated instruction; and the memory access address is used as the initial memory access address in the target instruction.

Optionally, the generating module 402 is configured to use the first memory access address as the initial memory access address in the target instruction when the address type is a non-aligned memory access address.

Optionally, the generation module 402 is used to obtain the memory capacity of the memory slice corresponding to the initial memory access address; search for a free memory slice including the memory capacity in the cache, and generate a memory access address of the free memory slice; and use the memory access address of the free memory slice as the remapped second memory access address.

Optionally, the generation module 402 is used to obtain the first starting address of the memory slice corresponding to the initial memory access address, and obtain the second starting address of the free memory slice; and obtain the memory access address of the free memory slice based on the first starting address and the second starting address.

Optionally, the device further includes:

A second acquisition module is used to obtain the encoding length of the memory access address in the instruction currently translated by the translator;

A first determining module is configured to determine that a memory access alignment exception exists in the currently translated instruction when the encoding length is greater than or equal to the encoding length corresponding to the host architecture;

The second determining module is configured to determine the target instruction after translation according to the currently translated instruction.

Optionally, the second determination module is used to write a stop instruction including a preset non-aligned memory access address at the corresponding instruction position obtained after the translation of the currently translated instruction; and store the initial memory access address included in the currently translated instruction in a predetermined preset register; and use the stop instruction as the target instruction.

Optionally, the device further includes:

A third acquisition module is used to obtain the instruction currently translated by the translator;

The third determining module is used to determine that the currently translated instruction has a memory access alignment exception when the address type of the memory access address in the currently translated instruction is a non-aligned memory access address, and translate the currently translated instruction to obtain the target instruction.

In summary, this embodiment can remap the memory access address of the memory slice according to the first memory access address with memory access alignment exception, and convert the non-aligned memory access into a memory access operation based on the new address (the second memory access address). In this way, the entire memory access process can be executed as an atomic operation, avoiding interference from other threads or processes; and the memory slice corresponding to the first memory access address is configured as inaccessible. This solution does not need to stop other threads, but solves the memory alignment problem by remapping the memory. Other threads that are not involved in data operations in the first memory slice can continue to execute unaffected tasks, reducing unnecessary thread blocking and scheduling overhead, thereby improving overall execution efficiency, improving the concurrency performance of the entire system and the efficiency of source program instruction translation and execution.

5 is a block diagram of an electronic device 500 according to an exemplary embodiment. For example, the electronic device 500 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

5 , electronic device 500 may include one or more of the following components: a processing component 502 , a memory 504 , a power component 506 , a multimedia component 508 , an audio component 510 , an input/output interface 512 , a sensor component 514 , and a communication component 516 .

The processing component 502 generally controls the overall operation of the electronic device 500, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 502 may include one or more processors 520 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 502 may include one or more modules to facilitate interaction between the processing component 502 and other components. For example, the processing component 502 may include a multimedia module to facilitate interaction between the multimedia component 508 and the processing component 502.

The memory 504 is used to store various types of data to support the operation of the electronic device 500. Examples of such data include instructions for any application or method operating on the electronic device 500, contact data, phone book data, messages, pictures, multimedia, etc.

The power supply assembly 506 provides power to the various components of the electronic device 500. The power supply assembly 506 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 500.

The multimedia component 508 includes a screen that provides an output interface between the electronic device 500 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, it may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensors can detect not only the demarcation of a touch or slide action, but also the duration and pressure associated with the touch or slide action. In some embodiments, the multimedia component 508 includes a front-facing camera and/or a rear-facing camera. When the electronic device 500 is in an operating mode, such as a capture mode or a multimedia mode, the front-facing camera and/or the rear-facing camera can receive external multimedia data. Each front-facing camera and the rear-facing camera can have a fixed optical lens system or have a variable focal length and optical zoom capability.

The audio component 510 is used to output and/or input audio signals. For example, the audio component 510 includes a microphone (MIC) that receives external audio signals when the electronic device 500 is in an operating mode, such as a call mode, a recording mode, or a voice recognition mode. The received audio signals may be further stored in the memory 504 or transmitted via the communication component 516. In some embodiments, the audio component 510 also includes a speaker for outputting audio signals.

The input/output interface 512 provides an interface between the processing component 502 and peripheral interface modules, such as a keyboard, a click wheel, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

The sensor assembly 514 includes one or more sensors for providing various aspects of status assessment for the electronic device 500. The sensor assembly 514 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 514 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 514 may also include an accelerometer, a gyroscope, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 516 is used to facilitate wired or wireless communication between the electronic device 500 and other devices. The electronic device 500 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G, or 5G), or a combination thereof. In an exemplary embodiment, the communication component 516 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 516 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the electronic device 500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement a binary translation method provided in an embodiment of the present application.

In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 504 including instructions, which can be executed by the processor 520 of the electronic device 500 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

FIG6 is a block diagram of an electronic device 600 according to an exemplary embodiment. For example, the electronic device 600 can be provided as a server. Referring to FIG6 , the electronic device 600 includes a processing component 622, which further includes one or more processors, and a memory resource represented by a memory 632 for storing instructions that can be executed by the processing component 622, such as an application. The application stored in the memory 632 can include one or more modules, each of which corresponds to a set of instructions. In addition, the processing component 622 is configured to execute instructions to perform a binary translation method provided in an embodiment of the present application.

The electronic device 600 may further include a power supply component 626 configured to perform power management of the electronic device 600, a wired or wireless network interface 650 configured to connect the electronic device 600 to a network, and an input/output interface 658. The electronic device 600 may operate based on an operating system stored in the memory 632.

An embodiment of the present application also provides a computer program product, including a computer program and a binary translation method implemented when the computer program is executed by a processor.

Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims (13)

1. A binary translation method, the method comprising:

The method comprises the steps of obtaining a translation result of each basic block from a cache of a translator, and translating a source architecture instruction into a target architecture instruction by taking the basic blocks as granularity after the translator reads a binary file;

when an instruction in the translation result is executed, if the currently executed instruction is determined to be a target instruction with access alignment abnormality, remapping according to a first access address included in the target instruction to generate a second access address, and configuring a memory fragment corresponding to the first access address as inaccessible;

The second memory access address generation step comprises the steps of taking the memory access address of the idle memory area meeting the target capacity in the cache as the second memory access address after remapping the first memory access address, wherein the target capacity is the capacity of the memory area corresponding to the first memory access address;

The method further comprises the step of determining that the currently executed instruction is a target instruction with access alignment abnormality if the maximum bit width of the atomic instruction supported by the target architecture is smaller than the instruction bit width included by the instruction of the source architecture or if the access address pair Ji Gui of the atomic instruction of the target architecture is more strictly defined than the access address alignment of the atomic instruction of the source architecture.

2. The method of claim 1, wherein the determining that the currently executing instruction is a target instruction for which there is a memory alignment exception comprises:

in the process of executing the instruction in the translation result, synchronously detecting an execution stop signal;

and under the condition that the execution stop signal is detected, if the stop instruction triggering the execution stop signal is determined to be an instruction with access alignment abnormality, the currently executed instruction is the target instruction, and the translation result is stopped.

3. The method of claim 1, wherein the generating the second address comprises:

Acquiring an initial memory access address in the target instruction according to the address type of the first memory access address, wherein the target instruction is a written stop instruction comprising a preset non-aligned memory access address at a corresponding instruction position obtained by a current translated instruction after translation;

And remapping the memory area corresponding to the initial memory address to obtain the second memory address.

4. The method of claim 3, wherein the obtaining the initial address in the target instruction comprises:

Acquiring an access memory address in a preset register under the condition that the address type is a preset unaligned access memory address, wherein the access memory address is included in the current translated instruction;

and taking the memory address as an initial memory address in the target instruction.

5. The method of claim 3, wherein the obtaining the initial address in the target instruction comprises:

And under the condition that the address type is a non-aligned address, taking the first address as an initial address in the target instruction.

6. The method of claim 3, wherein remapping the memory segment corresponding to the initial address comprises:

Acquiring the memory capacity of a memory chip area corresponding to the initial memory access;

searching an idle memory fragment including the memory capacity in the cache, and generating a memory access address of the idle memory fragment;

And taking the access address of the free memory area as the remapped second access address.

7. The method of claim 6, wherein the generating the memory address of the free memory patch comprises:

acquiring a first starting address of a memory chip area corresponding to the initial memory access address, and acquiring a second starting address of the idle memory chip area;

and obtaining the access address of the free memory chip area according to the first starting address and the second starting address.

8. The method according to claim 1, wherein the method further comprises:

Acquiring the coding length of an access address in an instruction currently translated by the translator;

when the coding length is greater than or equal to the coding length corresponding to the host architecture, determining that the current translated instruction has access alignment abnormality;

and determining the translated target instruction according to the current translated instruction.

9. The method of claim 8, wherein said determining the translated target instruction from the currently translated instruction comprises:

Writing a stop instruction comprising a preset non-aligned memory address into a corresponding instruction position obtained after translation of the current translated instruction, and storing the memory address included in the current translated instruction into a preset register;

and taking the stop instruction as the target instruction.

10. The method according to claim 1, wherein the method further comprises:

Acquiring a current translated instruction of the translator;

When the address type of the access address in the current translated instruction is a non-aligned access address, determining that the current translated instruction has access alignment abnormality, and translating the current translated instruction to obtain the target instruction.

11. A binary translation apparatus, the apparatus comprising:

the first acquisition module is used for acquiring a translation result of each basic block from a cache of a translator, and the translator translates a source architecture instruction into a target architecture instruction by taking the basic blocks as granularity after reading the binary file;

the generation module is used for, when executing the instruction in the translation result, if the currently executed instruction is determined to be a target instruction with access alignment abnormality, remapping according to a first access address included in the target instruction, generating a second access address, and configuring a memory fragment corresponding to the first access address to be inaccessible;

The execution module is used for executing memory access operation aiming at the second memory access address so as to access the data of the second memory access address;

The generating module is configured to use an address of an idle memory area in the cache, which meets a target capacity, as a second address after remapping the first address, where the target capacity is a capacity of a memory area corresponding to the first address;

the apparatus further comprises:

and the determining module is used for determining that the currently executed instruction is a target instruction with abnormal access alignment if the maximum bit width of the atomic instruction supported by the target architecture is smaller than the instruction bit width included by the instruction of the source architecture or if the access address pair Ji Gui of the atomic instruction of the target architecture is more strictly defined than the access address alignment rule of the atomic instruction of the source architecture.

12. An electronic device comprising a processor, a memory and a program or instruction stored on the memory and executable on the processor, which when executed by the processor, implements the steps of the method of any of claims 1 to 10.

13. A readable storage medium, characterized in that instructions in the readable storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the method of any one of claims 1-10.