CN119451253A

CN119451253A - A method for reducing impurities in a substrate, a semiconductor structure and a method for preparing the same

Info

Publication number: CN119451253A
Application number: CN202310961406.5A
Authority: CN
Inventors: 谢伍童
Original assignee: Wuhan Chuxing Technology Co ltd
Current assignee: Wuhan Chuxing Technology Co ltd
Priority date: 2023-08-01
Filing date: 2023-08-01
Publication date: 2025-02-14

Abstract

The present application discloses a method for reducing impurities in a substrate, a semiconductor structure and a preparation method thereof, the method comprising: providing a substrate, providing an isolation structure for defining an active region on a first surface of the substrate, forming a first dielectric layer on a second surface of the substrate, wherein the first surface and the second surface are arranged relative to each other; etching a region corresponding to the active region in the first dielectric layer to form a plurality of spaced first grooves, wherein the first grooves expose the second surface of the substrate; forming an impurity gettering layer, wherein the impurity gettering layer at least covers the inner wall of the first groove. By forming an impurity gettering layer of a small region on the inner wall of each first groove, an impurity gettering region is formed between the impurity gettering layer and the substrate, impurities introduced by the production process can be effectively adsorbed, thereby improving the performance of the semiconductor structure containing the substrate.

Description

Method for reducing impurities in substrate, semiconductor structure and preparation method thereof

Technical Field

The present application relates to the field of semiconductor technology, and in particular, to a method for reducing impurities in a substrate, a semiconductor structure and a method for manufacturing the semiconductor structure.

Background

Image sensors are widely used semiconductor devices, and generally classified into Charge-Coupled Device (CCD) image sensors and complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensors (CMOS Image Sensor, CIS), wherein the CIS includes a pixel array formed of individual pixels on a silicon substrate wafer, each pixel including several devices such as a Photodiode (PD) and a pixel transistor.

In the CIS device manufacturing process, metal impurity contamination is introduced due to the production process, metal ions having charges remain in the photodiode region for a long time, and a Dark Current (Dark Current) is formed by the continuous accumulation of a large amount of charges, so that for a pixel, when the Dark Current is greater than a photocurrent generated by capturing photons, the pixel becomes a White Pixel (WP). White pixels are one of the key parameters affecting CIS device performance, and when the number of white pixels is large, the imaging quality of CIS is seriously degraded.

In the related art, a method of introducing damage to the backside of a silicon substrate wafer is generally used to capture metal impurities introduced in the production process, so as to reduce the number of white pixels, however, mechanical damage generated in the backside damage gettering method may affect the strength of the silicon substrate wafer, and in the subsequent production process flow, the silicon substrate wafer may cause warpage or even chipping, thereby reducing the production efficiency.

Disclosure of Invention

The application provides a method for reducing impurities in a substrate, a semiconductor structure and a preparation method thereof, which are used for adsorbing the impurities introduced into the substrate by a production process so as to improve the performance of the semiconductor structure containing the substrate.

In a first aspect, an embodiment of the present application provides a method for reducing impurities in a substrate, including:

Providing a substrate, wherein an isolation structure for defining an active region is arranged on a first surface of the substrate, and a first dielectric layer is formed on a second surface of the substrate, and the first surface and the second surface are oppositely arranged;

etching a region corresponding to the active region in the first dielectric layer to form a plurality of first grooves with intervals, wherein the second surfaces of the substrates are exposed by the first grooves;

and forming a gettering layer, wherein the gettering layer at least covers the inner wall of the first groove.

The method for reducing impurities in the substrate comprises the steps of firstly providing a substrate, arranging an isolation structure used for defining an active area on the first surface of the substrate, forming a first dielectric layer on the second surface of the substrate, wherein the first surface and the second surface are opposite to each other, etching a region corresponding to the active area in the first dielectric layer to form a plurality of first grooves with intervals, exposing the second surface of the substrate from the first grooves, and finally forming a gettering layer at least covering the inner wall of the first grooves. By forming the gettering layer at least on the inner walls of the first grooves exposing the second surface of the substrate, since the gettering layer formed in each first groove is small-area, compared to the manner in which the gettering layer of a large area is directly deposited on the second surface of the substrate, the probability of occurrence of the peeling phenomenon of the gettering layer formed in the above manner is small, and furthermore, by forming the gettering region between the gettering layer and the substrate, impurities introduced due to the production process can be effectively adsorbed, and by reducing the impurities in the substrate, the performance of the semiconductor structure including the substrate can be improved.

In an alternative embodiment, after forming the plurality of first grooves, the method further comprises etching the exposed second surface of the substrate to form a plurality of second grooves, and the gettering layer at least covers the inner walls of the second grooves.

In the method, after the first grooves are formed, the exposed second surface of the substrate is etched to form the second grooves, and the gettering layer at least covers the inner walls of the second grooves. And forming a plurality of second grooves by continuously etching the second surface of the substrate exposed by the first grooves, and forming a gettering layer in each second groove, so that the contact area between the gettering layer and the substrate is increased, and the gettering effect of the gettering layer on the substrate is further improved.

In an alternative embodiment, the opening size of the second recess is the same as the opening size of the first recess.

According to the method, the contact area between the gettering layer covering the inner wall of the second groove and the substrate is increased by setting the opening size of the second groove to be the same as that of the first groove, so that the gettering effect of the gettering layer on the substrate is improved.

In an alternative embodiment, the isolation structures are inverted trapezoid structures, a maximum value of a distance between two opposite side walls of two adjacent isolation structures is a first size, a minimum value of the distance is a second size, an opening size of the first groove is the first size, and an opening size of the second groove is the second size.

According to the method, the opening size of the first groove is set to be the first size, the opening size of the second groove is set to be the second size, and the first size is larger than the second size, so that the inner wall of the groove structure formed by the first groove and the second groove is of a step structure, the contact area between the gettering layer covering the inner walls of the first groove and the second groove and the substrate is increased, and the gettering effect of the gettering layer on the substrate is improved.

In an alternative embodiment, the depth of the second groove is greater than or equal to the depth of the first groove.

According to the method, the depth of the second groove is set to be larger than or equal to that of the first groove, so that the contact area between the gettering layer covered by the side face of the inner wall of the second groove and the substrate is increased, and the gettering effect of the gettering layer on the substrate is improved.

In an alternative embodiment, the first dielectric layer is synchronously formed on the first surface of the substrate when the first dielectric layer is formed on the second surface of the substrate, and before etching the area corresponding to the active area in the first dielectric layer, an insulating protection layer is formed, and the insulating protection layer covers the first dielectric layer on the first surface of the substrate.

According to the method, first, the first dielectric layer is formed on the first surface and the second surface of the substrate at the same time, the insulating protective layer is continuously formed on the first dielectric layer formed on the first surface of the substrate, and then the area, corresponding to the active area, in the first dielectric layer is etched. The first dielectric layer and the insulating protective layer which are stacked are formed on the first surface of the substrate to form the protective layer on the first surface of the substrate, so that the first surface of the substrate is prevented from being damaged when the substrate is turned over, and the purpose of protecting the substrate is achieved.

In an alternative embodiment, the method further comprises nitriding the second surface of the substrate with a nitrogen-containing plasma prior to forming the first dielectric layer on the second surface of the substrate.

In the method, firstly, nitrogen-containing plasma is utilized to carry out nitriding pretreatment on the second surface of the substrate, and then, a first dielectric layer is formed on the second surface of the substrate. And removing particles on the second surface of the substrate through the nitrogen-containing plasma, and simultaneously converting silicon hydroxyl bonds on the second surface of the substrate into silicon nitrogen bonds so as to enhance the adhesion force between the subsequently formed first dielectric layer and the gettering layer and the substrate and reduce the occurrence probability of the shedding phenomenon.

In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, providing a substrate, forming an epitaxial layer on a surface of the substrate, forming an isolation structure for defining an active region in the epitaxial layer, and performing gettering treatment on the substrate by using the substrate and the epitaxial layer as a substrate and by using the method for reducing impurities in the substrate according to any one of the embodiments of the first aspect.

In an alternative embodiment, the preparation method further comprises thinning the second surface of the substrate after gettering the substrate, and removing the gettering layer and the first dielectric layer.

In a third aspect, an embodiment of the present application provides a semiconductor structure, where the semiconductor structure is prepared by using the preparation method according to any one of the embodiments in the second aspect.

The foregoing technical effects that may be achieved by the method for manufacturing a semiconductor structure disclosed in the second aspect and the semiconductor structure disclosed in the third aspect are referred to above for the first aspect or the description of the technical effects that may be achieved by the various possible solutions in the first aspect, and are not repeated here.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it will be apparent that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a substrate formed by a back side damage gettering method according to the related art;

FIG. 2 is a flow chart of a method for reducing impurities in a substrate according to an embodiment of the present application;

FIG. 3 is a schematic view of a substrate according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a chemical vapor deposition apparatus for a substrate according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a structure for converting silicon hydroxyl bonds on a second surface of a substrate into silicon nitrogen bonds according to an embodiment of the present application;

FIG. 6 is a schematic view of another substrate according to an embodiment of the present application;

FIG. 7 is a schematic view of a substrate with a plurality of first grooves and second grooves formed thereon according to an embodiment of the present application;

FIG. 8 is a schematic view of another substrate with a plurality of first grooves and second grooves formed thereon according to an embodiment of the present application;

FIG. 9 is a schematic view of another structure of a substrate with a plurality of first grooves and second grooves formed thereon according to an embodiment of the present application;

FIG. 10a is a schematic view of another substrate according to an embodiment of the present application;

FIG. 10b is a schematic view of another substrate according to an embodiment of the present application;

FIG. 10c is a schematic view of another substrate according to an embodiment of the present application;

FIG. 11a is a schematic diagram of a structure of a substrate without a gettering layer according to an embodiment of the present application;

FIG. 11b is a schematic diagram of a substrate with a gettering layer formed according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.

In the manufacturing process of the image sensor, in order to reduce metal impurities introduced in the production process, so as to reduce the number of white pixels of the produced image sensor and improve the imaging quality of the image sensor, a silicon wafer impurity removal method is generally adopted to capture the metal impurities introduced in the production process. In the semiconductor manufacturing process, the conventional impurity removing method comprises external impurity removing and internal impurity removing, wherein the internal impurity removing is to utilize high-temperature rapid heat treatment to promote oxygen precipitation nucleation growth in a substrate for capturing metal impurities, such as an annealing process, and the external impurity removing is to introduce stress or damage to the back surface of the substrate, induce secondary defects after heat treatment, and attract the metal impurities, such as back surface damage impurity removing (Backside Damage) or polycrystalline back surface field impurity removing (Poly-back metal) and the like.

Fig. 1 shows a schematic structure of a substrate formed by a back side damage gettering method, and as shown in fig. 1, a substrate 10 includes a substrate 11, an epitaxial layer 12, a crystal face 13, and a crystal back 14, an oxygen precipitate 15 and a metal impurity 16 are formed in the substrate 10, and a pixel transistor 17 is disposed on the crystal face 13 of the substrate 10, wherein the pixel transistor may be a MOS transistor, a triode, or the like. Damage is introduced at the back 14 of the substrate 10 to form a gettering region 18 for trapping metal impurities 16.

However, for internal gettering, the epitaxial layer of the substrate is melted due to the higher temperature of the epitaxial layer during the fabrication process, so that the gettering capability of the mode is weakened, and the time required for the annealing process is longer, which is easy to bring about risks. For external gettering, damage is required to be introduced into the back of the substrate in a mode of damaging gettering, and mechanical damage can seriously affect the strength of the substrate, so that a fragmentation phenomenon is easily generated in a subsequent high-temperature process, and the production efficiency is reduced.

Based on the above, embodiments of the present application provide a method for reducing impurities in a substrate, a semiconductor structure and a method for manufacturing the same, which adsorb impurities introduced into a substrate by a production process without damaging the substrate, thereby improving performance of the semiconductor structure including the substrate.

The method for reducing impurities in a substrate according to the present application is described below by way of specific examples, and as shown in fig. 2, the method includes the steps of:

Step S201, providing a substrate, wherein an isolation structure for defining an active region is arranged on a first surface of the substrate, and a first dielectric layer is formed on a second surface of the substrate, wherein the first surface and the second surface are oppositely arranged;

It should be noted that, in the embodiment of the present application, the first dielectric layer may be a silicon dioxide (SiO 2) layer, a silicon oxynitride (SiON) layer, an aluminum oxide (Al 2O 3) layer, or a dielectric layer formed of another oxide, which is not limited in this way.

In a specific implementation, for a substrate composed of a substrate and an epitaxial layer, a first surface of the substrate may be treated with a shallow trench isolation (Shallow Trench Isolation, STI) process to form a plurality of isolation structures on the first surface of the substrate, the isolation structures being used to define an active region.

Preferably, the first surface 303 in the embodiment of the present application may be a crystal plane of the substrate 30, and the second surface 304 may be a crystal back of the substrate 30.

For example, fig. 3 shows a schematic structural diagram of a substrate provided in an embodiment of the present application, as shown in fig. 3, the substrate 30 includes an epitaxial layer 301, a substrate 302, a first surface 303, and a second surface 304, and shallow trench isolation is performed on the first surface 303 of the substrate 30 to form a plurality of isolation structures 305 in the epitaxial layer 301, where the isolation structures 305 define a plurality of active regions 306 in the epitaxial layer 301.

It should be noted that, in the embodiment of the present application, the substrate 30 formed with the plurality of isolation structures 305 has a tensile stress characteristic, and each isolation structure 305 has an inverted trapezoid structure.

In an alternative embodiment, the second surface of the substrate is nitrided by a nitrogen containing plasma and a first dielectric layer is formed on the second surface of the substrate.

It should be noted that in the embodiment of the present application, the step of nitriding pretreatment may be performed after any step before the step of forming the first dielectric layer, for example, the substrate provided with the isolation structure may be provided first, then the second surface of the substrate may be subjected to nitriding pretreatment, and finally the first dielectric layer may be formed on the second surface of the substrate, or the second surface of the substrate may be subjected to nitriding pretreatment first, then the substrate provided with the isolation structure may be provided, and finally the first dielectric layer may be formed on the second surface of the substrate.

In a specific implementation, ammonia gas can be introduced into the reaction chamber in which the substrate is placed, so that the ammonia gas and the silicon hydroxyl bonds on the second surface of the substrate are subjected to nitriding reaction, and the silicon hydroxyl bonds are converted into silicon nitrogen bonds, so that nitriding pretreatment of the second surface of the substrate is realized.

For example, the substrate may be subjected to NH3 PLASMA TREATMENT (ammonia plasma treatment). As shown in fig. 4, a schematic structural diagram of a chemical vapor deposition apparatus is shown, where the chemical vapor deposition apparatus 40 includes a first spraying device (Sho-ped) 401, a Plasma (Plasma) 402, a gasket (CARRIER RING) 403, and a second spraying device (SHD) 404, where the first spraying device 401 is used as a reference electrode for grounding and also as a path for a reaction gas to enter a reaction chamber, the gasket 403 is used for placing a substrate 30, and the second spraying device 404 is used as an electrode for applying an external voltage and also as another path for the reaction gas to enter the reaction chamber.

In one embodiment, the substrate 30 is placed on the washer 403 such that the first surface of the placed substrate is adjacent to the second spraying device 404, the second surface of the placed substrate 30 is adjacent to the plasma 402, and the distance between the first surface of the substrate 30 and the second spraying device 404 is set to 2mm-5mm, so as to ensure that the first surface of the substrate 30 is not damaged during operation. Then, ammonia (NH 3) is input into the reaction chamber through the first spraying device 401, and after the ammonia passes through the plasma 402, nitrogen-containing plasma is excited, and the nitrogen-containing plasma and the silicon hydroxyl bond on the second surface of the substrate 30 undergo a nitridation reaction, so that the silicon hydroxyl bond is converted into a silicon nitrogen bond, thereby enhancing the adhesion of the second surface of the substrate 30 and reducing the occurrence probability of the flaking (Peeling) phenomenon. Wherein the chemical reaction occurring in the process is:

Si-OH+N→Si-N-N-Si+H2O;

Fig. 5 is a schematic diagram showing the conversion of the silicon hydroxyl bond on the second surface of the substrate into a silicon nitrogen bond.

Firstly, introducing ammonia into a reaction chamber for placing a substrate, nitriding the second surface of the substrate by utilizing generated nitrogen-containing plasma, and then forming a first dielectric layer on the second surface of the substrate. Particles (particles) on the second surface of the substrate are removed through the nitrogen-containing plasma, and simultaneously silicon hydroxyl bonds on the second surface of the substrate are converted into silicon nitrogen bonds, so that the adhesion force between the subsequently formed first dielectric layer and the gettering layer and the substrate is enhanced, and the probability of falling off is reduced.

In a specific implementation, for a substrate composed of a substrate and an epitaxial layer, a thin film deposition process may be used to treat the second surface of the substrate to form a first dielectric layer on the second surface of the substrate.

For example, fig. 6 shows a schematic structural diagram of a substrate provided in an embodiment of the present application, as shown in fig. 6, the substrate 30 includes an epitaxial layer 301, a substrate 302, a first surface 303, and a second surface 304, and a plurality of isolation structures 305 are formed in the epitaxial layer 301 of the substrate 30, and the isolation structures 305 define a plurality of active regions 306 in the epitaxial layer 301. Thin film deposition is performed on the second surface of the base 30 to form a first dielectric layer 601 on the side of the substrate 302 remote from the epitaxial layer 301, i.e., the second surface 304.

Preferably, the thickness of the first dielectric layer in the embodiment of the present application may be 5 nm to 10 nm.

In an alternative embodiment, the first dielectric layer is formed on the first surface of the substrate simultaneously with the formation of the first dielectric layer on the second surface of the substrate, and then an insulating protective layer is formed, wherein the insulating protective layer covers the first dielectric layer on the first surface of the substrate, and the region corresponding to the active region in the first dielectric layer is etched.

In a specific implementation, since the second surface of the substrate needs to be subjected to operations such as etching, the substrate needs to be turned over, in order to avoid damage to the device layer disposed on the first surface of the substrate in the turning process, before the etching operation is performed, a first dielectric layer may be formed on the first surface and the second surface of the substrate at the same time, and then an insulating protection layer is laminated on the first dielectric layer on the first surface of the substrate, so as to prevent damage to the first surface of the substrate in the turning process of the substrate.

It should be noted that the insulating protection layer in the embodiment of the present application may be a silicon nitride (SiN) layer, a silicon oxynitride (SiON) layer, a silicon carbon nitride (SiCN) layer, or the like, which is not limited in any way.

In addition, the insulating protection layer is continuously formed on the first dielectric layer formed on the first surface of the substrate, so that the first surface of the substrate is prevented from being damaged when the substrate is turned over, and the purpose of protecting the substrate is achieved.

In an alternative embodiment, a first dielectric layer is formed on the second surface of the substrate, and a second dielectric layer is formed on the first surface of the substrate, then an insulating protective layer is formed, the insulating protective layer covers the first dielectric layer on the first surface of the substrate, and a region of the first dielectric layer corresponding to the active region is etched.

In the embodiment of the application, the dielectric layers are formed on the second surface of the first surface of the substrate, specifically, the second dielectric layer may be formed on the first surface of the substrate first, then the first dielectric layer may be formed on the second surface of the substrate first, or the first dielectric layer may be formed on the second surface of the substrate first, then the second dielectric layer may be formed on the first surface of the substrate.

According to the method, firstly, the first dielectric layer is formed on the second surface of the substrate, the second dielectric layer is formed on the first surface of the substrate, the insulating protection layer is continuously formed on the second dielectric layer formed on the first surface of the substrate, and then the area corresponding to the active area in the first dielectric layer is etched. The second dielectric layer and the insulating protective layer which are stacked are formed on the first surface of the substrate to form the protective layer on the first surface of the substrate, so that the first surface of the substrate is prevented from being damaged when the substrate is turned over, and the purpose of protecting the substrate is achieved.

Step S202, etching a region corresponding to the active region in the first dielectric layer to form a plurality of first grooves at intervals, wherein the second surfaces of the substrates are exposed by the first grooves;

In a specific implementation, an etching process is utilized to perform etching operation on areas corresponding to the plurality of active areas on the first surface of the substrate in the first dielectric layer, wherein the etching depth is the depth of the first dielectric layer, so that a plurality of first grooves obtained after etching are exposed out of the second surface of the substrate. For example, if the depth of the first dielectric layer is 6nm, the depth of the first recess formed is also 6nm, if the depth of the first dielectric layer is 8nm, the depth of the first recess formed is also 8nm, and so on.

For example, fig. 7 shows a schematic structural diagram of a substrate formed with a plurality of first grooves, as shown in fig. 7, a plurality of first grooves 701 are formed in the first dielectric layer 601, a side of each first groove 701 facing away from the opening exposes the second surface 304 of the substrate 30, and the first grooves 701 are in one-to-one correspondence with the active regions 306.

Alternatively, as shown in fig. 7, the isolation structures 305 are in inverted trapezoid structures, the maximum distance between two opposite sidewalls of two adjacent isolation structures is a first dimension L1, the opening dimension of the first recess 701 is equal to the first dimension L1, and the depth of the first recess 701 is equal to the thickness of the first dielectric layer 601. The opening size of the first groove 701 is set to be the maximum value of the distance between two opposite side walls of two adjacent isolation structures, so that the contact area between the gettering layer formed on the inner wall of the first groove and the substrate is increased, and the gettering effect of the gettering layer is improved.

In an alternative embodiment, after forming the plurality of first grooves, etching the exposed second surface of the substrate to form a plurality of second grooves, and the gettering layer also covers at least the inner walls of the second grooves.

In a specific implementation, after the plurality of first grooves are formed, etching is continued on the second surface of the substrate exposed by the first grooves, a plurality of second grooves are formed, and a gettering layer is formed, so that the gettering layer at least covers the inner walls of the first grooves and the second grooves.

In the embodiment of the application, the first medium layer can be etched to form the first groove in the process of etching the first groove and the second groove, and the exposed second surface of the substrate can be etched after the etching of the first medium layer is finished, or the first medium layer and the exposed second surface of the substrate can be etched at the same time, namely, after the etching of the first medium layer is finished to form any one first groove, the exposed second surface of the substrate can be continuously etched to form the second groove, and then the first medium layer can be etched again to form the next first groove, and the cycle is repeated until the etching is finished.

In specific implementation, the opening size of the second groove obtained by etching is the same as the opening size of the first groove, so that the contact area between the gettering layer covering the inner wall of the second groove and the substrate is increased, and the gettering effect of the gettering layer on the substrate is improved.

For example, fig. 8 shows a schematic structural diagram of a substrate formed with a plurality of first grooves and second grooves, as shown in fig. 8, the isolation structure 305 is in an inverted trapezoid structure, a maximum value of a distance between two opposite sidewalls of two adjacent isolation structures is a first dimension L1, a plurality of first grooves 701 are formed in the first dielectric layer 601, an opening dimension of the first grooves 701 is equal to the first dimension L1, a depth H1 of the first grooves 701 is equal to a thickness of the first dielectric layer 601, a second groove 801 is etched on a second surface exposed by the first grooves 701, and an opening dimension of the second grooves 801 is equal to an opening dimension of the first grooves 701, which are both the first dimension L1. So that the inner wall of the groove structure composed of the first groove 701 and the second groove 801 is in a smooth structure.

Optionally, the depth of the second groove formed in the embodiment of the present application is greater than or equal to the depth of the first groove.

As shown in fig. 8, the depth of the first groove 701 is H1, the depth of the second groove 801 is H2, and by setting H2 be equal to or greater than H1, the contact area between the gettering layer covered by the side surface of the inner wall of the second groove 801 and the substrate is increased, so as to further improve the gettering effect of the gettering layer to the substrate.

In the method, after the first grooves are formed, the exposed second surface of the substrate is etched to form the second grooves, and the gettering layer at least covers the inner walls of the second grooves. Forming a plurality of second grooves by continuing to etch the second surface of the substrate exposed by the first grooves, and forming a gettering layer inside each of the second grooves, compared to forming only the first grooves, and the structure of the gettering layer is formed on the inner wall of the first groove, the contact area between the gettering layer formed on the inner wall of the second groove and the substrate is larger, and the gettering effect of the gettering layer on the substrate can be further improved.

In an alternative embodiment, the isolation structures are inverted trapezoid structures, the maximum value of the distance between two opposite side walls of two adjacent isolation structures is a first size, the minimum value of the distance is a second size, the opening size of the first groove is the first size, and the opening size of the second groove is the second size.

In a specific implementation, the opening size of the second groove obtained by etching is smaller than the opening size of the first groove, namely, the opening size of the second groove is equal to the minimum distance between two opposite side walls of two adjacent isolation structures, and the opening size of the first groove is equal to the maximum distance between two opposite side walls of two adjacent isolation structures, so that the contact area between the gettering layer covering the inner walls of the first groove and the second groove and the substrate is increased, and the gettering effect of the gettering layer to the substrate is improved.

For example, fig. 9 shows a schematic structural diagram of a substrate formed with a plurality of first grooves and second grooves, as shown in fig. 9, the isolation structure 305 is in an inverted trapezoid structure, a maximum distance between two opposite sidewalls of two adjacent isolation structures is a first dimension L1, a minimum distance is a second dimension L2, a plurality of first grooves 701 are formed in the first dielectric layer 601, an opening dimension of the first grooves 701 is equal to the first dimension L1, a depth of the first grooves 701 is H1, H1 is equal to a thickness of the first dielectric layer 601, the second grooves 901 are etched on the exposed second surface of the first grooves 701, and an opening dimension of the second grooves 901 is equal to the second dimension L2. So that the inner wall of the groove structure composed of the first groove 701 and the second groove 901 is in a stepped structure.

As shown in fig. 9, the depth of the first groove 701 is H1, the depth of the second groove 901 is H3, and by setting H3 be equal to or greater than H1, the contact area between the gettering layer covered by the side surface of the inner wall of the second groove 901 and the substrate is increased, so as to further improve the gettering effect of the gettering layer to the substrate.

According to the method, the opening size of the first groove is set to be the first size, the opening size of the second groove is set to be the second size, and the first size is larger than the second size, so that the inner wall of the groove structure formed by the first groove and the second groove is of a step structure, the contact area between the gettering layer covering the inner walls of the first groove and the second groove and the substrate is increased, and the gettering effect of the gettering layer on the substrate is improved. In an alternative embodiment, a plurality of grooves with different opening sizes can be formed on the second surface of the substrate, and the grooves are etched to form a stepped structure with the opening sizes gradually reduced, so that the contact area is further increased, and the gettering effect is provided.

In step S203, a gettering layer is formed, and the gettering layer covers at least an inner wall of the first groove.

It should be noted that, in the embodiment of the present application, the gettering layer may be a silicon nitride layer or a polysilicon layer, which is not limited in any way.

Preferably, if the gettering layer in the embodiment of the present application is a silicon nitride layer, the silicon nitride layer exhibits a compressive stress characteristic. The substrate with the isolation structure is in tensile stress characteristic, and the silicon nitride layer is in compressive stress characteristic, so that the bending direction of the first surface of the substrate is consistent with the bending direction of the second surface of the substrate, and the occurrence of flaking phenomenon is avoided.

In the implementation, while the inner walls of the first groove and the second groove are deposited to form the gettering layer, the gettering layer is also deposited on one side of the etched first dielectric layer away from the substrate, and the complete gettering layer is formed by the gettering layer formed by depositing the inner walls of the first groove and the second groove and the gettering layer formed by depositing one side of the etched first dielectric layer. In addition, the active areas are arranged in an array, so that a gettering region is formed between the gettering layer and the substrate and corresponds to the active areas arranged in the array, metal impurities diffused from the active areas are adsorbed, the stay time of the metal impurities in the active areas is reduced, and the performance of a semiconductor structure comprising the substrate is improved.

For example, fig. 10a shows a schematic structural view of a substrate, as shown in fig. 10a, first grooves 701 are formed in the substrate 30, and a gettering layer 1001 is deposited on the inner wall of each first groove 701 and the surface of the first dielectric layer 601.

For example, fig. 10b shows a schematic structural view of a substrate, as shown in fig. 10b, a first groove 701 and a second groove 801 are formed in the substrate 30, and a gettering layer 1002 is deposited on the inner wall of the first groove 701, the inner wall of the second groove 801, and the surface of the first dielectric layer 601.

For example, fig. 10c shows a schematic structural view of a substrate, as shown in fig. 10c, a first groove 701 and a second groove 901 are formed in the substrate 30, and a gettering layer 1003 is deposited on the inner wall of the first groove 701, the inner wall of the second groove 901, and the surface of the first dielectric layer 601.

In the embodiment, as shown in fig. 11a, a schematic structural diagram of a substrate without forming a gettering layer is shown, an isolation structure 305 is disposed in the substrate 30, the isolation structure 305 is used to define an active region 306, a pixel for sensitization is disposed in the active region 306, as shown in fig. 11a, a large amount of metal impurities 110 are introduced into the substrate 30, and since the metal impurities 110 are charged, most of the metal impurities 110 are accumulated in the active region 306, thereby degrading the performance of the semiconductor structure including the substrate.

As shown in fig. 11b, a schematic structural diagram of a substrate with a gettering layer is shown, and as shown in fig. 11b, a gettering layer is formed on the back surface of the substrate 30, a gettering region 111 is formed between the gettering layer and the substrate, and the density of interface traps in the gettering region 111 is higher, which is 10 ¹¹～10¹²cm^-2, so that charges are very easy to be attracted, so that most of the metal impurities 110 accumulated in the active region 306 can be adsorbed out to improve the performance of the semiconductor structure including the substrate.

Based on the same conception, the embodiment of the application also provides a method for preparing a semiconductor structure, and because the semiconductor structure is obtained by gettering treatment by the method for reducing impurities in the substrate in the embodiment of the application, and the principle of solving the problem of the semiconductor structure is similar to that of the method, the implementation of the substrate semiconductor structure can refer to the implementation of the method, and the repetition is omitted.

The preparation method of the semiconductor structure comprises the steps of providing a substrate, forming an epitaxial layer on the surface of the substrate, forming an isolation structure used for defining an active region in the epitaxial layer, and carrying out gettering treatment on the substrate by taking the substrate and the epitaxial layer as the substrates through the method for reducing impurities in the substrates according to any one of the embodiments.

In an alternative embodiment, the preparation method further comprises the step of thinning the second surface of the substrate after gettering treatment is carried out on the substrate, and removing the gettering layer and the first dielectric layer.

In a specific implementation, after gettering treatment is performed on the substrate, thinning is performed on the second surface of the substrate, and the gettering layer and the first dielectric layer are removed, so that influence on a product formed by the semiconductor structure obtained by the preparation method is avoided.

Based on the same conception, the embodiment of the present application further provides a semiconductor structure, and because the semiconductor structure is a semiconductor structure obtained by the method for manufacturing a semiconductor structure in the embodiment of the present application, and the principle of solving the problem of the semiconductor structure is similar to that of the method, the implementation of the base semiconductor structure can refer to the implementation of the method, and the repetition is omitted.

As shown in fig. 12, a schematic structure of a semiconductor structure 120 includes:

The pixel array 121 and the substrate 30 subjected to gettering treatment by a method of reducing impurities in the substrate provided in the embodiment of the present application, the pixel array 1201 is disposed on an active region of the substrate 30.

The pixel array 121 is composed of pixels 1211 distributed in an array, and the pixels 1211 are used for sensitization and light current.

Preferably, the semiconductor structure in the embodiment of the present application may be an image sensor, for example, a CMOS image sensor.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A method for reducing impurities in a substrate, comprising:

Providing a substrate, wherein an isolation structure for defining an active area is disposed on a first surface of the substrate, and a first dielectric layer is formed on a second surface of the substrate, wherein the first surface and the second surface are disposed opposite to each other;

Etching a region of the first dielectric layer corresponding to the active region to form a plurality of spaced first grooves, wherein the first grooves expose the second surface of the substrate;

A gettering layer is formed, wherein the gettering layer at least covers an inner wall of the first groove.

2. The method according to claim 1, characterized in that after forming the plurality of first grooves, the method further comprises: etching the exposed second surface of the substrate to form a plurality of second grooves; and the gettering layer at least covers the inner walls of the second grooves.

3 . The method according to claim 2 , wherein an opening size of the second groove is the same as an opening size of the first groove.

4. The method as claimed in claim 2 is characterized in that the isolation structure is an inverted trapezoidal structure, the maximum distance between the two opposite side walls of two adjacent isolation structures is a first size, the minimum distance is a second size, the opening size of the first groove is the first size, and the opening size of the second groove is the second size.

5. The method according to any one of claims 2 to 4, characterized in that a depth of the second groove formed is greater than or equal to a depth of the first groove.

6. The method as claimed in claim 1 is characterized in that when the first dielectric layer is formed on the second surface of the substrate, the first dielectric layer is simultaneously formed on the first surface of the substrate; before etching the area in the first dielectric layer corresponding to the active area, it also includes: forming an insulating protective layer, wherein the insulating protective layer covers the first dielectric layer located on the first surface of the substrate.

7. The method according to any one of claims 1 to 4, characterized in that before forming the first dielectric layer on the second surface of the substrate, it further comprises: performing a nitridation pretreatment on the second surface of the substrate using nitrogen-containing plasma.

8. A method for preparing a semiconductor structure, characterized in that a substrate is provided, an epitaxial layer is formed on the surface of the substrate, an isolation structure for defining an active area is formed in the epitaxial layer, the substrate and the epitaxial layer are used as a base, and the base is subjected to a doping treatment by the method for reducing impurities in the base as described in any one of claims 1 to 7.

9 . The preparation method according to claim 8 , further comprising: after performing gettering treatment on the substrate, thinning the second surface of the substrate to remove the gettering layer and the first dielectric layer.

10. A semiconductor structure, characterized in that the semiconductor structure is prepared by the preparation method according to claim 8 or 9.