CN119403132B - Phase change memory and manufacturing method thereof - Google Patents
Phase change memory and manufacturing method thereofInfo
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- CN119403132B CN119403132B CN202411522584.9A CN202411522584A CN119403132B CN 119403132 B CN119403132 B CN 119403132B CN 202411522584 A CN202411522584 A CN 202411522584A CN 119403132 B CN119403132 B CN 119403132B
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Abstract
Embodiments of the present disclosure provide a phase change memory and a method of manufacturing the same. The method comprises the steps of providing a semiconductor structure, forming a first storage unit, an isolation layer arranged between adjacent first storage units, a first conductive wire arranged on one side of the first storage unit, wherein the surface of the first conductive wire protrudes out of the surface of the isolation layer, a first groove is formed by the adjacent first conductive wire and the isolation layer together, a first dielectric layer which covers the side wall and the bottom of the first groove and covers the first conductive wire is formed to form a second groove in the first groove, a second dielectric layer which covers the side wall and the bottom of the second groove and covers the first dielectric layer is formed, and flattening treatment is conducted to expose the first conductive wire, wherein the removal rate of the second dielectric layer is smaller than that of the first dielectric layer in the flattening treatment.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, including but not limited to a phase change memory and a method of manufacturing the same.
Background
By improving the manufacturing process of the semiconductor, the planar memory cell can be reduced to a smaller size. However, as the critical dimensions of the planar memory cells approach the lower limit, the storage density of the planar memory architecture approaches the upper limit. The three-dimensional storage structure may address density limitations in planar storage architectures.
Phase Change Memory (PCM) has become one of the most developed potential Memory technologies at present. Phase change memories use the difference in conductivity exhibited by phase change layers when they are converted to each other between crystalline and amorphous states to store data. The phase change memory may include a Bottom memory cell array (Bottom Stack) and a Top memory cell array (Top Stack) stacked to form a three-dimensional memory architecture. The bottom memory cell and the top memory cell may be connected by a shared conductive Line (e.g., shared Word Line). Thus, the shared conductive line process becomes a key manufacturing process in the phase change memory.
Currently, the fabrication process of phase change memories is still to be further improved.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a phase change memory and a method for manufacturing the same.
In order to achieve the above purpose, the technical scheme of the present disclosure is realized as follows:
In a first aspect, an embodiment of the disclosure provides a method for manufacturing a phase change memory, including providing a semiconductor structure, including a first memory cell, an isolation layer disposed between adjacent first memory cells, a first conductive line disposed on one side of the first memory cell, the first conductive line protruding from a surface of the isolation layer, the adjacent first conductive line and the isolation layer together forming a first recess, forming a first dielectric layer covering sidewalls and bottoms of the first recess and covering the first conductive line to form a second recess in the first recess, forming a second dielectric layer covering sidewalls and bottoms of the second recess and covering the first dielectric layer, and performing a planarization process to expose the first conductive line, wherein a removal rate of the second dielectric layer is smaller than a removal rate of the first dielectric layer in the planarization process.
In some embodiments, the second dielectric layer has a density that is greater than the density of the first dielectric layer.
In some embodiments, the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.
In some embodiments, the thickness of the second dielectric layer ranges from 150 to 200 angstroms, and the thickness of the first dielectric layer ranges from 50 to 100 angstroms.
In some embodiments, the process of forming the first dielectric layer includes a first atomic layer deposition process, and the process of forming the second dielectric layer includes a second atomic layer deposition process, wherein the radio frequency power in the second atomic layer deposition process is greater than the radio frequency power in the first atomic layer deposition process.
In some embodiments, the radio frequency power in the first atomic layer deposition process is 300-500 w, and the radio frequency power in the second atomic layer deposition process is 800-1000 w.
In some embodiments, the ratio between the removal rates of the second dielectric layer and the first conductive line ranges from 22 to 24.
In a second aspect, an embodiment of the present disclosure provides a phase change memory, where the phase change memory is manufactured by using the manufacturing method in the above technical scheme, and the phase change memory includes first memory cells arranged at intervals along a first direction. The memory device comprises a first memory unit, a first conductive wire, a first dielectric layer, a second dielectric layer and a second dielectric layer, wherein the first conductive wire is arranged on one side of the first memory unit and extends along a second direction, the two directions are intersected with the first direction, the first dielectric layer is arranged between adjacent first conductive wires and covers two side walls of the first conductive wire, the two side walls are oppositely arranged along the first direction, and the second dielectric layer is arranged between the first dielectric layers of the side walls of the adjacent first conductive wires.
In some embodiments, the second dielectric layer has a density that is greater than the density of the first dielectric layer.
Embodiments of the present disclosure provide a phase change memory and a method of manufacturing the same. In the embodiment of the disclosure, a first dielectric layer covering the side wall and the top surface of a first conductive wire is formed to protect the side wall and the top surface of the first conductive wire in the subsequent process of forming a second dielectric layer, the second dielectric layer is formed to fill gaps between adjacent first conductive wires, and the removal rate of the second dielectric layer is higher than that of the first dielectric layer in the process of flattening the second dielectric layer and the first dielectric layer, so that the height difference between the top surface of the first conductive wire and the surface of the second dielectric layer is reduced, the top surface of the first conductive wire and the surface of the second dielectric layer are basically flush, and further the yield of the phase change memory is improved and the electrical parameters of the phase change memory are improved.
Drawings
FIG. 1A is a cross-sectional view of a phase change memory provided in some embodiments during a manufacturing process;
FIG. 1B is a cross-sectional view of a second phase change memory provided in some embodiments during a manufacturing process;
FIG. 2 is a flow chart of a method for fabricating a phase change memory according to an embodiment of the disclosure;
FIG. 3A is a cross-sectional view of a phase change memory provided in an embodiment of the present disclosure during a manufacturing process;
FIG. 3B is a second cross-sectional view of a phase change memory provided in an embodiment of the present disclosure during a fabrication process;
FIG. 3C is a cross-sectional view III of a phase change memory provided in an embodiment of the present disclosure during a manufacturing process;
FIG. 3D is a cross-sectional view of a phase change memory provided in an embodiment of the present disclosure during a fabrication process;
fig. 4 is a schematic diagram of the results of the parameters in comparative examples 1 and 2 and examples 1 to 4;
fig. 5 is a block diagram of a memory system provided by an embodiment of the present disclosure.
Detailed Description
The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the embodiments of the present disclosure and the accompanying drawings, it being apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known functions and constructions are not described in detail to avoid obscuring the present disclosure, i.e., not all features of an actual embodiment are described herein.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.
Spatial relationship terms such as "under", "above", "over" and the like may be used herein for convenience of description to describe one element or feature as illustrated in the figures in relation to another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical aspects of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.
Before describing the embodiments of the present disclosure, various directions that may be involved in the embodiments of the present disclosure are defined. The direction in which the first memory cells (or the second memory cells) are arranged at intervals in the phase change memory is defined as a first direction (i.e., D1 direction) and a second direction (i.e., D2 direction) which intersect, and the stacking direction of the first memory cells and the second memory cells in the phase change memory is defined as a third direction (i.e., D3 direction). Here, any two of the first direction, the second direction, and the third direction intersect. In some embodiments, any two of the first direction, the second direction, and the third direction are perpendicular to each other. In the following, an example will be described in which any two of the first direction, the second direction, and the third direction are perpendicular to each other.
Fig. 1A and 1B are cross-sectional views of a phase change memory provided in some embodiments during a manufacturing process. As shown in FIG. 1A, the phase change memory may include bottom memory cells 104 (as shown by dotted circle boxes in FIG. 1A) arranged at intervals along the direction D1 and the direction D2, an isolation layer 106 between adjacent bottom memory cells 104, and a first conductive line 108 disposed on one side of the bottom memory cell 104, wherein the surface of the first conductive line 108 protrudes from the surface of the isolation layer 106. The surface of the first conductive line 108 away from the bottom memory cell 104 is referred to as a top surface, and two surfaces of the first conductive line opposite to each other in the D1 direction are referred to as sidewalls. The phase change memory may further include a first oxide layer 112 covering sidewalls and top surfaces of the first conductive lines 108 and covering a surface of the isolation layer 106, and a second oxide layer 118 covering the first oxide layer 112.
As shown in fig. 1B, the second oxide layer 118 and the first oxide layer 112 are planarized to expose the top surface of the first conductive line 108. During the planarization process, the second oxide layer 118 and the first oxide layer 112 need to be removed to stay on the top surface of the first conductive line 108. In the planarization process, the Removal Rate (RR) of the first oxide layer 112 is much greater than that of the first conductive lines 108, and thus, after the planarization process, the top surfaces of the first oxide layers 112 between adjacent first conductive lines 108 are lower than the top surfaces of the first conductive lines 108, and depressions (Dishing) occur in the top surfaces of the first oxide layers 112 between adjacent first conductive lines 108.
That is, the top surface of the first oxide layer and the top surface of the first conductive line between the adjacent first conductive lines cannot be flush, it is difficult to continue forming the top memory cell over the bottom memory cell, and Leakage (LKG) of the phase change memory may occur. Accordingly, a further improvement in the manufacturing process of the phase change memory is still needed.
In view of the above, embodiments of the present disclosure provide a phase change memory and a method for manufacturing the same.
Referring to fig. 2, fig. 2 is a flow chart illustrating a method for manufacturing a phase change memory according to an embodiment of the disclosure. As shown in fig. 2, an embodiment of the present disclosure provides a method for manufacturing a phase change memory, the method including:
step S210, providing a semiconductor structure, wherein the semiconductor structure comprises first storage units, isolation layers arranged between adjacent first storage units, first conductive wires arranged on one side of each first storage unit, the surfaces of the first conductive wires protruding out of the surfaces of the isolation layers, and first grooves formed by the adjacent first conductive wires and the isolation layers;
step S220, forming a first dielectric layer which covers the side wall and the bottom of the first groove and covers the first conductive wire so as to form a second groove in the first groove;
step S230, forming a second dielectric layer which covers the side wall and the bottom of the second groove and covers the first dielectric layer;
And step S240, performing planarization treatment to expose the first conductive line, wherein the removal rate of the second dielectric layer is smaller than that of the first dielectric layer in the planarization treatment.
Referring to fig. 3A to 3D, fig. 3A to 3D are cross-sectional views of a phase change memory provided in an embodiment of the present disclosure during a manufacturing process. The manufacturing process of the phase change memory provided by the embodiment of the present disclosure will be described in detail with reference to fig. 2 and 3A to 3D.
In the embodiment of the disclosure, in step S210, a semiconductor structure 302 is provided, which includes a first memory cell 304, a first isolation layer 306 disposed between adjacent first memory cells 304, and a first conductive line 308 disposed on one side of the first memory cell 304, wherein a surface of the first conductive line 308 protrudes from a surface of the first isolation layer 306, and adjacent first conductive lines 308 and the first isolation layer 306 together form a first recess 310.
As shown in FIG. 3A, in some embodiments, step S210 includes forming a second conductive line 320, forming first memory cells 304 on a side of the second conductive line 320, the first memory cells 304 being spaced apart along both the D1 direction and the D2 direction, forming first conductive lines 308 on a side of the first memory cells 304 remote from the second conductive line 320, wherein the first conductive lines 308 extend along the D2 direction and the second conductive lines 320 extend along the D1 direction.
Illustratively, forming the second conductive line 320 may include providing a substrate, forming a second conductive material layer on a side of the substrate, forming a first storage stack layer on a side of the second conductive material layer remote from the substrate, sequentially etching the first storage stack layer and the second conductive material layer in a D3 direction to form a plurality of first trenches extending in a D1 direction, wherein the etched second conductive material layer forms the second conductive line 320 extending in the D1 direction, and the etched first storage stack layer forms a first storage stack stripe extending in the D1 direction.
Here, the substrate may include a semiconductor substrate, specifically at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art, and may include other semiconductor material-containing substrates such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, a silicon-germanium substrate, etc.
Here, the first memory stack layer may include a first electrode layer, a phase change layer, a second electrode layer, a gate layer, and a third electrode layer stacked in this order in the D3 direction.
Here, the first electrode layer, the second electrode layer, and the third electrode layer may be used to transfer an electrical signal, and may include a conductive material, such as a metal material, a metal nitride, or any combination thereof. The metal material may be, for example, platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or titanium (Ti), or the like. In some embodiments, the first electrode layer, the second electrode layer, and the third electrode layer may include carbon electrodes.
Here, the phase change layer may include a phase change material. The phase change material may be an alloy of chalcogenide compounds such as germanium antimony telluride compound (Ge-Sb-Te compound, GST), germanium antimony compound, indium germanium telluride compound, aluminum selenium telluride compound, indium selenium telluride compound, aluminum indium selenium telluride compound, and the like. In this embodiment, taking the material of the phase-change layer as GST as an example, the GST material can realize reversible transformation between amorphous and crystalline states. In the amorphous state, the GST material has a short range atomic energy level and a low free electron density, resulting in a high resistivity, and in the crystalline state, the GST material has a long range atomic energy level and a high free electron density, resulting in a low resistivity. The phase change memory utilizes the resistance difference of the phase change material between different phase states to realize information storage, and the phase change material is subjected to physical phase change by applying different voltage or current pulse signals on the phase change layer, namely, the phase change material is subjected to reciprocal conversion between a crystalline state (low-resistance state) and an amorphous state (high-resistance state), so that information writing and erasing operations are realized to store data.
Here, the gating layer may include a threshold switch material, such as an ovonic threshold switch (Ovonic Threshold Switching, OTS) material, which may be a chalcogenide material, such as GeSeAs, geTeAs, geSeTeSe, geSe, seAs, geTe, siTe, or the like. The bidirectional threshold switch is used for controlling the switch of the gating device by using an electrical signal, when the applied electrical signal is higher than the threshold voltage, the OTS material is switched from a high-resistance state to a low-resistance state, and when the electrical signal is removed, the OTS material is switched from the low-resistance state to the high-resistance state, and the OTS is in a closed state. The gating layer is used for controlling the current flowing through the phase-change layer, keeps the on state when the erasing operation is performed on the phase-change layer, and keeps the off state after the erasing operation is completed, so as to avoid the read-write crosstalk between the memory cells.
Here, the process of forming the first memory stack layer may include, but is not limited to, physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atomic Layer Deposition, ALD), or any combination thereof.
Here, the material of the second conductive line 320 may include a conductive material, for example, a metal material. Illustratively, the second conductive line may include metallic tungsten.
Here, the process of forming the second conductive material layer may include, but is not limited to PVD, CVD, ALD or any combination thereof.
Illustratively, forming the first memory cell 304 and the first conductive line 308 on one side of the second conductive line 320 may include filling a second isolation material in the first trench to form a second isolation layer such that a first memory stack stripe surface and a second isolation layer surface are substantially flush, forming a first conductive material layer on one side of the first memory stack stripe and the second isolation layer away from the second conductive line, sequentially etching the first conductive material layer and the first memory stack stripe in a D3 direction to form a plurality of second trenches extending in the D2 direction and exposing the second conductive line 320, wherein the etched first conductive material layer forms the first conductive line 308 extending in the D2 direction, and the etched first memory stack stripe forms the plurality of first memory cells 304 arranged at intervals in both the D1 direction and the D2 direction.
Here, the orthographic projection shape of the first memory cell 304 on the substrate plane may be a circle, a quadrangle, or other shapes. Or the cross-sectional shape of the first memory cell 304 in the direction perpendicular to D3 may be circular, quadrangular, or other shapes. The present disclosure is not particularly limited to the orthographic projection shape (or cross-sectional shape) of the first storage unit 304.
Here, the material of the first conductive line 308 may include a conductive material, for example, a metal material. Illustratively, the first conductive line 308 may include metallic tungsten.
Here, the process of forming the first conductive material layer may include, but is not limited to PVD, CVD, ALD or any combination thereof.
Here, the material of the second isolation layer may include, but is not limited to, spin-On-Dielectric (SOD).
The first etching forms a first groove extending along the direction D1, the etching depth is the sum of the thicknesses of the second conductive material layer and the first storage stack layer, and the second etching forms a second groove extending along the direction D2, and the etching depth is the sum of the thicknesses of the first storage stack layer and the first conductive material layer.
Illustratively, forming the semiconductor structure may further include filling the first isolation material in the second trench to form a first isolation material layer such that the first conductive line surface and the first isolation layer surface are substantially flush, and etching back a portion of the first isolation material layer to form a first isolation layer exposing the first conductive line sidewalls and the top surface. The first conductive line 308 extends along the D2 direction, the first conductive line 308 includes two sidewalls disposed opposite to each other along the D1 direction, and a bottom surface and a top surface disposed opposite to each other along the D3 direction, the bottom surface of the first conductive line 308 is close to the first memory cell 304, and the top surface of the first conductive line 308 is far from the first memory cell 304.
Here, a second isolation layer is provided between adjacent first memory cells 304 in the D2 direction, and a first isolation layer 306 is provided between adjacent first memory cells 304 in the D1 direction. Illustratively, the first memory cells 304 arranged at intervals along the D1 direction and the D2 direction may be isolated by SOD.
It should be noted that, before the second isolation material is filled in the first trench, a barrier layer covering the sidewalls of the first storage stack stripe may be formed, and/or, before the first isolation material is filled in the second trench, a barrier layer covering the sidewalls of the first storage unit may be formed.
As also shown in fig. 3A, portions of the first isolation material layer are removed by etching back, and portions of the barrier layer covering sidewalls of the first conductive lines 308 are removed to expose top surfaces and portions of the sidewalls of the first conductive lines 308, with the remaining first isolation material layer forming a first isolation layer. At this time, not all sidewalls of the first conductive line 308 are exposed, and a portion of the sidewalls of the first conductive line 308 are still covered by the barrier layer 324. In other words, the first isolation layer 306 surface is higher than the bottom surface of the first conductive line 308 and the first isolation layer 306 surface is lower than the top surface of the first conductive line 308. The top surfaces of the first conductive lines 308 protrude from the surface of the first isolation layer 306, and after etching back, first grooves 310 may be formed between adjacent first conductive lines 308. The sidewalls of the first groove 310 are two sidewalls of the first conductive line 308 opposite to each other along the D1 direction, and the bottom of the first groove 310 exposes the surface of the first isolation layer 306.
Here, the material of the first isolation layer 306 may include, but is not limited to, SOD.
In addition, the substrate may include a chip region in which the chip structure, for example, the first conductive line, the second conductive line, and the first memory cell may be disposed, and a scribe line region surrounding the chip region in which the test structure for testing the chip structure may be disposed. The dashed lines in fig. 3A to 3D illustrate the dicing streets.
In the embodiment of the present disclosure, in step S220, a first dielectric layer 312 covering sidewalls and bottom of the first recess 310 and covering the first conductive line 308 is formed to form a second recess 314 in the first recess 310.
As shown in fig. 3B, the first dielectric layer 312 covers the first groove 310 sidewall, i.e., the first dielectric layer 312 covers the first conductive line 308 sidewall, the first dielectric layer 312 also covers the first groove 310 bottom, i.e., the first dielectric layer 312 also covers the first isolation layer 306 surface, and the first dielectric layer 312 also covers the first conductive line 308, i.e., the first dielectric layer 312 also covers the first conductive line 308 top surface. That is, the first dielectric layer 312 covers the sidewalls and top surface of the first conductive lines 308 and covers the surface of the first isolation layer 306. At this time, the thickness of the first dielectric layer 312 is smaller, and the first dielectric layer 312 does not fill the first recess 310, but forms the second recess 314 in the first recess 310. Illustratively, the first dielectric layer 312 may be, for example, 50 angstroms thick.
Here, the first dielectric layer 312 may include, but is not limited to, a silicon oxide material.
Here, the process of forming the first dielectric layer 312 may include ALD.
Here, the width of the first groove 310 in the D1 direction is denoted as W1, and the depth of the first groove 310 in the D3 direction is denoted as H1. Let D be the thickness of the first dielectric layer 312, the width of the second groove 314 along the D1 direction is (W1-2*d), and the depth of the second groove 314 along the D3 direction is H1.
In the embodiment of the present disclosure, in step S230, a second dielectric layer 316 is formed to cover the sidewalls and bottom of the second recess 314 and to cover the first dielectric layer 312.
As shown in fig. 3C, the second dielectric layer 316 covers the second recess 314 and fills the second recess 314, and a third dielectric layer 318 is formed to cover the second dielectric layer 316. At this time, the thickness of the second dielectric layer 316 is larger than that of the first dielectric layer 312. The second dielectric layer 316 may be, for example, 200 angstroms thick and the third dielectric layer 318 may be, for example, 5000 angstroms thick.
Here, the second dielectric layer 316 and the third dielectric layer 318 may each include, but are not limited to, a silicon oxide material.
Here, the process of forming the second dielectric layer 316 may include ALD.
Here, the process of forming the third dielectric layer 318 may include CVD. Illustratively, the third dielectric layer 318 is formed using tetraethyl siloxane (TEOS) as a starting material.
In the embodiment of the disclosure, in step S240, a planarization process is performed to expose the first conductive line 308, where the removal rate of the second dielectric layer 316 is smaller than the removal rate of the first dielectric layer 312 in the planarization process.
As shown in fig. 3D, the third dielectric layer 318, the second dielectric layer 316, and the first dielectric layer 312 are planarized until the top surfaces of the first conductive lines 308 are exposed such that the top surfaces of the first conductive lines 308 and the second dielectric layer 316 are substantially flush. In the planarization process, the removal rate of the second dielectric layer 316 is smaller than that of the first dielectric layer 312, which is beneficial to making the top surface of the first conductive line 308 substantially flush with the surface of the second dielectric layer 316, thereby improving the yield of the phase change memory and improving the electrical parameters of the phase change memory.
Here, substantially flush means that the difference in height between the top surface of the first conductive line 308 and the surface of the second dielectric layer 316 in the D3 direction is 0, or that the difference in height between the top surface of the first conductive line 308 and the surface of the second dielectric layer 316 in the D3 direction satisfies the process error range. In the embodiment of the disclosure, the height difference between the surface of the second dielectric layer and the top surface of the first conductive line between adjacent first conductive layers is smaller (or the recess formed by the surface of the second dielectric layer is smaller) or the height difference is 0, compared to the recess formed by the surface of the first oxide layer between adjacent first conductive lines.
Here, the planarization process may include a Chemical Mechanical Polishing (CMP) process.
Illustratively, the polishing agent of the CMP process may be, for example, ceria.
In some embodiments, the removal rate of the first conductive line 308 and the second dielectric layer 316 during the planarization process may also be reduced by reducing the pressure of the planarization process, i.e., reducing the pressure during the planarization process may reduce the removal rate of the first conductive line 308 and reducing the pressure during the planarization process may also reduce the removal rate of the second dielectric layer 316, with other parameters unchanged.
In some embodiments, the ratio between the removal rates of the second dielectric layer 316 and the first conductive line 308 (i.e., the selection ratio between the second dielectric layer 316 and the first conductive line 308) may range from 22 to 24.
The reduction of the removal rate of the first conductive line 308 by the pressure in the planarization process is different from the reduction of the second dielectric layer 316. In some embodiments, the pressure of the planarization process is reduced, as is the selectivity between the second dielectric layer 316 and the first conductive line 308.
In some embodiments, the process of forming the first dielectric layer 312 includes a first atomic layer deposition process and the process of forming the second dielectric layer 316 includes a second atomic layer deposition process, wherein the radio frequency power in the second atomic layer deposition process is greater than the radio frequency power in the first atomic layer deposition process. In some embodiments, the density of the second dielectric layer 316 is greater than the density of the first dielectric layer 312.
Here, the reaction principle of forming the first dielectric layer 312 or the second dielectric layer 316 is that atomic thin films are formed by alternately pulsing precursors into the reaction chamber and performing chemisorption reactions on the substrate surface. The method comprises the steps of (1) leading a precursor to be adsorbed on the surface after surface pretreatment, leading the precursor into the atmosphere, forming an adsorption layer on the surface through a chemical reaction mode, (2) leading in inert gas to wash away the precursor, (3) leading in another precursor after the adsorption layer is formed, forming plasma under the action of alternating current and reacting with the precursor to form a reaction layer, (4) leading in inert gas to wash away reaction byproducts, and (5) repeatedly executing the above 4 steps until a required film is formed. The reaction process is mainly carried out in the step (3), and the density of the plasma is improved by increasing the power of alternating current, so that the dissociation of the O 2 precursor is more sufficient, and the density of the film layer is further improved.
Here, the process of forming the first dielectric layer 312 may include a first atomic layer deposition process, where radio frequency power in the first atomic layer deposition process is smaller, and the density of forming the first dielectric layer 312 is smaller. The process of forming the second dielectric layer 316 may include a second atomic layer deposition process, where the radio frequency power in the second atomic layer deposition process is greater, so that the second dielectric layer 316 is formed with greater density. Thus, during the planarization process, the removal rate of the second dielectric layer 316 is less than the removal rate of the first dielectric layer 312.
On the one hand, if the first dielectric layer is formed only between the adjacent first conductive lines, the removal rate of the first conductive lines is greater than that of the first dielectric layer in the planarization process, and after the planarization process, larger pits are formed on the surface of the first dielectric layer between the adjacent first conductive lines, which is not beneficial for the subsequent formation of the second memory cells. On the other hand, if the second dielectric layer is formed only between adjacent first conductive lines, the high radio frequency power condition in forming the second dielectric layer may cause damage to the first conductive lines. In the embodiment of the disclosure, a first dielectric layer covering the side wall and the top surface of a first conductive wire is formed first, radio frequency power in a first atomic layer deposition process is smaller, the side wall and the top surface of the first conductive wire can be protected, a second dielectric layer filling a gap between adjacent first conductive wires is formed later, radio frequency power in the second atomic layer deposition process is larger, and the density of the formed second dielectric layer is larger. Because the density of the second medium layer is greater than that of the first medium layer, the removal rate of the second medium layer is smaller than that of the first medium layer in the planarization treatment.
The range of the rf power in the first atomic layer deposition process may be 300 to 500w, and the range of the rf power in the second atomic layer deposition process may be 800 to 1000w.
In some embodiments, the deposition duration in the first atomic layer deposition process is less than the deposition duration in the second atomic layer deposition process. In some embodiments, the thickness of the second dielectric layer 316 is greater than the thickness of the first dielectric layer 312. In some embodiments, the thickness of the second dielectric layer 316 ranges from 150 to 200 angstroms, and the thickness of the first dielectric layer 312 ranges from 50 to 100 angstroms.
Here, the deposition time period in the first atomic layer deposition process is shorter, and the first dielectric layer 312 covering the sidewall and the top surface of the first conductive line 308 and covering the surface of the first isolation layer 306 may be formed, where the thickness of the first dielectric layer 312 is smaller. The second atomic layer deposition process has a longer deposition time period, and the second dielectric layer 316 covering the first dielectric layer 312 may be formed, and at this time, the thickness of the second dielectric layer 316 is larger.
Referring to fig. 4, fig. 4 is a schematic diagram of the results of each parameter in comparative examples 1 and 2 and examples 1 to 4. As shown in fig. 4, in comparative example 1, the first dielectric layer was formed only under the condition of low rf power, and the thickness of the first dielectric layer was 250 a, at this time, the removal rate of the first dielectric layer was greater than the removal rate of the first conductive line in the planarization process, and the maximum height of the recess formed on the surface of the first dielectric layer after the planarization process was 80 a. Thus, after the planarization process, the first dielectric layer and the first conductive line cannot be flush, and it is difficult to continue forming the second memory cell over the first memory cell.
In comparative example 2, the second dielectric layer was formed only under the high rf power condition, and the thickness of the second dielectric layer was 250 a, at this time, the removal rate of the second dielectric layer was smaller than the removal rate of the first dielectric layer in the planarization process, and the maximum height of the recess formed on the surface of the second dielectric layer after the planarization process was 40 a. In this way, the second dielectric layer and the first conductive line are substantially flush, and the second memory cell can continue to be formed over the first memory cell, however, the high radio frequency power has resulted in damage to the first memory cell.
In each of embodiments 1 to 4, the first dielectric layer is formed under the condition of low rf power, and then the second dielectric layer is formed under the condition of high rf power, and the sum of the thicknesses of the first dielectric layer and the second dielectric layer is 250 a. Therefore, the first dielectric layer is formed under the condition of low radio frequency power, the first storage unit can be prevented from being damaged, the second dielectric layer is formed under the condition of high radio frequency power, the difference between removal rates in planarization treatment can be reduced, the maximum height of the concave formed on the surface of the second dielectric layer is reduced, the top surface of the first conductive wire and the surface of the second dielectric layer are enabled to be basically flush, and further the yield of the phase change memory is improved, and the electrical parameters of the phase change memory are improved.
In some embodiments, after step S240, the method further includes forming a third conductive line on a side of the first conductive line 308 away from the first memory cell 304, the third conductive line extending in the direction D2 and the first conductive line 308 and the third conductive line being connected in a one-to-one correspondence, forming a second memory cell on a side of the third conductive line away from the first conductive line 308, the second memory cells being spaced apart in both the direction D1 and the direction D2, and forming a fourth conductive line on a side of the second memory cell away from the third conductive line, the fourth conductive line extending in the direction D1.
Illustratively, forming the third conductive line may include forming a third conductive material layer on a side of the first conductive line remote from the first memory cell, the third conductive material layer covering a top surface of the first conductive line 308 and a surface of the second dielectric layer 316, forming a second memory stack layer on a side of the third conductive material layer remote from the first conductive line, sequentially etching the second memory stack layer and the third conductive material layer in a D3 direction to form a plurality of third trenches extending in the D2 direction and exposing the second dielectric layer 316, wherein the etched third conductive material layer forms a third conductive line extending in the D2 direction, and the etched second memory stack layer forms a second memory stack stripe extending in the D2 direction.
Here, the third conductive lines may be connected in one-to-one correspondence with the first conductive lines.
The forming of the second memory cell and the fourth conductive line at the side of the third conductive line far from the first conductive line may further include filling a third isolation material in the third trench to form a third isolation layer such that the surface of the second memory stack bar and the surface of the third isolation layer are substantially flush, forming a fourth conductive material layer at the side of the second memory stack bar and the third isolation layer far from the third conductive line, sequentially etching the fourth conductive material layer and the second memory stack bar along the D3 direction to form a plurality of fourth trenches extending along the D1 direction and exposing the third conductive line, wherein the etched fourth conductive material layer forms the fourth conductive line extending along the D1 direction, and the etched second memory stack bar forms a plurality of second memory cells arranged at intervals along both the D1 direction and the D2 direction.
Here, the third etching forms a third trench extending in the D2 direction, the etching depth being the sum of thicknesses of the third conductive material layer and the second storage stack layer, and the fourth etching forms a fourth trench extending in the D1 direction, the etching depth being the sum of thicknesses of the second storage stack layer and the fourth conductive material layer.
Here, the second storage stack layer and the second storage unit may refer to the above description of the first storage stack layer and the first storage unit, and will not be repeated herein.
Here, the materials of the third conductive line and the fourth conductive line, and the process of forming the third conductive line and the fourth conductive line may refer to the above description of the first conductive line and the second conductive line, which is not repeated herein.
Illustratively, forming the phase change memory may further include filling the fourth isolation material in the fourth trench to form a fourth isolation layer such that a surface of the fourth conductive line and a surface of the fourth isolation layer are substantially flush.
Here, the materials of the third isolation layer and the fourth isolation layer, and the process of forming the third isolation layer and the fourth isolation layer may be described with reference to the above description of the first isolation layer and the second isolation layer, which are not repeated herein.
Here, a third isolation layer is provided between the adjacent second memory cells in the D1 direction, and a fourth isolation layer is provided between the adjacent second memory cells in the D2 direction. Illustratively, the second memory cells arranged at intervals along the D1 direction and the D2 direction can be isolated by SOD.
Here, the first conductive Line may also be referred to as a Bottom Bit Line (Bottom Bit Line), the second conductive Line may also be referred to as a Bottom Word Line (Bottom Word Line), and the first memory cell disposed at the intersection between the first conductive Line and the second conductive Line may also be referred to as a Bottom memory cell. The third conductive Line may also be referred to as a Top Word Line (Top Word Line), the fourth conductive Line may also be referred to as a Top Bit Line (Top Bit Line), and the second memory cell disposed at the intersection between the third conductive Line and the fourth conductive Line may also be referred to as a Top memory cell.
As shown in fig. 3D, an embodiment of the disclosure provides a phase change memory 300, where the phase change memory 300 includes first memory cells 304 arranged at intervals along a D1 direction and a D2 direction, first conductive lines 308 disposed on one side of the first memory cells 304 and extending along the D2 direction, second conductive lines 320 disposed on one side of the first memory cells 304 away from the first conductive lines 308 and extending along the D1 direction, first dielectric layers 312 disposed between adjacent first conductive lines 308, the first dielectric layers 312 covering two sidewalls of the first conductive lines 308 disposed opposite to each other along the D1 direction, and second dielectric layers 316 disposed between the first dielectric layers 312 of the sidewalls of the adjacent first conductive lines 308.
Here, the phase change memory 300 further includes a first isolation layer 306 disposed between adjacent first memory cells 304 in the D1 direction. The first dielectric layer 312 includes a first portion and a second portion, the first portion of the first dielectric layer 312 covers two sidewalls of the first conductive line 308 that are disposed opposite to each other along the D1 direction, and the second portion of the first dielectric layer 312 covers the surface of the first isolation layer 306. The second dielectric layer 316 is disposed between the first dielectric layers 312 of adjacent first conductive lines 308, and the second dielectric layer 316 is in contact with both the first and second portions of the first dielectric layer 312. The first dielectric layer 312 covers both sidewalls of the second dielectric layer 316 disposed opposite to each other in the D1 direction and covers a surface of the second dielectric layer 316 near the first isolation layer 306, i.e., the first dielectric layer 312 partially surrounds the second dielectric layer 316.
In some embodiments, the density of the second dielectric layer 316 is greater than the density of the first dielectric layer 312.
In some embodiments, the phase change memory 300 further includes a third conductive line disposed on a side of the first conductive line 308 away from the first memory cell 304, the third conductive line extending in the D2 direction and being connected in one-to-one correspondence to the third conductive line, a second memory cell disposed on a side of the third conductive line away from the first conductive line, the second memory cells being spaced apart in both the D1 direction and the D2 direction, and a fourth conductive line disposed on a side of the second memory cell away from the third conductive line, the fourth conductive line extending in the D1 direction.
Referring to fig. 5, fig. 5 is a block diagram of a memory system provided by an embodiment of the present disclosure. As shown in fig. 5, the presently disclosed embodiments also provide a memory system 400 including a phase change memory 300 as in the above-described aspects, and a controller 402 coupled to the phase change memory 300 and configured to control the phase change memory 300.
Embodiments of the present disclosure provide a phase change memory and a method of manufacturing the same. In the embodiment of the disclosure, a first dielectric layer covering the side wall and the top surface of a first conductive wire is formed to protect the side wall and the top surface of the first conductive wire in the subsequent process of forming a second dielectric layer, the second dielectric layer is formed to fill gaps between adjacent first conductive wires, and the removal rate of the second dielectric layer is smaller than that of the first dielectric layer in the process of flattening the second dielectric layer and the first dielectric layer, so that the height difference between the top surface of the first conductive wire and the surface of the second dielectric layer is reduced, the top surface of the first conductive wire and the surface of the second dielectric layer are basically flush, and further the yield of the phase change memory is improved and the electrical parameters of the phase change memory are improved.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.
The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure, but rather, the equivalent structural changes made by the present disclosure and the accompanying drawings under the inventive concept of the present disclosure, or the direct/indirect application in other related technical fields are included in the scope of the present disclosure.
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