CN119153458B - Power submodule and power module having the same - Google Patents

Abstract

The application provides a power sub-module and a power module with the same, wherein the power sub-module comprises an upper half-bridge unit, a lower half-bridge unit and a lower half-bridge unit, wherein the upper half-bridge unit comprises an upper substrate, a plurality of upper MOSFET chips connected in parallel, an upper series diode and a plurality of upper diode chips connected in parallel, the number of the upper MOSFET chips is even, the two upper MOSFET chips are an upper MOSFET chip group, an upper series diode is arranged between the two upper MOSFET chip groups, the lower half-bridge unit comprises a lower substrate, a plurality of lower MOSFET chips connected in parallel, a lower series diode and a plurality of lower diode chips connected in parallel, the number of the lower MOSFET chips is even, the two lower MOSFET chips are a lower MOSFET chip group, and a lower series diode is arranged between the two lower MOSFET chip groups. By the technical scheme provided by the application, the problem that the parasitic inductance of the power module in the related technology is large and the application of the silicon carbide device in the high-voltage field is limited can be solved.

Description

Power sub-module and power module with same

Technical Field

The invention relates to the technical field of power devices, in particular to a power sub-module and a power module with the same.

Background

A fully controlled device power field effect transistor (MOSFET) is a semiconductor device that belongs to a voltage controlled device that uses a gate voltage to control the flow of current. MOSFETs are field effect transistors of metal-oxide-semiconductor (MOS) structure and are widely used in various electronic circuits, in particular in the field of power electronics. A fully controlled device power field effect transistor (MOSFET) is considered to be an ideal switching device by virtue of its high input impedance, fast switching rate, low drive requirements, etc. However, the power processing capability of the traditional silicon-based power MOSFET device in the high-voltage field is limited by the internal resistance of the chip, and how to reduce the on-resistance of the chip and improve the breakdown voltage of the chip is the research focus of the next-generation power MOSFET device.

In the related art, a wide bandgap semiconductor material represented by a silicon carbide material is considered to be an ideal material for next-generation high-voltage power devices due to its excellent material characteristics, such as a wide bandgap, a high critical breakdown field strength, and a high saturation carrier mobility. Among all silicon carbide devices, silicon carbide MOSFETs have the advantages of low on-resistance, fast switching speed, high withstand voltage, etc., and have gradually replaced silicon-based MOSFETs and IGBT devices. Because the current level of a single chip is low, a plurality of chips are generally packaged in parallel to form a power module under the application of high current. At present, the packaging of the silicon carbide power module still adopts the packaging of the traditional silicon-based power module, the parasitic inductance of the power module is larger, the switching speed of silicon carbide is high, the larger parasitic inductance generates larger voltage overshoot in switching transient state, the application of the silicon carbide device in the high-voltage field is severely limited, and the advantage of high withstand voltage of the silicon carbide can not be fully exerted.

Therefore, the parasitic inductance of the power module is larger in the related art, and the application of the silicon carbide device in the high-voltage field is limited.

Disclosure of Invention

The invention provides a power sub-module and a power module with the same, which are used for solving the problems that parasitic inductance of the power module in the related technology is large and the application of a silicon carbide device in the high-voltage field is limited.

According to one aspect of the invention, a power sub-module is provided, the power sub-module comprises an upper half-bridge unit, a lower half-bridge unit and a power sub-module, wherein the upper half-bridge unit comprises an upper substrate, a plurality of upper MOSFET chips connected in parallel, an upper series diode and a plurality of upper diode chips connected in parallel, the number of the upper MOSFET chips is even, the two upper MOSFET chips are an upper MOSFET chip group, one upper series diode is arranged between the two upper MOSFET chip groups, the drain electrode of the upper MOSFET chip is connected with a first upper drain electrode conducting layer of the upper substrate, the power source electrode of the upper MOSFET chip is connected with the anode of the upper diode chip, the cathode of the upper series diode is connected with a first upper drain electrode conducting layer, the anode of the upper series diode is connected with a second upper drain electrode conducting layer of the upper substrate, the cathode of the upper diode chip is connected with a second upper drain electrode conducting layer of the upper substrate, the anode of the upper diode chip is connected with an upper power source electrode conducting layer of the upper substrate, the lower half-bridge unit comprises a lower substrate, a plurality of lower MOSFET chips connected in parallel, a lower series diode and a plurality of lower diode chips connected in parallel, the lower diode chips are connected in parallel, the number of the lower MOSFET chips is an even, the lower MOSFET chip is connected in parallel, the lower MOSFET chip is connected with the lower diode chip is connected in parallel, the power sub-chip is connected with a second upper drain electrode conducting layer, the lower diode chip is connected in parallel, the lower diode chip is connected with the second drain electrode is connected with the lower drain electrode conducting layer, and a power source electrode is connected with the lower diode chip is connected with the lower drain electrode.

The upper half-bridge unit further comprises an upper drain power terminal connected with the second upper drain conductive layer, and the lower half-bridge unit further comprises a first lower output power terminal, a second lower output power terminal and a lower power source power terminal, wherein the lower power source power terminal is connected with the lower power source conductive layer, and the first lower output power terminal and the second lower output power terminal are respectively connected with the second lower drain conductive layer.

Further, the upper drain power terminal, the first lower output power terminal, the second lower output power terminal, and the lower power source power terminal are all low-threaded power terminals.

Further, two upper power source electrode conducting layers are arranged on the upper substrate, the two upper power source electrode conducting layers are respectively arranged on two sides of an upper drain electrode power terminal, the second lower drain electrode conducting layer comprises a first section, a second section and a third section, the first section and the third section are respectively connected with two ends of the second section, the first section and the third section are located on the same side of the second section, a plurality of lower diode chips are arranged on the second section at intervals along the extending direction of the second section, a second lower output power terminal is arranged on the first section, a first lower output power terminal is arranged on the third section, the first section is connected with one upper power source electrode conducting layer, and the third section is connected with the other upper power source electrode conducting layer.

Further, the second upper drain conductive layer includes a fourth section and a fifth section perpendicular to each other, one end of the fifth section is connected to a middle portion of the fourth section, the plurality of upper diode chips are disposed on the fourth section at intervals along a length direction of the fourth section, and the upper drain power terminal is disposed on the fifth section.

Further, the first section is connected with one of the upper power source electrode conductive layers through a first bridge arm connection bonding wire, and the third section is connected with the other upper power source electrode conductive layer through a second bridge arm connection bonding wire.

Further, the grid electrode of the upper MOSFET chip is connected with a first upper grid electrode conducting layer of the upper substrate, the driving source electrode of the upper MOSFET chip is connected with an upper driving source electrode conducting layer of the upper substrate, the upper half-bridge unit further comprises an upper driving resistor, a first upper grid electrode signal terminal, a first upper driving source electrode signal terminal, a second upper grid electrode signal terminal and a second upper grid electrode signal terminal, the first upper grid electrode conducting layer is connected with the second upper grid electrode conducting layer of the upper substrate, the first upper grid electrode signal terminal and the second upper grid electrode signal terminal are respectively connected with the second upper grid electrode conducting layer, the first upper driving source electrode signal terminal and the second upper driving source electrode signal terminal are respectively connected with the upper driving source electrode conducting layer, the grid electrode of the lower MOSFET chip is connected with a first lower grid electrode conducting layer of the lower substrate, the driving source electrode of the lower MOSFET chip is connected with a lower driving source electrode conducting layer of the lower substrate, the lower half-bridge unit further comprises a lower driving resistor, a first lower driving source electrode signal terminal, a first lower grid electrode signal terminal, a second lower driving source electrode signal terminal and a second lower driving source electrode signal terminal, a second lower grid electrode signal terminal are respectively connected with the second lower grid electrode conducting layer, the first lower grid electrode signal terminal is respectively connected with the lower grid electrode conducting layer, the first upper driving source electrode conducting layer is respectively connected with the lower grid electrode conducting layer.

Further, the first upper drain electrode conducting layer is located at one side of the second upper drain electrode conducting layer far away from the upper power source electrode conducting layer, the plurality of upper MOSFET chips are distributed at intervals along the length direction of the first upper drain electrode conducting layer, the upper semi-bridge unit comprises a plurality of upper driving resistors, the upper substrate is provided with a plurality of first upper gate electrode conducting layers, the plurality of first upper gate electrode conducting layers are arranged in one-to-one correspondence with the plurality of upper MOSFET chips, the plurality of first upper gate electrode conducting layers are all located at one side of the first upper drain electrode conducting layer far away from the first upper drain electrode conducting layer, the second upper gate electrode conducting layer is located at one side of the first upper gate electrode conducting layer far away from the first upper gate electrode conducting layer, the first lower drain electrode conducting layer is located at one side of the second lower drain electrode conducting layer far away from the lower power source electrode conducting layer, the lower semi-bridge unit comprises a plurality of lower driving resistors, the lower substrate is provided with a plurality of first lower gate electrode conducting layers, the plurality of first lower gate electrode conducting layers are arranged in one-to-one correspondence with the plurality of first lower gate electrode conducting layers, the first lower gate electrode conducting layers are located at one side of the first lower gate electrode conducting layers far away from the first lower gate electrode conducting layers, and the first lower gate electrode conducting layers are located at one side of the first lower gate electrode conducting layers far away from the first lower gate electrode conducting layers.

Further, the first upper drain electrode conductive layer, the second upper grid electrode conductive layer and the upper driving source electrode conductive layer are all of long-strip-shaped structures, and the first lower drain electrode conductive layer, the second lower grid electrode conductive layer and the lower driving source electrode conductive layer are all of long-strip-shaped structures.

Further, the drain electrode of the upper MOSFET chip is sintered with the first upper drain electrode conductive layer by solder, the power source electrode of the upper MOSFET chip is sintered with the anode of the upper diode chip by a first upper MOSFET power source bonding wire, the drain electrode of the lower MOSFET chip is sintered with the first upper gate electrode conductive layer by a first lower MOSFET power source bonding wire, the gate electrode of the lower MOSFET chip is sintered with the first lower gate electrode conductive layer by a lower MOSFET power source bonding wire, the cathode of the upper series diode chip is sintered with the first upper drain electrode conductive layer by solder, the anode of the upper series diode chip is sintered with the second upper drain electrode conductive layer by an upper series diode anode bonding wire, the anode of the upper diode chip is sintered with the second upper drain electrode conductive layer by solder, the anode of the upper diode chip is sintered with the upper power source electrode conductive layer by a second upper MOSFET power source bonding wire, the drain electrode of the lower MOSFET chip is sintered with the first lower drain electrode conductive layer by solder, the power source electrode of the lower MOSFET chip is sintered with the first lower drain electrode conductive layer by a first lower MOSFET power source bonding wire, the gate electrode of the lower MOSFET chip is connected with the anode of the lower MOSFET chip by a lower MOSFET power source electrode bonding wire, the lower MOSFET chip is sintered with the first lower drain electrode conductive layer by a lower MOSFET power source electrode bonding wire, the lower MOSFET chip is connected with the second drain electrode conductive layer by a lower MOSFET power source electrode of the lower MOSFET chip is sintered with the second lower drain electrode conductive layer by a lower diode bonding wire, and the lower MOSFET power source electrode of the lower MOSFET chip is sintered with the lower power source electrode conductive layer by a lower diode.

Further, the upper half-bridge unit comprises four upper MOSFET chips connected in parallel, an upper series diode and three upper diode chips connected in parallel, and the lower half-bridge unit comprises four lower MOSFET chips connected in parallel, a lower series diode and three lower diode chips connected in parallel.

Further, the upper substrate and the lower substrate are both ceramic substrates.

According to another aspect of the invention, a power module is provided, which comprises a substrate and a power sub-module arranged on the substrate, wherein the power sub-module is the power sub-module provided above.

Further, the power module includes a plurality of power sub-modules.

Further, the plurality of power sub-modules are arranged at intervals in the length direction of the substrate, and the upper half-bridge unit and the lower half-bridge unit of each power sub-module are arranged at intervals in the width direction of the substrate.

Further, the current flow directions of two adjacent power sub-modules are opposite.

Further, the lower surface of the upper substrate of the power sub-module is connected with the substrate through solder sintering, and the lower surface of the lower substrate of the power sub-module is connected with the substrate through solder sintering.

By applying the technical scheme of the invention, the power sub-module comprises an upper half-bridge unit and a lower half-bridge unit, wherein the upper half-bridge unit comprises an upper substrate, a plurality of upper MOSFET chips connected in parallel, an upper series diode and a plurality of upper diode chips connected in parallel, the number of the upper MOSFET chips is even, two upper MOSFET chips are an upper MOSFET chip set, and an upper series diode is arranged between the two upper MOSFET chip sets. The lower half-bridge unit comprises a lower substrate, a plurality of lower MOSFET chips connected in parallel, lower series diodes and a plurality of lower diode chips connected in parallel, wherein the number of the lower MOSFET chips is even, two lower MOSFET chips are lower MOSFET chip sets, and a lower series diode is arranged between the two lower MOSFET chip sets. With the adoption of the structure, the upper series diode can group a plurality of upper MOSFET chips which are connected in parallel, and the lower series diode can group a plurality of lower MOSFET chips which are connected in parallel, so that the current coupling effect is eliminated.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

fig. 1 shows a schematic structural diagram of a power module according to an embodiment of the present invention;

Fig. 2 shows a schematic structural diagram of a power sub-module according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of an upper half-bridge unit of a power sub-module according to an embodiment of the present invention;

Fig. 4 shows a schematic structural diagram of a lower half-bridge unit of a power sub-module according to an embodiment of the present invention;

fig. 5 shows a schematic diagram of a double pulse test circuit of a lower half bridge unit of a power sub-module according to an embodiment of the present invention;

FIG. 6 illustrates a power module circuit topology provided in accordance with an embodiment of the present invention;

FIG. 7 illustrates a current pattern of a power module provided in accordance with an embodiment of the present invention;

Fig. 8 is a schematic structural diagram illustrating another view angle of a power sub-module according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram illustrating another view angle of an upper half-bridge unit of a power sub-module according to an embodiment of the present invention;

Fig. 10 is a schematic structural diagram illustrating another view angle of a lower half-bridge unit of a power sub-module according to an embodiment of the present invention.

Wherein the above figures include the following reference numerals:

1. The device comprises a first sub-module, a second sub-module, a third sub-module, a fourth sub-module, a substrate, a lower half-bridge unit, an upper MOSFET grid bonding wire, an upper MOSFET driving source electrode bonding wire and an upper MOSFET driving source electrode bonding wire, wherein the first sub-module, the second sub-module, the third sub-module, the fourth sub-module, the substrate, the lower half-bridge unit, the upper MOSFET grid bonding wire and the upper MOSFET driving source electrode bonding wire are respectively arranged;

10. Upper series diode, 11, upper MOSFET chip, 12, first upper MOSFET power source bonding wire, 13, upper diode chip, 14, second upper MOSFET power source bonding wire, 15, upper power source conductive layer, 16, upper drain power terminal, 17, upper series diode anode bonding wire, 18, second upper drain conductive layer, 181, fourth segment, 182, fifth segment, 19, first upper drain conductive layer;

20. Upper drive resistor, upper substrate, 22, second upper grid electrode conductive layer, 23, upper drive source electrode conductive layer, 24, first upper grid electrode signal terminal, 25, first upper drive source electrode signal terminal, 26, second upper drive source electrode signal terminal, 27, second upper grid electrode signal terminal, 28, first lower output power terminal, 29, second lower MOSFET power source electrode bonding wire;

30. a first lower MOSFET power source bonding wire, a lower series diode anode bonding wire, a 32 lower series diode, a 33 second lower grid electrode conductive layer, a 34 lower driving source electrode conductive layer, a 35 first lower driving source electrode signal terminal, a 36 first lower grid electrode signal terminal, a 37 second lower driving source electrode signal terminal, a 38 second lower grid electrode signal terminal, a 39 lower MOSFET grid electrode bonding wire;

40. Lower MOSFET drive source electrode bonding wires, 41, lower drive resistors, 42, lower MOSFET chips, 43, a first lower drain electrode conducting layer, 44, a lower diode chip, 45, a second lower drain electrode conducting layer, 451, a first section, 452, a second section, 453, a third section, 46, a lower substrate, 47, a second lower output power terminal, 48, a lower power source power terminal, 49, a lower power source conducting layer;

50. The semiconductor device comprises a first upper grid electrode conductive layer, a first lower grid electrode conductive layer, a first bridge arm connecting bonding wire and a second bridge arm connecting bonding wire.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

As shown in fig. 1 to 10, an embodiment of the present invention provides a power sub-module including an upper half-bridge unit 7 and a lower half-bridge unit 6. The upper half-bridge unit 7 includes an upper substrate 21, a plurality of upper MOSFET chips 11 connected in parallel, an upper series diode 10, and a plurality of upper diode chips 13 connected in parallel, the number of the upper MOSFET chips 11 is even, and two upper MOSFET chips 11 are one upper MOSFET chip group, between which one upper series diode 10 is provided, the drain electrode of the upper MOSFET chip 11 is connected with a first upper drain electrode conductive layer 19 of the upper substrate 21, the power source electrode of the upper MOSFET chip 11 is connected with the anode electrode of the upper diode chip 13, the cathode electrode of the upper series diode 10 is connected with the first upper drain electrode conductive layer 19, the anode electrode of the upper series diode 10 is connected with a second upper drain electrode conductive layer 18 of the upper substrate 21, the cathode electrode of the upper diode chip 13 is connected with the second upper drain electrode conductive layer 18, and the anode electrode of the upper diode chip 13 is connected with an upper power source electrode conductive layer 15 of the upper substrate 21. The lower half-bridge unit 6 includes a lower substrate 46, a plurality of parallel lower MOSFET chips 42, a lower serial diode 32, and a plurality of parallel lower diode chips 44, the number of the lower MOSFET chips 42 is even, and two lower MOSFET chips 42 are one lower MOSFET chip group, between which one lower serial diode 32 is disposed, the drain of the lower MOSFET chip 42 is connected to the first lower drain conductive layer 43 of the lower substrate 46, the power source of the lower MOSFET chip 42 is connected to the anode of the lower diode chip 44, the cathode of the lower serial diode 32 is connected to the first lower drain conductive layer 43, the anode of the lower serial diode 32 is connected to the second lower drain conductive layer 45 of the lower substrate 46, the cathode of the lower diode chip 44 is connected to the second lower drain conductive layer 45, the anode of the lower diode chip 44 is connected to the lower power source conductive layer 49 of the lower substrate 46, and the upper power source conductive layer 15 is connected to the second lower drain conductive layer 45.

With the power sub-module provided in this embodiment, the upper half-bridge unit 7 includes an upper substrate 21, a plurality of upper MOSFET chips 11 connected in parallel, an upper series diode 10, and a plurality of upper diode chips 13 connected in parallel, where the number of the upper MOSFET chips 11 is even, two upper MOSFET chips 11 are an upper MOSFET chipset, and an upper series diode 10 is disposed between the two upper MOSFET chipsets. The lower half-bridge unit 6 includes a lower substrate 46, a plurality of parallel lower MOSFET chips 42, a lower series diode 32, and a plurality of parallel lower diode chips 44, the number of the lower MOSFET chips 42 is even, and two lower MOSFET chips 42 are a lower MOSFET chip set, between which one lower series diode 32 is disposed. With the above structure, the upper series diode 10 can group a plurality of upper MOSFET chips 11 connected in parallel, and the lower series diode 32 can group a plurality of lower MOSFET chips 42 connected in parallel, thereby eliminating the current coupling effect and realizing a better current sharing effect.

And, during the period when the upper MOSFET chip 11 is turned off, the upper diode chip 13 is turned on to perform current freewheel. During the off period of the lower MOSFET chip 42, the lower diode chip 44 is turned on for current freewheeling.

In order to explain how the power sub-module provided in this embodiment eliminates the current coupling effect, the following can be understood with reference to fig. 5 and the following description:

Fig. 5 is a schematic diagram of a double pulse test circuit of a lower half bridge unit according to an embodiment of the present invention, referring to fig. 5, v _DC is a dc voltage source for supplying power to a power loop of a power module. C _bus is a busbar capacitor for maintaining the DC voltage stable. L _load is a load inductance, and V _D is three parallel upper diode chips 13 in the upper half-bridge unit, and is used for freewheeling when four parallel lower MOSFET chips 42 in the lower half-bridge unit are turned off. Q ₁~Q₄ is the bottom MOSFET chip 42 in the bottom half-bridge cell, L _s is the source side stray inductance of the bottom MOSFET chip 42, L _g is the gate stray inductance of the bottom MOSFET chip 42, L _as is the drive source stray inductance of the bottom MOSFET chip 42, L _d is the drain side inter-branch stray inductance of the bottom MOSFET chip 42, L _b is the power source side inter-branch stray inductance of the bottom MOSFET chip 42, L _a is the gate side inter-branch stray inductance of the bottom MOSFET chip 42, L _c is the drive source side inter-branch stray inductance of the bottom MOSFET chip 42, i _d is the current through the load inductance, i _d1 is the current through Q ₁, i _d2 is the current through Q ₂, i _d3 is the current through Q ₃, i _d4 is the current through Q ₄. V _driver is a gate drive power supply for powering the drive loop, and R _g is a gate drive resistor. O is a power source current sink point, which is also a power source potential reference point when analyzing the current coupling effect, O ₁ is a power source current potential reference point of Q ₁, O ₂ is a power source current potential reference point of Q ₂, O ₃ is a power source current potential reference point of Q ₃, O ₄ is a power source current potential reference point of Q ₄, L ₁ is a parasitic inductance between a load inductance and a DC voltage source positive electrode, L ₂ is a parasitic inductance between a power source current potential reference point O and a DC voltage source negative electrode, ASO is a driving source current sink point, which is also a driving source potential reference point, and L ₃ is a parasitic inductance between a driving source potential reference point ASO and a DC voltage source negative electrode. i _g is the total current of the drive loop parallel chip, i _g1~i_g4 is the drive current of Q ₁~Q₄, and S ₁~S₄ is the power source of Q ₁~Q₄.

The principle of eliminating the influence of the current coupling effect of the power module is deduced and demonstrated below.

The drain current of the lower MOSFET chip 42 may represent i _d as follows:

wherein g _fs is the transconductance of the lower MOSFET chip 42, V _gs1 is the gate-source voltage difference of Q ₁, V _gs2 is the gate-source voltage difference of Q ₂, V _gs3 is the gate-source voltage difference of Q ₃, V _gs4 is the gate-source voltage difference of Q ₄, and V _th is the threshold voltage. i _g is the total current of the drive loop parallel chip, L _g2 is the gate parasitic inductance of Q ₂, L _g3 is the gate parasitic inductance of Q ₃, and i _g1~i_g4 is the gate current of Q ₁~Q₄. V _gs can be expressed in the drive loop by the following expression:

Since the lower MOSFET chip 42 belongs to a voltage controlled device, the required driving current is only several hundred milliamperes, and the drain current of a single lower MOSFET chip 42 is several tens amperes, so the current of the driving circuit is far smaller than that of the power circuit, the influence of the driving current on the gate inductance on V _gs can be ignored, and V _gs can be simplified into the following expression:

the unbalanced current of the parallel lower MOSFET chip 42 obtainable by the above formula can be expressed by the following expression:

Wherein Δi _d12 is the dynamic unbalance current of Q ₁ and Q ₂, Δi _d13 is the dynamic unbalance current of Q ₁ and Q ₃, Δi _d14 is the dynamic unbalance current of Q ₁ and Q ₄, Δi _d23 is the dynamic unbalance current of Q ₂ and Q ₃, Δi _d34 is the dynamic unbalance current of Q ₃ and Q ₄, and g _fs is the transconductance.

It can be seen from the above that the unbalanced current of the parallel lower MOSFET chip 42 is mainly caused by the stray inductance L _b between the power source side branches of the lower MOSFET chip 42, but only the current of one chip flows through the stray inductance L _b between the power source side branches, and the current of other chips is not coupled, so that the influence of the current coupling effect on the parallel current sharing can be eliminated through the design.

In the above formula, dt is a derivative of time.

The MOSFET is an abbreviation of "Metal-Oxide-Semiconductor Field-Effect Transistor", and Chinese means "Metal-Oxide-semiconductor field effect transistor". It is a common semiconductor device that is widely used in electronic circuits, particularly in analog and digital circuit designs.

In the present embodiment, the upper MOSFET chip 11 and the lower MOSFET chip 42 are both silicon carbide MOSFETs, the upper diode chip 13 and the lower diode chip 44 are both SiC SBDs, and the upper series diode 10 and the lower series diode 32 are both schottky diodes.

Note that SiC SBD is an abbreviation of "Silicon Carbide Schottky Barrier Diodes", and chinese means a silicon carbide schottky barrier diode.

As shown in fig. 3, the upper half-bridge unit 7 further includes an upper drain power terminal 16, the upper drain power terminal 16 is connected with the second upper drain conductive layer 18 by sintering, the lower half-bridge unit 6 further includes a first lower output power terminal 28, a second lower output power terminal 47, and a lower power source power terminal 48, the lower power source power terminal 48 is connected with the lower power source conductive layer 49 by sintering, and the first lower output power terminal 28 and the second lower output power terminal 47 are connected with the second lower drain conductive layer 45 by sintering, respectively, so that connection of the power module with other components is facilitated by using the power terminals.

In this embodiment, the upper drain power terminal 16, the first lower output power terminal 28, the second lower output power terminal 47, and the lower power source power terminal 48 are all low-threaded power terminals, so that parasitic inductance of the power terminals can be effectively reduced, and voltage overshoot of switching transients of the power module can be reduced.

The low-thread power terminal is a copper column terminal with lower height, and threads are arranged above the copper column terminal and connected with the capacitor busbar.

It should be noted that the low-thread power terminal means a power terminal having a height dimension of between 14mm and 16 mm. In particular, the height dimension of the low thread power terminal may be 14mm, 15mm, 16mm, and any other value between 14mm and 16 mm.

In this embodiment, the height dimension of the low thread power terminal is 15.6mm.

In the related art, the height of the same type of power terminal is 40mm.

It should be noted that the power sub-module is connected to a capacitor busbar, the capacitor busbar has dc+, DC-and AC terminals thereon, the upper drain power terminal 16 is connected to dc+, the first lower output power terminal 28 and the second lower output power terminal 47 are simultaneously connected to AC, and the lower power source power terminal 48 is connected to DC-.

As shown in fig. 3, two upper power source conductive layers 15 are disposed on the upper substrate 21, and the two upper power source conductive layers 15 are disposed on both sides of the upper drain power terminal 16, respectively. With the above structure, the two upper power source conductive layers 15 are respectively disposed at two sides of the upper drain power terminal 16, so that the layout of the upper half-bridge unit 7 is more compact, and more components can be conveniently placed under the same area.

As shown in fig. 4, the second lower drain conductive layer 45 includes a first section 451, a second section 452, and a third section 453, the first section 451 and the third section 453 are connected to both ends of the second section 452, respectively, the first section 451 and the third section 453 are located on the same side of the second section 452, the plurality of lower diode chips 44 are disposed on the second section 452 at intervals along an extending direction of the second section 452, the second lower output power terminal 47 is disposed on the first section 451, the first lower output power terminal 28 is disposed on the third section 453, the first section 451 is connected to one of the upper power source conductive layers 15, and the third section 453 is connected to the other upper power source conductive layer 15. With the above structure, the plurality of lower diode chips 44 are conveniently placed by the second section 452, the second lower output power terminal 47 is conveniently placed by the first section 451, and the first lower output power terminal 28 is conveniently placed by the third section 453, so that the layout of the lower half-bridge unit 6 is more compact, and more components can be conveniently placed under the same area.

As shown in fig. 3, the second upper drain conductive layer 18 includes a fourth segment 181 and a fifth segment 182 perpendicular to each other, one end of the fifth segment 182 is connected to the middle of the fourth segment 181, a plurality of upper diode chips 13 are disposed on the fourth segment 181 at intervals along the length direction of the fourth segment 181, and the upper drain power terminal 16 is disposed on the fifth segment 182. With the above structure, the fourth section 181 is used to place a plurality of upper diode chips 13, the upper drain power terminal 16 is disposed on the fifth section 182, and the two upper power source conductive layers 15 are disposed on both sides of the upper drain power terminal 16, so that the layout compactness of the upper half-bridge unit 7 can be further improved.

In this embodiment, the second upper drain conductive layer 18 includes a fourth segment 181 and a fifth segment 182 perpendicular to each other to form a T-shaped structure, and the second lower drain conductive layer 45 includes a first segment 451, a second segment 452, and a third segment 453 to form a concave structure. In particular, the convex portion of the T-shaped structure corresponds to the concave position of the concave structure.

As shown in fig. 2, in the present embodiment, the first section 451 is connected to one of the upper power source conductive layers 15 through the first arm connection bonding wire 53, and the third section 453 is connected to the other upper power source conductive layer 15 through the second arm connection bonding wire 54. The connection between the second lower drain electrode conductive layer 45 and the upper power source electrode conductive layer 15 is realized by using the first bridge arm connection bonding wire 53 and the second bridge arm connection bonding wire 54, and the connection structure is simple and the cost is low.

As shown in fig. 3 and 4, the gate of the upper MOSFET chip 11 is connected to the first upper gate conductive layer 50 of the upper substrate 21, the driving source of the upper MOSFET chip 11 is connected to the upper driving source conductive layer 23 of the upper substrate 21, the upper half-bridge unit 7 further includes an upper driving resistor 20, a first upper gate signal terminal 24, a first upper driving source signal terminal 25, a second upper driving source signal terminal 26, and a second upper gate signal terminal 27, the first upper gate conductive layer 50 is connected to the upper driving resistor 20, the upper driving resistor 20 is connected to the second upper gate conductive layer 22 of the upper substrate 21, the first upper gate signal terminal 24 and the second upper gate signal terminal 27 are respectively connected to the second upper gate conductive layer 22, and the first upper driving source signal terminal 25 and the second upper driving source signal terminal 26 are respectively connected to the upper driving source conductive layer 23. The gate of the lower MOSFET chip 42 is connected to the first lower gate conductive layer 51 of the lower substrate 46, the driving source of the lower MOSFET chip 42 is connected to the lower driving source conductive layer 34 of the lower substrate 46, the lower half-bridge unit 6 further includes a lower driving resistor 41, a first lower driving source signal terminal 35, a first lower gate signal terminal 36, a second lower driving source signal terminal 37, and a second lower gate signal terminal 38, the first lower gate conductive layer 51 is connected to the lower driving resistor 41, the lower driving resistor 41 is connected to the second lower gate conductive layer 33 of the lower substrate 46, the first lower gate signal terminal 36 and the second lower gate signal terminal 38 are connected to the second lower gate conductive layer 33, and the first lower driving source signal terminal 35 and the second lower driving source signal terminal 37 are connected to the lower driving source conductive layer 34, respectively. The terminal is convenient for realizing connection of the power module and other components.

As shown in fig. 3, the first upper drain conductive layer 19 is located at a side of the second upper drain conductive layer 18 away from the upper power source conductive layer 15, the plurality of upper MOSFET chips 11 are arranged at intervals along the length direction of the first upper drain conductive layer 19, the upper half-bridge unit 7 includes a plurality of upper driving resistors 20, a plurality of first upper gate conductive layers 50 are disposed on the upper substrate 21 in a one-to-one correspondence with the plurality of upper MOSFET chips 11, the plurality of upper driving resistors 20 are disposed in a one-to-one correspondence with the plurality of first upper gate conductive layers 50, the plurality of first upper gate conductive layers 50 are all located at a side of the first upper drain conductive layer 19 away from the second upper drain conductive layer 18, the second upper gate conductive layer 22 is located at a side of the first upper gate conductive layer 50 away from the first upper drain conductive layer 19, and the upper driving source conductive layer 23 is located at a side of the second upper gate conductive layer 22 away from the first upper gate conductive layer 50. By adopting the structure, the upper surface of the upper substrate 21 can be fully utilized, the arrangement of each conductive layer on the upper substrate 21 is compact, and the layout of the upper half-bridge unit 7 is reasonable.

Specifically, the interval between the second upper drain conductive layer 18 and the first upper drain conductive layer 19 is a first interval, the interval between the second upper drain conductive layer 18 and the upper power source conductive layer 15 is a second interval, and the first interval is smaller than the second interval.

As shown in fig. 4, the first lower drain conductive layer 43 is located on a side of the second lower drain conductive layer 45 away from the lower power source conductive layer 49, the lower half-bridge unit 6 includes a plurality of lower driving resistors 41, a plurality of first lower gate conductive layers 51 are disposed on the lower substrate 46, the plurality of first lower gate conductive layers 51 are disposed in one-to-one correspondence with the plurality of lower MOSFET chips 42, the plurality of lower driving resistors 41 are disposed in one-to-one correspondence with the plurality of first lower gate conductive layers 51, the plurality of first lower gate conductive layers 51 are located on a side of the first lower drain conductive layer 43 away from the second lower drain conductive layer 45, the second lower gate conductive layer 33 is located on a side of the first lower gate conductive layer 51 away from the first lower drain conductive layer 43, and the lower driving source conductive layer 34 is located on a side of the second lower gate conductive layer 33 away from the first lower gate conductive layer 51. With the above structure, the upper surface of the lower substrate 46 can be fully utilized, the arrangement of each conductive layer on the lower substrate 46 is compact, and the layout of the lower half-bridge unit 6 is reasonable.

Specifically, the interval between the first lower drain conductive layer 43 and the second lower drain conductive layer 45 is a third interval, the interval between the second lower drain conductive layer 45 and the lower power source conductive layer 49 is a fourth interval, and the third interval is smaller than the fourth interval.

As shown in fig. 3 and 4, the first upper drain conductive layer 19, the second upper gate conductive layer 22 and the upper driving source conductive layer 23 are all elongated structures. The upper surface of the upper substrate 21 can be fully utilized in the length direction of the first upper drain conductive layer 19, the second upper gate conductive layer 22, and the upper driving source conductive layer 23. The first lower drain conductive layer 43, the second lower gate conductive layer 33 and the lower driving source conductive layer 34 are all of a long strip structure. The upper surface of the lower substrate 46 can be fully utilized in the longitudinal direction of the first lower drain conductive layer 43, the second lower gate conductive layer 33, and the lower driving source conductive layer 34.

When the upper half bridge unit 7 and the lower half bridge unit 6 are assembled together, the arrangement direction of the upper half bridge unit 7 and the lower half bridge unit 6 is a first direction, the extension directions of the first upper drain conductive layer 19, the second upper gate conductive layer 22, and the upper driving source conductive layer 23 are second directions, and the extension directions of the first lower drain conductive layer 43, the second lower gate conductive layer 33, and the lower driving source conductive layer 34 are also second directions, and the first direction and the second direction are perpendicular.

The extending direction (longitudinal direction) of the fourth segment 181 is also the second direction. The extending direction (length direction) of the second section 452 is also the second direction.

As shown in fig. 2 to 4, the drain electrode of the upper MOSFET chip 11 is sintered with the first upper drain conductive layer 19 by solder, the power source electrode of the upper MOSFET chip 11 is sintered with the anode electrode of the upper diode chip 13 by the first upper MOSFET power source bonding wire 12, the gate electrode of the upper MOSFET chip 11 is connected with the first upper gate conductive layer 50 by the upper MOSFET gate bonding wire 8, the driving source electrode of the upper MOSFET chip 11 is connected with the upper driving source conductive layer 23 by the upper MOSFET driving source bonding wire 9, the cathode electrode of the upper series diode 10 is sintered with the first upper drain conductive layer 19 by solder, the anode electrode of the upper series diode 10 is sintered with the second upper drain conductive layer 18 by the upper series diode anode bonding wire 17, the cathode electrode of the upper diode chip 13 is sintered with the second upper drain conductive layer 18 by solder, and the anode electrode of the upper diode chip 13 is sintered with the upper power source conductive layer 15 by the second upper MOSFET power source bonding wire 14. The drain electrode of the lower MOSFET die 42 is sinter-connected to the first lower drain conductive layer 43 by solder, the power source electrode of the lower MOSFET die 42 is sinter-connected to the anode electrode of the lower diode die 44 by the first lower MOSFET power source bond wire 30, the gate electrode of the lower MOSFET die 42 is connected to the first lower gate conductive layer 51 by the lower MOSFET gate bond wire 39, the drive source electrode of the lower MOSFET die 42 is sinter-connected to the lower drive source conductive layer 34 by the lower MOSFET drive source bond wire 40, the cathode electrode of the lower series diode 32 is sinter-connected to the first lower drain conductive layer 43 by solder, the anode electrode of the lower series diode 32 is sinter-connected to the second lower drain conductive layer 45 by the anode bond wire 31, the cathode electrode of the lower diode die 44 is sinter-connected to the second lower drain conductive layer 45 by solder, the anode electrode of the lower diode die 44 is sinter-connected to the lower power source conductive layer 49 by the second lower MOSFET power source bond wire 29, and the upper power source conductive layer 15 is sinter-connected to the second lower drain conductive layer 45.

Specifically, the upper MOSFET chip 11, the upper series diode 10 and the upper diode chip 13 are directly sintered on the conductive layer of the upper substrate 21, wherein the drain electrode of the upper MOSFET chip 11 is sintered and connected with the first upper drain conductive layer 19 by solder, the cathode of the upper series diode 10 is sintered and connected with the first upper drain conductive layer 19 by solder, and the cathode of the upper diode chip 13 is sintered and connected with the second upper drain conductive layer 18 by solder. The lower MOSFET die 42, the lower series diode 32, and the lower diode die 44 are sintered directly onto the lower substrate 46, with the drain of the lower MOSFET die 42 being sintered with the first lower drain conductive layer 43 by solder, the cathode of the lower series diode 32 being sintered with the first lower drain conductive layer 43 by solder, and the cathode of the lower diode die 44 being sintered with the second lower drain conductive layer 45 by solder.

The mode of sintering connection is adopted to realize the fixation of the MOSFET chip, the serial diode and the diode chip, so that the LED chip has the advantage of firm connection, and is convenient for conducting heat and dissipating heat by using the conductive layer. The MOSFET chip, the series diode and the diode chip are connected with other components in a bonding wire connection mode, and the connecting structure has the advantages of being simple in structure and low in cost.

In the present embodiment, the upper half-bridge unit 7 includes four upper MOSFET chips 11 connected in parallel, one upper series diode 10, and three upper diode chips 13 connected in parallel. The lower half-bridge unit 6 comprises four parallel lower MOSFET chips 42, one lower series diode 32 and three parallel lower diode chips 44. By adopting the arrangement mode, the current coupling effect is eliminated, and the specific principle is shown in the principle of the double-pulse test circuit of the lower half-bridge unit.

In order to facilitate understanding of the power sub-module provided in this embodiment, as explained below with reference to fig. 6, fig. 6 is a circuit topology of the power module, in which the upper drain power terminal 16 is electrically connected to the anode of the upper series diode 10, the cathode of the upper series diode 10 is electrically connected to the drain of the upper MOSFET chip 11, the power source of the upper MOSFET chip 11 is electrically connected to the anode of the upper diode chip 13 through the first upper MOSFET power source electrode bonding wire 12, the anode of the upper diode chip 13 is electrically connected to the first lower output power terminal 28 and the second lower output power terminal 47 through the second upper MOSFET power source electrode bonding wire 14, and the cathode of the upper diode chip 13 is simultaneously electrically connected to the upper drain power terminal 16 and the anode of the upper series diode 10. The anode of the lower series diode 32 is electrically connected to the first lower output power terminal 28 and the second lower output power terminal 47, the cathode of the lower series diode 32 is electrically connected to the drain of the lower MOSFET chip 42, the power source of the lower MOSFET chip 42 is electrically connected to the anode of the lower diode chip 44 through the first lower MOSFET power source bonding wire 30, the anode of the lower diode chip 44 is electrically connected to the lower power source power terminal 48 through the second lower MOSFET power source bonding wire 29, and the cathode of the lower diode chip 44 is electrically connected to the anode of the lower series diode 32, the first lower output power terminal 28, and the second lower output power terminal 47 at the same time.

Specifically, the upper substrate 21 and the lower substrate 46 are each ceramic substrates. Ceramic substrates, by virtue of their unique thermal, mechanical and electrical properties, help to improve the efficiency, stability and safety of power electronics systems.

The ceramic substrate has high thermal conductivity, large heat capacity and strong heat diffusion function, and can effectively conduct heat generated by a chip in the power module to the outside, so that a good heat dissipation effect is realized. The ceramic substrate has a strong electrical insulation capability, protects the user from the electrical system, and ensures electrical safety inside the module. The low thermal expansion coefficient of the ceramic substrate helps to mechanically remain stable, and is suitable for some applications with strict requirements.

Note that the conductive layer in this embodiment is copper-clad.

As shown in fig. 1, another embodiment of the present invention provides a power module, which includes a substrate 5 and a power sub-module, wherein the power sub-module is disposed on the substrate 5, and the power sub-module is the power sub-module provided above. Thus, the power module can also group a plurality of upper MOSFET chips 11 connected in parallel by using the upper series diode 10, and a plurality of lower MOSFET chips 42 connected in parallel by using the lower series diode 32, thereby eliminating the current coupling effect.

In this embodiment, the power module includes a plurality of power sub-modules. By arranging a plurality of power sub-modules, different power requirements can be met. Specifically, the plurality of power sub-modules includes a first sub-module 1, a second sub-module 2, a third sub-module 3, and a fourth sub-module 4.

In the present embodiment, a plurality of power sub-modules are arranged at intervals in the length direction of the substrate 5, and the upper half-bridge unit 7 and the lower half-bridge unit 6 of each power sub-module are arranged at intervals in the width direction of the substrate 5. Therefore, the area of the substrate 5 can be fully utilized, and the integration level of the power module is improved.

As shown in fig. 7, in this embodiment, the current flow directions of two adjacent power sub-modules are opposite, and the mutual inductance of two adjacent power sub-modules is negative, so that parasitic inductance can be reduced.

Specifically, the lower surface of the upper substrate 21 of the power sub-module is connected with the substrate 5 by solder sintering, and the lower surface of the lower substrate 46 of the power sub-module is connected with the substrate 5 by solder sintering, so as to realize the connection of the upper substrate 21 and the lower substrate 46 with the substrate 5, respectively. The substrate 5 can conduct heat and dissipate heat to the power sub-module.

In this embodiment, the power module is a silicon carbide power module.

It should be noted that, in the related art, there is no commercialized 6.5kV silicon carbide half bridge module yet. In addition, in order to improve the yield of chips, the area of an active area of the silicon carbide chip is smaller, so that the current level of a single chip is smaller, the current level of a commercial silicon carbide single chip with high voltage of 6.5kV is only 25A, in order to improve the current level of a silicon carbide device application, a plurality of chips are required to be connected in parallel, the parallel chips are influenced by device parameters and packaging parameters when connected in parallel, the problem of unbalanced current distribution exists among the parallel chips, and therefore the temperature distribution of the parallel chips is unbalanced, and under severe conditions, the chips with overlarge current distribution can generate thermal runaway, so that the reliability of the whole power module is seriously threatened.

In order to meet the requirements of the high-voltage high-current low-parasitic-inductance power module, the power module provided by the invention meets the requirements of high-voltage insulation packaging, reduces parasitic parameters and reduces the loss of the module. Four parallel units are adopted, so that the influence of the current coupling effect on the current distribution of parallel chips is eliminated, and the multi-chip parallel current sharing is realized. The power module is the first 6.5kV/250A high-voltage high-current power module, and fills the gap of the packaging design of the high-voltage high-current power module.

The device provided by the embodiment has the following beneficial effects:

(1) At present, no power module of 6.5kV/250A exists, and the power module provided by the embodiment is divided into an upper half bridge and a lower half bridge, wherein each half bridge adopts 16 silicon carbide MOSFET chips, the current level is 320A at 25 ℃ and 256A at 100 ℃. The power module is divided into four power sub-modules which are connected in parallel, and each power sub-module is composed of 8 silicon carbide MOSFET chips, 6 silicon carbide Schottky diodes and 2 diodes connected in series. The upper half-bridge unit and the lower half-bridge unit of the power sub-module are respectively connected in parallel by 4 silicon carbide MOSFETs, so that the current coupling effect is eliminated;

(2) By applying the low-thread power terminal, parasitic inductance of the power terminal can be effectively reduced, and voltage overshoot of switching transient state of the power module is reduced;

(3) The current flow direction between adjacent power sub-modules in the four parallel power sub-modules is opposite, and the mutual inductance is negative, so that parasitic inductance can be reduced.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.

The relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values. It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

In the description of the present invention, it should be understood that the azimuth or positional relationships indicated by the azimuth terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal", and "top, bottom", etc., are generally based on the azimuth or positional relationships shown in the drawings, and are merely for convenience of describing the present invention and simplifying the description, and these azimuth terms do not indicate and imply that the apparatus or elements referred to must have a specific azimuth or be constructed and operated in a specific azimuth, and thus should not be construed as limiting the scope of the present invention, and the azimuth terms "inside and outside" refer to inside and outside with respect to the outline of each component itself.

Spatially relative terms, such as "above," "upper" and "upper surface," "above" and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the process is carried out, the exemplary term "above" may be included. Upper and lower. Two orientations below. The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In addition, the terms "first", "second", etc. are used to define the components, and are only for convenience of distinguishing the corresponding components, and the terms have no special meaning unless otherwise stated, and therefore should not be construed as limiting the scope of the present invention.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (16)

1. A power sub-module, the power sub-module comprising:

An upper half-bridge unit (7) comprising an upper substrate (21), a plurality of upper MOSFET chips (11) connected in parallel, an upper series diode (10) and a plurality of upper diode chips (13) connected in parallel, wherein the number of the upper MOSFET chips (11) is even, and two upper MOSFET chips (11) are an upper MOSFET chip group, one upper series diode (10) is arranged between the two upper MOSFET chip groups, the drain electrode of the upper MOSFET chip (11) is connected with a first upper drain electrode conductive layer (19) of the upper substrate (21), the power source electrode of the upper MOSFET chip (11) is connected with the anode electrode of the upper diode chip (13), the cathode electrode of the upper series diode chip (10) is connected with a second upper drain electrode conductive layer (18) of the upper substrate (21), the cathode electrode of the upper diode chip (13) is connected with the second upper drain electrode conductive layer (18), and the power source electrode of the upper diode chip (13) is connected with the upper drain electrode conductive layer (15);

A lower half-bridge unit (6) comprising a lower substrate (46), a plurality of lower MOSFET chips (42) connected in parallel, a lower series diode (32) and a plurality of lower diode chips (44) connected in parallel, wherein the number of the lower MOSFET chips (42) is even, and the two lower MOSFET chips (42) are one lower MOSFET chip group, one lower series diode (32) is arranged between the two lower MOSFET chip groups, the drain electrode of the lower MOSFET chip (42) is connected with a first lower drain electrode conductive layer (43) of the lower substrate (46), the power source electrode of the lower MOSFET chip (42) is connected with the anode electrode of the lower diode chip (44), the cathode electrode of the lower series diode chip (32) is connected with a second lower drain electrode conductive layer (45) of the lower substrate (46), the anode electrode of the lower diode chip (44) is connected with the second lower drain electrode conductive layer (45), and the power source electrode of the lower MOSFET chip (42) is connected with the second lower drain electrode conductive layer (45);

The upper half-bridge unit (7) further comprises an upper drain power terminal (16), the upper drain power terminal (16) being connected with the second upper drain conductive layer (18);

the lower half-bridge unit (6) further comprises a first lower output power terminal (28), a second lower output power terminal (47) and a lower power source power terminal (48), wherein the lower power source power terminal (48) is connected with the lower power source conducting layer (49), and the first lower output power terminal (28) and the second lower output power terminal (47) are respectively connected with the second lower drain conducting layer (45).

2. The power sub-module of claim 1, wherein the upper drain power terminal (16), the first lower output power terminal (28), the second lower output power terminal (47), and the lower power source power terminal (48) are all low-threaded power terminals.

3. The power sub-module of claim 1, wherein,

The upper substrate (21) is provided with two upper power source electrode conducting layers (15), and the two upper power source electrode conducting layers (15) are respectively arranged on two sides of the upper drain electrode power terminal (16);

The second lower drain conductive layer (45) comprises a first section (451), a second section (452) and a third section (453), the first section (451) and the third section (453) are respectively connected with two ends of the second section (452), the first section (451) and the third section (453) are positioned on the same side of the second section (452), a plurality of lower diode chips (44) are arranged on the second section (452) at intervals along the extending direction of the second section (452), the second lower output power terminal (47) is arranged on the first section (451), and the first lower output power terminal (28) is arranged on the third section (453);

the first section (451) is connected to one of the upper power source conductive layers (15), and the third section (453) is connected to the other upper power source conductive layer (15).

4. The power sub-module according to claim 1, wherein the second upper drain conductive layer (18) includes a fourth segment (181) and a fifth segment (182) perpendicular to each other, one end of the fifth segment (182) is connected to a middle portion of the fourth segment (181), a plurality of upper diode chips (13) are disposed on the fourth segment (181) at intervals along a length direction of the fourth segment (181), and the upper drain power terminal (16) is disposed on the fifth segment (182).

5. A power sub-module according to claim 3, characterized in that the first section (451) is connected to one of the upper power source conductive layers (15) by a first leg connection bond wire (53), and the third section (453) is connected to the other upper power source conductive layer (15) by a second leg connection bond wire (54).

6. The power sub-module according to any one of claims 1 to 5, wherein,

The grid of the upper MOSFET chip (11) is connected with a first upper grid conducting layer (50) of the upper substrate (21), a driving source electrode of the upper MOSFET chip (11) is connected with an upper driving source conducting layer (23) of the upper substrate (21), the upper half-bridge unit (7) further comprises an upper driving resistor (20), a first upper grid signal terminal (24), a first upper driving source signal terminal (25), a second upper driving source signal terminal (26) and a second upper grid signal terminal (27), the first upper grid conducting layer (50) is connected with the upper driving resistor (20), the upper driving resistor (20) is connected with a second upper grid conducting layer (22) of the upper substrate (21), the first upper grid signal terminal (24) and the second upper grid signal terminal (27) are respectively connected with the second upper grid conducting layer (22), and the first upper driving source signal terminal (25) and the second upper driving signal terminal (26) are respectively connected with the upper source conducting layer (23);

The grid of lower MOSFET chip (42) is connected with first gate conducting layer (51) of lower base plate (46), the drive source of lower MOSFET chip (42) with lower drive source conducting layer (34) of lower base plate (46) are connected, lower half-bridge unit (6) still includes lower drive resistance (41), first lower drive source signal terminal (35), first lower gate signal terminal (36), second lower drive source signal terminal (37) and second lower gate signal terminal (38), first gate conducting layer (51) with lower drive resistance (41) are connected, lower drive resistance (41) with second lower gate conducting layer (33) of lower base plate (46) are connected, first lower gate signal terminal (36) and second lower gate signal terminal (38) respectively with second lower gate conducting layer (33), first lower drive source signal terminal (35) and second lower drive source signal terminal (37) respectively with lower drive source conducting layer (34) are connected.

7. The power sub-module of claim 6, wherein,

The first upper drain electrode conducting layer (19) is located at one side of the second upper drain electrode conducting layer (18) far away from the upper power source electrode conducting layer (15), the plurality of upper MOSFET chips (11) are arranged at intervals along the length direction of the first upper drain electrode conducting layer (19), the upper half-bridge unit (7) comprises a plurality of upper driving resistors (20), a plurality of first upper gate electrode conducting layers (50) are arranged on the upper substrate (21), the plurality of first upper gate electrode conducting layers (50) are arranged in one-to-one correspondence with the plurality of upper MOSFET chips (11), the plurality of upper driving resistors (20) are arranged in one-to-one correspondence with the plurality of first upper gate electrode conducting layers (50), the plurality of first upper gate electrode conducting layers (50) are located at one side of the first upper drain electrode conducting layers (19) far away from the second upper drain electrode conducting layers (18), the second upper gate electrode conducting layers (22) are located at one side of the first upper gate electrode conducting layers (50) far away from the first upper drain electrode conducting layers (19), and the second upper gate electrode conducting layers (22) are located at one side of the first upper gate electrode conducting layers (23);

The first lower drain electrode conducting layer (43) is located on one side, far away from the lower power source electrode conducting layer (49), of the second lower drain electrode conducting layer (45), the lower half-bridge unit (6) comprises a plurality of lower driving resistors (41), a plurality of first lower gate electrode conducting layers (51) are arranged on the lower substrate (46), the first lower gate electrode conducting layers (51) and the lower MOSFET chips (42) are arranged in a one-to-one correspondence mode, the lower driving resistors (41) and the first lower gate electrode conducting layers (51) are arranged in a one-to-one correspondence mode, the first lower gate electrode conducting layers (51) are located on one side, far away from the second lower drain electrode conducting layers (45), of the first lower drain electrode conducting layers (43), the second lower gate electrode conducting layers (33) are located on one side, far away from the first lower drain electrode conducting layers (43), of the second lower gate electrode conducting layers (34) are located on one side, far away from the first lower gate electrode conducting layers (51), of the second lower gate electrode conducting layers (33).

8. The power sub-module of claim 6, wherein,

The first upper drain electrode conductive layer (19), the second upper gate electrode conductive layer (22) and the upper driving source electrode conductive layer (23) are all of strip structures;

the first lower drain electrode conductive layer (43), the second lower gate electrode conductive layer (33) and the lower driving source electrode conductive layer (34) are all of long strip structures.

9. The power sub-module of claim 6, wherein,

The drain electrode of the upper MOSFET chip (11) is sintered and connected with the first upper drain electrode conductive layer (19) through solder, the power source electrode of the upper MOSFET chip (11) is sintered and connected with the anode electrode of the upper diode chip (13) through a first upper MOSFET power source electrode bonding wire (12), the grid electrode of the upper MOSFET chip (11) is connected with the first upper grid electrode conductive layer (50) through an upper MOSFET grid electrode bonding wire (8), the driving source electrode of the upper MOSFET chip (11) is sintered and connected with the upper driving source electrode conductive layer (23) through an upper MOSFET driving source electrode bonding wire (9), the cathode electrode of the upper series diode (10) is sintered and connected with the first upper drain electrode conductive layer (19) through solder, the anode electrode of the upper series diode chip (10) is connected with the second upper drain electrode conductive layer (18) through an upper series diode anode electrode bonding wire (17), the cathode electrode of the upper diode chip (13) is sintered and connected with the second upper drain electrode conductive layer (18) through solder, and the cathode electrode of the upper series diode chip (13) is connected with the upper power source electrode conductive layer (15);

The drain electrode of the lower MOSFET chip (42) is connected with the first lower drain electrode conducting layer (43) in a sintering mode through welding flux, the power source electrode of the lower MOSFET chip (42) is connected with the anode electrode of the lower diode chip (44) through a first lower MOSFET power source electrode bonding wire (30), the grid electrode of the lower MOSFET chip (42) is connected with the first lower grid electrode conducting layer (51) through a lower MOSFET grid electrode bonding wire (39), the driving source electrode of the lower MOSFET chip (42) is connected with the lower driving source electrode conducting layer (34) through a lower MOSFET driving source electrode bonding wire (40), the cathode electrode of the lower series diode (32) is connected with the first lower drain electrode conducting layer (43) in a sintering mode through welding flux, the anode electrode of the lower series diode (32) is connected with the second lower drain electrode conducting layer (45) through a lower series diode (32) anode electrode bonding wire (31), the cathode electrode of the lower diode chip (44) is connected with the second lower drain electrode conducting layer (45) in a sintering mode through welding flux, and the cathode electrode of the lower diode chip (44) is connected with the second lower drain electrode conducting layer (29) through a lower power source electrode conducting layer (29).

10. The power sub-module according to any one of claims 1 to 5, wherein,

The upper half-bridge unit (7) comprises four upper MOSFET chips (11) connected in parallel, one upper series diode (10) and three upper diode chips (13) connected in parallel;

the lower half-bridge unit (6) comprises four parallel lower MOSFET chips (42), one lower series diode (32) and three parallel lower diode chips (44).

11. The power sub-module according to any of claims 1 to 5, characterized in that the upper substrate (21) and the lower substrate (46) are both ceramic substrates.

12. A power module, the power module comprising:

A substrate (5);

a power sub-module arranged on the substrate (5), the power sub-module being as claimed in any one of claims 1 to 11.

13. The power module of claim 12, wherein the power module comprises a plurality of the power sub-modules.

14. The power module according to claim 13, wherein a plurality of the power sub-modules are arranged at intervals in a length direction of the substrate (5), and an upper half-bridge unit (7) and a lower half-bridge unit (6) of each of the power sub-modules are arranged at intervals in a width direction of the substrate (5).

15. The power module of claim 14, wherein current flow is opposite between two adjacent power sub-modules.

16. The power module according to claim 12, characterized in that the lower surface of the upper substrate (21) of the power sub-module is connected to the substrate (5) by solder sintering, and the lower surface of the lower substrate (46) of the power sub-module is connected to the substrate (5) by solder sintering.