Disclosure of Invention
A switch arm of the above-mentioned type is therefore proposed, characterized in that the printed circuit board further comprises an inner layer, called inner loop layer, comprising a trace, called loop trace, having an opening for the heat dissipating via to pass through, the capacitor being connected to the other of the high-side switch and the low-side switch via the loop trace of the inner loop layer.
Thus, by making the loop connection using the inner layer of the printed circuit board, it is possible to locate the loop connection as close as possible to the top surface and thus obtain a very small loop surface area, thus obtaining a very low loop stray inductance, while maintaining cooling via the bottom surface of the printed circuit board.
The invention may further have one or more of the following optional features in any technically possible combination.
Optionally, the printed circuit board includes a series of a plurality of conductive inner layers starting from the top layer, the inner loop layer being a first layer of the inner layers starting from the top layer.
Still alternatively, the printed circuit board includes at least one inner layer, referred to as an inner multiplication layer, which, for at least one trace of the top layer, includes multiplication traces and multiplication vias connecting the associated trace of the top layer to the associated multiplication trace.
Still optionally, the heat dissipating vias comprise at least one of multiplication vias.
Still alternatively, the top layer of the printed circuit board includes a first trace and a second trace, the other of the high side switch and the low side switch is connected to the first trace, the capacitor is connected to the second trace, the printed circuit board includes a first via, referred to as a first loop via, connecting the first trace to the loop trace, and a second via, referred to as a second loop via, connecting the second trace to the loop trace, the loop trace including straight conductive portions extending from the first loop via to the second loop via.
Still alternatively, each straight conductive portion has a width of at least 200 μm.
Still alternatively, the openings through which the heat dissipating vias pass are distributed in parallel rows with one or more straight conductive portions defined between the parallel rows.
Still optionally, the switch arm further comprises a heat sink that presses against the bottom surface of the printed circuit board.
A switched mode power supply is also proposed, which comprises at least one switching arm according to the invention.
A mobile carrier is also proposed, comprising a switched mode power supply according to the invention.
Detailed Description
Referring to fig. 1, an example of an electrical device 100 embodying the present invention will now be described.
The electrical device 100 may be used, for example, for a mobile vehicle, such as a motor vehicle, an electric bicycle, an unmanned aerial vehicle, an electric scooter, or the like.
The electrical device 100 first comprises a DC voltage source 102, such as a battery, designed to supply a DC voltage U.
The electrical device 100 further comprises a switching arm 104 designed to receive the DC voltage U and to supply the DC voltage U and the zero voltage alternately. For example, the switch arm 104 is part of a switched mode power supply, such as an inverter, a DC-DC converter, an AC-DC converter, or the like.
More precisely, the switch arm 104 comprises a high-side switch HS and a low-side switch LS connected to each other at a midpoint M. Therefore, the high-side switch HS and the low-side switch LS each have a current input terminal D HS、DLS and a current output terminal S HS、SLS in view of the current flow as shown in fig. 1. With this arrangement, the current output terminal S HS of the high-side switch HS is connected to the current input terminal D HS of the low-side switch LS.
The high-side switch HS and the low-side switch LS each also have a control terminal G HS、GLS for example for defining the state thereof as on or off. Thus, the switch arm 104 is designed to alternately switch between a configuration in which the high-side switch HS is on and the low-side switch LS is off to provide the voltage U and a configuration in which the high-side switch HS is off and the low-side switch LS is on to provide the zero voltage.
The high-side switch HS and the low-side switch LS are each preferably controllable semiconductor switches, for example switches based on transistors such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or indeed Insulated Gate Bipolar Transistors (IGBTs) or even gallium nitride field effect transistors (GaN FETs).
In the case of the field effect transistor as shown in fig. 1, the current input terminal is referred to as "drain", the current output terminal is referred to as "source", and the control terminal is referred to as "gate".
The switch arm 104 further comprises an input capacitor C connected between the high side switch HS and the low side switch LS, more particularly between the current input terminal D HS of the high side switch HS and the current output terminal S LS of the low side switch LS. In practice, the capacitor C may comprise a plurality of capacitive components connected in parallel, for example.
The capacitor C is then connected to the DC voltage source 102, for example, to receive the DC voltage U.
The electrical device 100 further comprises an output component 106 connected between the midpoint M and the current output terminal S LS of the low-side switch LS. The output component 106 is, for example, the phase of the motor. In general, the output component 106 may be an inductive load that behaves essentially like a current source.
The switch arm 104 will now be described in more detail with reference to fig. 2.
In the example shown, the current input terminal D HS、DLS and the current output terminal S HS、SLS are each formed by a single contact surface, which may be referred to as a "contact pad", "bond pad" or simply "pad". Furthermore, the high-side switch HS and the low-side switch LS are each designed to be cooled, for example, by the contact surface of their current input terminals D HS、DLS. Therefore, the contact surface is generally larger, and at least larger than the contact surface of the current output terminal S HS、SLS. In other embodiments, the high-side switch HS and/or the low-side switch LS may be designed to be cooled by the contact surface of its current output terminal S HS、SLS.
The switch arm 104 includes a printed circuit board 202 (PCB) that is multi-layered, i.e., includes a series of multiple conductive layers throughout its thickness. These layers are planar, for example. The printed circuit board 202 thus comprises a top layer SUP with a top outer face 204. The printed circuit board 202 further includes a bottom layer INF having a bottom outer face 206, and at least one inner layer (two in the example shown, denoted by reference numerals INT1, INT2, respectively). The layers SUP, INT1, INT2, INF are separated from each other by an electrically insulating material, e.g. a resin such as a prepreg, represented by the dot filled areas in fig. 2.
As will be described in more detail below, each layer SUP, INT1, INT2, INF may be divided into a plurality of electrically conductive traces separated from each other by an electrically insulating material. In fig. 2, the trace at zero potential (at electrical ground) is represented by the area filled with horizontal lines. The trace at the potential of the DC voltage U is represented by the area filled with diagonal lines sloping upward from left to right. The trace at the potential at midpoint M is represented by the area filled with diagonal lines sloping downward from left to right.
The low side switch LS, the high side switch HS and the capacitor C are carried by the top outer face 204, preferably aligned in the direction X, for example, in this order.
These three components are connected by the top layer SUP. Thus, the top layer includes a trace called top trace H SUP, which connects the capacitor C and the high-side switch HS to each other. More precisely, the first terminal C 1 of the capacitor C and the current input terminal D HS of the high-side switch HS (in particular the contact surface thereof) are pressed against this top trace H SUP of the top layer SUP. The top layer SUP further comprises a trace called middle trace M SUP, which connects the high-side switch HS and the low-side switch LS to each other. More precisely, the current output terminal S HS of the high-side switch HS (in particular the contact surface thereof) and the current input terminal D LS of the low-side switch LS (in particular the contact surface thereof) are pressed against this intermediate trace M SUP of the top layer SUP.
The top layer SUP further comprises a first track called first ground track G1 SUP against which the current output terminal S LS of the low-side switch LS, in particular its contact surface, is pressed and a second track called second ground track G2 SUP against which the second terminal C 2 of the capacitor C is pressed.
In order to connect the current output terminal S LS of the low-side switch LS and the second terminal C 2 of the capacitor C to each other, an inner layer INT1, hereinafter referred to as an inner loop layer, is used. In the example shown, the inner component forms a single trace referred to as loop trace G INT1. To this end, the printed circuit board 202 includes at least one first via, referred to as a first loop via V G1, connecting the first ground trace G1 SUP to the loop trace G INT1, and at least one second via, referred to as a second loop via V G2, connecting the second ground trace G2 SUP to the loop trace G INT1.
Furthermore, the printed circuit board 202 may further comprise at least one inner multiplication layer in order to at least partially multiply the top layer SUP to allow for a larger current transfer. In fig. 2, the inner multiplication layer is the inner layer INT2. In other embodiments, multiple inner multiplication layers (such as inner multiplication layer INT 2) may be disposed below inner loop layer INT 1.
For each of one or more of the traces G1 SUP、MSUP、HSUP、G2SUP of the top layer SUP, the inner loop layer INT2 includes a corresponding trace G1 INT2、MINT2、HINT2、G2INT2, and a via V G1、VM、VH、VG2, referred to as a multiplication via, that connects the associated trace G1 SUP、MSUP、HSUP、G2SUP of the top layer SUP to the corresponding trace G1 INT2、MINT2、HINT2、G2INT2 of the inner loop layer INT 2.
To enable the multiplication via V H、VM to reach the inner multiplication layer INT2, the loop trace G INT1 of the inner loop layer INT1 has an opening 208 for the multiplication via V H、VM to pass through.
To dissipate the heat generated by the high side switch HS and the low side switch LS, the multiplication via V H、VM extends to the bottom surface 206. Thus, these multiplication vias V H、VM act as heat dissipating vias and transfer heat to the bottom surface 206, particularly the portion of the bottom surface that is below the current input terminal D HS、DLS in the example shown, because that portion of the bottom surface constitutes the main heat exchanging surface of the high-side switch HS and the low-side switch LS. In addition, the switch arm 104 includes a heat sink 210 that is pressed against the bottom surface 206 of the printed circuit board 202, for example, by an electrically insulating but thermally conductive interface 212 (such as thermal paste). The heat sink 210 is thus designed to dissipate heat reaching the bottom surface 206. For example, the heat sink is a heat sink with a heat transfer fluid (such as water), or more simply a heat sink with fins.
As shown, the multiplied trace M INT2 of the intermediate trace M SUP is positioned facing and near the heat sink 210. Thus, there may be stray capacitance between them. However, the multiplication trace M INT2 is at the potential of the midpoint, which is switched at high frequency. Thus, such high frequency switching may cause stray currents to occur due to capacitive coupling with the heat sink 210. To avoid such stray currents between the one or more inner multiplication layers INT2 and the heat sink 210, the bottom layer INF preferably includes a screening trace G INF (also referred to as a screening trace) that is at a substantially constant potential (e.g., connected to electrical ground so as to be at zero potential). This is accomplished, for example, by extending the via V G1、VG2 to the screening trace G INF of the underlying INF. Alternatively, the screening trace G INF may be at a positive potential by being connected to the top trace H SUP, for example, through the via V H.
To enable the heat dissipating vias V H、VM to reach the bottom surface 206, the screening trace G INF has an opening 214 through which the heat dissipating vias V H、VM pass. Thus, opening 208 and opening 214 are positioned facing each other.
Referring to fig. 3, 4 and 5, the openings 208 through which the heat dissipating vias V M、VH pass are distributed in parallel rows. In particular, these rows extend in the alignment direction X of the switches HS, LS and the capacitor C. The rows are spaced far enough apart to define one or more straight conductive portions 402 in the loop trace G INT1 therebetween, the straight conductive portions 402 extending from the first loop via V G1 to the second loop via V G2. Since the conductive portions 402 are straight, they connect the loop via V G1、VG2 in as short a path as possible, which helps to reduce stray inductance. Each straight conductive portion 402 has a lateral dimension (width) of, for example, at least 200 μm, especially when the inner loop layer INT1 has a thickness of at least 35 μm.
Referring to fig. 6, another example of a switch arm 600 according to the present invention will now be described. The switch arm 600 may be used, for example, in the electrical device 100 of fig. 1 in place of the switch arm 104.
The switch arm 600 is similar to the switch arm 104 of fig. 2, except for the following differences.
In the switch arm 600, the capacitor C, the low-side switch LS, and the high-side switch HS are aligned in the direction X in this order in this example.
In addition, in this example, the top layer SUP has two traces H1 SUP、H2SUP against which the drain D HS of the high-side switch HS and the terminal C 1 of the capacitor C are pressed, respectively. Similarly, the multiplication layer INT2 includes two corresponding traces H1 INT2、H2INT2.
The loop trace H INT1 connects the two traces H1 SUP、H2SUP. The loop trace is connected to both traces through loop vias V H1 and V H2, respectively.
The opening 208 in the loop trace H INT1 allows the ground via V G and the midpoint via V M to pass through.
In addition, the screening trace G INF is connected to the ground trace through the via V G. The screening trace G INF is then provided with openings for other vias, in particular via V M、VH1, to allow heat to dissipate from the switches HS, LS to the heat sink 210.
Referring to fig. 7, the openings 208 are distributed in parallel rows. In particular, these rows extend in the alignment direction X of the capacitor C and the switches HS, LS. The rows are spaced far enough apart to define one or more straight conductive portions 402 in loop trace H INT1 therebetween, the straight conductive portions 402 extending from the first loop via V H1 to the second loop via V H2. Since the conductive portions 402 are straight, they connect the loop via V H1、VH2 in as short a path as possible, which helps to reduce stray inductance. Each straight conductive portion 402 has a lateral dimension (width) of, for example, at least 200 μm, especially when the inner loop layer INT1 has a thickness of at least 35 μm.
In summary, it is apparent that switch arms such as those described above allow for reduced loop stray inductance while maintaining cooling through the bottom surface of the printed circuit board.
It should also be noted that the present invention is not limited to the above-described embodiments. In particular, it will be apparent to those skilled in the art that various modifications can be made to the embodiments described above in light of the teachings just disclosed to them.
In the detailed presentation of the invention given above, the terms used should not be construed as limiting the invention to the embodiments disclosed in the present specification, but should be construed to include all equivalents which can be envisioned by those skilled in the art by applying their general knowledge to practice the teachings just disclosed.