CN118677424A

CN118677424A - Gate drive circuit and electronic equipment

Info

Publication number: CN118677424A
Application number: CN202410896547.8A
Authority: CN
Inventors: 张兵
Original assignee: Beijing Huacheng Electronics Co ltd
Current assignee: Beijing Huacheng Electronics Co ltd
Priority date: 2024-07-04
Filing date: 2024-07-04
Publication date: 2024-09-20
Also published as: WO2026007989A1

Abstract

The present application provides a gate drive circuit and an electronic device, which are applied to the technical field of semiconductor process equipment. The circuit is used to drive a target switch tube to be turned on or off. The circuit includes a first switch circuit, a second switch circuit and a charging circuit. The first input end of the first switch circuit receives a power supply signal, and the output end is connected to the input end of the charging circuit. The first input end of the second switch circuit is grounded, and the output end is connected to the input end of the charging circuit. The output end of the charging circuit is connected to the gate of the target switch tube. The first switch circuit and the second switch circuit are alternately turned on. The charging circuit is configured as follows: when the first switch circuit is turned on, the gate-source capacitor is positively charged to drive the target switch tube to be turned on, and when the second switch circuit is turned on, the gate-source capacitor is reversely charged to drive the target switch tube to be turned off. Therefore, the circuit only needs one power supply to control the conduction state of the target switch tube, which can effectively reduce the overall cost of the circuit.

Description

Gate drive circuit and electronic equipment

Technical Field

The application relates to the technical field of semiconductor process equipment, in particular to a gate driving circuit and electronic equipment.

Background

Wide band gap semiconductor devices typified by SiC (silicon carbide) and GaN (gallium nitride) are widely used in high frequency power electronic converters in recent years. As with other types of semiconductor devices, the wide bandgap semiconductor device is also affected by its own parasitic parameters, such as parasitic capacitance between source and gate or parasitic capacitance between drain and gate, which have insignificant effects in low frequency application scenarios, and in high frequency application scenarios, voltages affecting the on state of the wide bandgap semiconductor device may be generated, and even the normal operation of the system may be damaged due to misleading of the device.

In order to solve the above-mentioned problems, the prior art generally adopts a driving circuit capable of providing negative pressure to control the wide bandgap semiconductor device to be reliably turned off, so that although the reliability of the driving process of the wide bandgap semiconductor device can be improved, the driving circuit in the prior art needs to be connected to a positive voltage power supply and a negative voltage power supply respectively to realize the control process of turning on and off the wide bandgap semiconductor device, which obviously increases the overall cost of the driving circuit and the system to which the driving circuit belongs.

Disclosure of Invention

In view of the above, the present application is directed to providing a gate driving circuit and an electronic apparatus, which utilize a power source to drive on and off of a wide bandgap semiconductor device, and reduce the overall cost of the gate driving circuit and the system to which the gate driving circuit belongs.

In a first aspect, the present application provides a gate driving circuit for driving a target switching tube to be turned on or off, the gate driving circuit comprising: a first switch circuit, a second switch circuit and a charging circuit, wherein,

The first input end of the first switch circuit is used for receiving a power supply signal, the second input end of the first switch circuit is used for receiving a driving signal, and the output end of the first switch circuit is connected with the input end of the charging circuit;

The first input end of the second switching circuit is used for being grounded, the second input end of the second switching circuit is used for receiving the driving signal, and the output end of the second switching circuit is connected with the input end of the charging circuit;

the output end of the charging circuit is connected with the grid electrode of the target switching tube, and the source electrode of the target switching tube is grounded;

The first switch circuit and the second switch circuit are used for being alternately conducted in response to the driving signal;

The charging circuit is configured to: the gate-source capacitance of the target switching tube is positively charged when the first switching circuit is turned on to drive the target switching tube to be turned on, and the gate-source capacitance of the target transistor is reversely charged when the second switching circuit is turned on to drive the target switching tube to be turned off.

In an alternative embodiment, the charging circuit includes: an energy storage regulating sub-circuit, a first unidirectional conduction sub-circuit and a second unidirectional conduction sub-circuit, wherein,

The input end of the first unidirectional conduction sub-circuit is connected with the output end of the first switch circuit;

the output end of the second unidirectional conduction sub-circuit is connected with the output end of the second switch circuit;

The first end of the energy storage regulating sub-circuit is respectively connected with the output end of the first unidirectional conduction sub-circuit and the input end of the second unidirectional conduction sub-circuit;

the second end of the energy storage regulation sub-circuit is used as the output end of the charging circuit;

the conducting direction of the first unidirectional conduction sub-circuit is the same as the voltage drop direction of forward charging, and the conducting direction of the second unidirectional conduction sub-circuit is the same as the voltage drop direction of reverse charging.

In an alternative embodiment, the tank conditioning sub-circuit includes a first resistor and a first inductor, wherein,

One end of the first resistor is used as a first end of the energy storage regulation subcircuit, and the other end of the first resistor is connected with one end of the first inductor;

the other end of the first inductor is used as a second end of the energy storage regulating sub-circuit.

In an alternative embodiment, the tank regulator sub-circuit includes a second resistor, a third resistor, and a second inductor, wherein,

One end of the second resistor is connected with the output end of the first unidirectional conduction sub-circuit;

One end of the third resistor is connected with the input end of the second unidirectional conduction sub-circuit;

One end of the second inductor is connected with the second resistor and the other end of the third resistor respectively, and the other end of the second inductor is used as the second end of the energy storage regulator circuit.

In an alternative embodiment, the first unidirectional-conduction sub-circuit comprises a first diode and the second unidirectional-conduction sub-circuit comprises a second diode.

In an alternative embodiment, the gate driving circuit provided in the first application further includes: a bleeder circuit, wherein,

One end of the bleeder circuit is connected with the output end of the charging circuit, and the other end of the bleeder circuit is grounded;

the bleeder circuit is used for releasing the electric energy of the gate source capacitor under the condition that the gate driving circuit is powered down.

In an alternative embodiment, the gate driving circuit provided in the first application further includes: a compensation circuit, wherein,

One end of the compensation circuit is connected with the output end of the charging circuit, and the other end of the compensation circuit is grounded;

The compensation circuit is used for adjusting the capacitance value between the source electrode and the grid electrode of the target switching tube.

In an alternative embodiment, the gate driving circuit provided in the first application further includes: the protection circuit comprises a first voltage stabilizing tube and a second voltage stabilizing tube, wherein,

The cathode of the first voltage stabilizing tube is connected with the output end of the charging circuit, and the anode of the first voltage stabilizing tube is connected with the anode of the second voltage stabilizing tube;

and the cathode of the second voltage stabilizing tube is grounded.

In an alternative embodiment, the first switching circuit comprises a first controllable switch and a first driving sub-circuit, wherein,

A first end of the first controllable switch is used as a first input end of the first switch circuit, and a second end of the first controllable switch is used as an output end of the first switch circuit;

the output end of the first driving sub-circuit is connected with the control end of the first controllable switch, and the input end of the first driving sub-circuit is used for receiving the driving signal;

The first driving sub-circuit is used for configuring the on-time delay and the off-time delay of the first controllable switch.

In an alternative embodiment, the first driving sub-circuit comprises: a first buffer, a second buffer, and a first delay circuit, the first delay circuit comprising: a third diode, a first capacitor and a fourth resistor, wherein,

The input end of the first buffer is used as the input end of the first driving sub-circuit;

The cathode of the third diode is connected with the output end of the first buffer, and the anode of the third diode is connected with the input end of the second buffer;

the fourth resistor is connected with the third diode in parallel;

One end of the first capacitor is connected with the anode of the third diode, and the other end of the first capacitor is grounded;

the output of the second buffer serves as the output of the first drive sub-circuit.

In an alternative embodiment, the second switching circuit comprises a second controllable switch and a second driving sub-circuit, wherein,

The first end of the second controllable switch is used as a first input end of the second switch circuit, and the second end of the second controllable switch is used as an output end of the second switch circuit;

The output end of the second driving sub-circuit is connected with the control end of the second controllable switch, and the input end of the second driving sub-circuit is used for receiving the driving signal;

The second driving sub-circuit is used for configuring the on-time delay and the off-time delay of the second controllable switch.

In an alternative embodiment, the second driving sub-circuit comprises: an inverter, a third buffer, and a second delay circuit, the second delay circuit comprising: a fourth diode, a second capacitor and a fifth resistor, wherein,

The input end of the inverter is used as the input end of the second driving sub-circuit;

The cathode of the fourth diode is connected with the output end of the inverter, and the anode of the fourth diode is connected with the input end of the third buffer;

The fifth resistor is connected with the fourth diode in parallel;

one end of the second capacitor is connected with the anode of the fourth diode, and the other end of the second capacitor is grounded;

the output of the third buffer is used as the output of the second driving sub-circuit.

In a second aspect, the present application provides an electronic device comprising: a power supply module, a signal output module, a target switching tube and a gate driving circuit according to any one of the first aspect of the present application, wherein,

The power supply module is connected with a first input end of a first switch circuit in the grid driving circuit and is used for providing a power supply signal for the first switch circuit;

The signal output module is respectively connected with second input ends of a first switch circuit and a second switch circuit in the grid driving circuit and is used for outputting driving signals to the first switch circuit and the second switch circuit;

The grid driving circuit is connected with the grid of the target switching tube and is used for responding to the driving signal to drive the target switching tube to be turned on or turned off.

Based on the above, the gate driving circuit provided by the application is applied to the target switching tube with the gate-source capacitance between the gate and the source, the gate driving circuit comprises a first switching circuit, a second switching circuit and a charging circuit, the first input end of the first switching circuit receives a power supply signal, the first input end of the second switching circuit is grounded, the input end of the charging circuit is respectively connected with the output ends of the first switching circuit and the second switching circuit, the output ends are connected with the gate of the target switching tube, in practical application, the first switching circuit and the second switching circuit are alternately turned on in response to the driving signal, namely, only one switching circuit is turned on at the same moment, when the first switching circuit is turned on, the charging circuit positively charges the gate-source capacitance of the target switching tube, and applies forward voltage between the gate and the source of the target switching tube, and correspondingly, when the second switching circuit is turned on, the source of the target switching tube and the first input end of the second switching circuit are grounded, a closed charging loop can be formed, and the charging circuit can be turned off to the gate of the target switching tube, and the current driving circuit can be turned off, and the current can be controlled by the gate to be turned off.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a wide bandgap switching tube in the prior art.

Fig. 2 is a circuit topology diagram of a gate driving circuit according to the present application.

Fig. 3 is a circuit topology diagram of another gate driving circuit provided by the present application.

Fig. 4 is a schematic diagram of a forward charging path of the gate driving circuit according to the present application.

Fig. 5 is a schematic diagram of a correspondence between a first resistance value and a gate-source capacitance forward voltage in the energy storage regulator sub-circuit.

Fig. 6 is a schematic diagram of a reverse charging path of the gate driving circuit according to the present application.

Fig. 7 is a schematic diagram of a correspondence between a first resistance value and a gate-source capacitance reverse voltage in the energy storage regulator sub-circuit.

Fig. 8 is a circuit topology of still another gate driving circuit provided by the present application.

Fig. 9 is a circuit topology of a gate driving circuit according to still another embodiment of the present application.

Fig. 10 is a schematic diagram showing the phase relationship between the driving signal and the control signal of the first controllable switch and the control signal of the second controllable switch according to the present application.

FIG. 11 is a schematic diagram showing the phase relationship between the gate-source capacitance voltage and the control signals of the first controllable switch and the second controllable switch according to the present application.

Fig. 12 is a circuit topology diagram of a radio frequency power supply provided by the application.

Fig. 13 is a schematic diagram of an isolation circuit between a signal output module and a gate driving circuit in a rf power supply according to the present application.

Fig. 14 is a schematic diagram of another isolation circuit between a signal output module and a gate driving circuit in a rf power supply according to the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

With the continuous development of power electronics technology, wide bandgap semiconductor devices represented by third generation semiconductor materials such as SiC (silicon carbide) and GaN (gallium nitride) have significant advantages in terms of critical parameters such as bandgap width, breakdown electric field, thermal conductivity, and electron saturation rate, and can meet the application requirements of modern industry on high power, high voltage, and high frequency, and are widely applied to high-frequency power electronic converters in recent years.

As with other types of semiconductor devices, the wide bandgap semiconductor device is also affected by its own parasitic parameters, and as shown in fig. 1, taking a controllable switching transistor SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-Oxide semiconductor field effect transistor) as an example, the parasitic parameters of the controllable switching transistor mainly include: the parasitic capacitance Cgs (gate-source capacitance) between the source S and the gate G, the parasitic capacitance Cgd (gate-drain capacitance) between the drain D and the gate G, and the parasitic capacitance Cds between the drain D and the source S may, of course, have other parasitic parameters, and in practical applications, the actual situation of the semiconductor device is not described in detail here.

It should be noted that, these parasitic parameters that are not significantly affected in the low-frequency application scenario may generate voltage that affects the on state of the wide bandgap semiconductor device in the high-frequency application scenario, and may even damage the normal operation of the system due to misleading of the device. Still taking SiC MOSFETs as an example, the threshold voltage and the sustainable reverse voltage of the SiC MOSFETs are small and are greatly affected by temperature, and if the voltage spike is too large in practical application, the SiC MOSFETs may be turned on by mistake, thereby damaging the switching tube and the circuit system to which the switching tube belongs.

In order to prevent the erroneous conduction of the wide bandgap semiconductor device, a driving circuit capable of providing negative pressure is generally adopted in the prior art to control the reliable turn-off of the wide bandgap semiconductor device, so as to ensure that the spike voltage cannot cause the erroneous conduction of the semiconductor device. The inventor researches and discovers that although the reliability of the driving process of the wide bandgap semiconductor device can be improved, the driving circuit in the prior art needs to be connected to a positive voltage power supply and a negative voltage power supply respectively to realize the control process of turning on and off the wide bandgap semiconductor device, and obviously, the overall cost of the driving circuit and a system to which the driving circuit belongs can be increased.

In order to solve the above problems, the present application provides a gate driving circuit, including a first switch circuit, a second switch circuit and a charging circuit, wherein a first input terminal of the first switch circuit is connected to a power supply, receives a power supply signal, a first input terminal of the second switch circuit is grounded, the charging circuit is connected between the switch circuit and a target switch tube, and a source electrode of the target switch tube is grounded, the first switch circuit and the second switch circuit are alternately turned on, the charging circuit is configured to forward charge a gate-source capacitor when the first switch circuit is turned on so as to drive the target switch tube to be turned on, and reverse charge the gate-source capacitor when the second switch circuit is turned on so as to drive the target switch tube to be turned off.

Based on the above, referring to fig. 2, the gate driving circuit provided by the present application includes: a first switching circuit 10, a second switching circuit 20, and a charging circuit 30.

Firstly, it should be noted that the gate driving circuit provided by the present application is applied to driving the on and off of the wide bandgap semiconductor switching transistor shown in fig. 1, and for convenience of description, the switching transistor is defined as a target switching transistor in the following description. As shown in fig. 2, a gate-source capacitance Cgs exists between the gate G and the source S of the target switching tube Q0, and of course, other parasitic capacitances exist in the target switching tube Q0, which will not be described in detail herein.

Referring to fig. 2, a first input terminal of the first switch circuit 10 is connected to the power module V1, and a first input terminal of the second switch circuit 20 is grounded. In this embodiment, the connection point between the power module V1 and the first input end of the first switch circuit 10 is further connected to one end of the capacitor Cx, and the other end of the capacitor Cx is grounded, and the capacitor Cx is used as a filter capacitor of the power module V1, and is mainly used for filtering harmonic components and other interference sources in the power module V1. It should be noted that the capacitance Cx in fig. 2 is only schematic, and in practical applications, one or more capacitors may be configured according to specific parameters of the power module V1 and the electromagnetic environment of the gate driving circuit, for example, a large capacitance capacitor and a small capacitance capacitor may be configured, and then connected in parallel between the power module V1 and the first input terminal of the first switch circuit 10, although other combinations may exist, and are not listed here.

The input end of the charging circuit 30 is connected to the output ends of the first switching circuit 10 and the second switching circuit 20, the output end of the charging circuit 30 is connected to the gate of the target switching tube Q0, and further, the source of the target switching tube Q0 is grounded, it can be understood that the drain of the target switching tube Q0 needs to be connected to other post-stage circuits, and the specific connection situation of the drain of the target switching tube Q0 in the embodiment shown in fig. 2 and the subsequent embodiments is not shown, so that the charging circuit can be determined in practical application in combination with an application scenario.

The control terminals of the first switch circuit 10 and the second switch circuit 20 are respectively configured to receive a driving signal, and the first switch circuit 10 and the second switch circuit 20 are alternately turned on in response to the driving signal, that is, at the same time, only one of the first switch circuit 10 and the second switch circuit 20 is in a conductive state.

Based on the above, when the first switch circuit 10 is turned on and the second switch circuit 20 is turned off, a closed charging path shown by a dotted line S1 in fig. 2 can be obtained, that is, the electric energy provided by the power supply module V1 sequentially passes through the capacitor Cx, the first switch circuit 10 and the charging circuit 30, and finally charges the gate-source capacitor Cgs, based on the basic principle of capacitor energy storage, the voltage across the gate-source capacitor Cgs can be continuously increased, and when the voltage across the gate-source capacitor Cgs is greater than the on voltage of the target switch tube Q0, the target switch tube Q0 is driven to be turned on. It can be understood that the voltage drop direction of the gate-source capacitance Cgs at this time is the conduction direction between the gate G and the source S of the target switching transistor Q0.

Further, it can be understood that, through the foregoing conduction control process, the gate-source capacitance Cgs stores a certain amount of electric energy, based on this, when the first switch circuit 10 is turned off and the second switch circuit 20 is turned on, a closed charging path shown by a dashed line S2 in fig. 2 can be obtained, and the electric energy stored in the gate-source capacitance Cgs is transmitted through the gate G of the target switch tube Q0, the charging circuit 30 and the second switch circuit 20, and since the first input end of the second switch circuit 20 and the source S of the target switch tube Q0 are grounded, a closed charging loop can be formed, and the charging circuit 30 reversely charges the gate-source capacitance Cgs by using the electric energy stored in the gate-source capacitance Cgs, and at this time, the voltage drop direction of both ends of the gate-source capacitance Cgs is opposite to the conduction direction of the gate G and the source S of the target switch tube Q0, so as to apply a reverse turn-off voltage to the target switch tube Q0, thereby ensuring that the target switch tube Q0 is reliably turned off.

In summary, in the gate driving circuit provided by the application, the first switch circuit and the second switch circuit are alternately turned on in response to the driving signal, when the first switch circuit is turned on, the charging circuit charges the gate-source capacitance of the target switch tube forward, applies forward voltage between the gate and the source of the target switch tube, and drives the target switch tube to be turned on, and correspondingly, when the second switch circuit is turned on, because the source of the target switch tube and the first input end of the second switch circuit are grounded, a closed charging loop can be formed, the charging circuit charges the gate-source capacitance of the target switch tube reversely, and applies reverse voltage between the gate and the source of the target switch tube, so that the target switch tube is driven to be turned off reliably.

Further, on the basis of the embodiment shown in fig. 2, the present application also provides another gate driving circuit, where the charging circuit includes: the energy storage regulation sub-circuit, the first unidirectional conduction sub-circuit and the second unidirectional conduction sub-circuit.

The input end of the first unidirectional conduction sub-circuit is used as a first input end of the charging circuit and is connected with the output end of the first switching circuit, and the output end of the second unidirectional conduction sub-circuit is used as a second input end of the charging circuit and is connected with the output end of the second switching circuit. Further, the first end of the energy storage adjusting sub-circuit is connected with the output end of the first unidirectional conduction sub-circuit and the input end of the second unidirectional conduction sub-circuit respectively, and the second end of the energy storage adjusting sub-circuit is used as the output end of the charging circuit and is connected with the control end of the target switching tube.

Based on the connection relation, the conducting direction of the first unidirectional conduction sub-circuit is the same as the voltage drop direction for forward charging the grid-source capacitance of the target switch tube, and the conducting direction of the second unidirectional conduction sub-circuit is the same as the voltage drop direction for reverse charging the grid-source capacitance of the target switch tube.

Referring to fig. 3, the first unidirectional conduction sub-circuit includes a first diode D1, the second unidirectional conduction sub-circuit includes a second diode D2, and the energy storage adjustment sub-circuit 310 includes a first resistor R1 and a first inductor L1.

Specifically, the anode of the first diode D1 is used as the input end of the first unidirectional conduction sub-circuit and connected to the output end of the first switch circuit 10, and the cathode of the first diode D1 is used as the output end of the first unidirectional conduction sub-circuit and connected to the first end of the energy storage regulator sub-circuit 310; correspondingly, the cathode of the second diode D2 is connected to the output of the second switch circuit 20 as the output of the second unidirectional conduction sub-circuit, and the anode of the second diode D2 is connected to the first end of the energy storage regulator sub-circuit 310 as the input of the second unidirectional conduction sub-circuit.

Further, one end of the first resistor R1 is used as a first end of the energy storage adjusting sub-circuit 310, the other end of the first resistor R1 is connected to one end of the first inductor L1, and the other end of the first inductor L1 is used as a second end of the energy storage adjusting sub-circuit 310, i.e. is used as an output end of the charging circuit 30, and is connected to the gate G of the target switching tube Q0.

Based on the above connection relationship, when the first switch circuit 10 is turned on and the second switch circuit 20 is turned off, a forward charging loop as shown in fig. 4 can be obtained. Referring to fig. 4, the power provided by the power module V1 charges the gate-source capacitor Cgs of the target switching transistor Q0 in a forward direction through the first switching circuit 10, the first diode D1, the first resistor R1 and the first inductor L1. It will be appreciated that in the secondary process, as shown in fig. 4, the RLC series resonant circuit is formed, the power module V1 charges the first inductor L1, the current of the first inductor L1 starts to increase, when the current of the first inductor L1 reaches the maximum value, the energy of the first inductor reaches the maximum value, the power module V1 continues to charge the gate-source capacitor Cgs until the voltage of the power module V1 is reached, the current direction of the first inductor L1 cannot be reversed due to the existence of the first diode D1, the current of the first inductor L1 starts to decrease, and when the current of the first inductor L1 is zero, the energy of the first inductor L1 is completely transferred to the gate-source capacitor Cgs, and the electric energy and the voltage stored by the gate-source capacitor Cgs reach the maximum value. In this process, the voltage across the gate-source capacitance Cgs will increase continuously, and when the voltage across the gate-source capacitance Cgs is greater than the turn-on voltage of the target switching transistor Q0, the target switching transistor Q0 is driven to turn on. The direction of the voltage drop across the gate-source capacitance Cgs can now be seen in fig. 4.

Ideally, the resistance of the first resistor R1 is 0Ω, the internal resistance of the first inductor L1 is 0Ω, the internal resistance of the gate-source capacitor Cgs is infinity, the on-voltage drops of the first diode D1 and the first switch circuit 10 are all 0V, and the voltage provided by the power supply module V1 is Vcc, so that the LC charging circuit will be obtained. According to the formula vgs=2vcc (1-n/4Q), where Q is the quality factor of the first inductor L1, the ideal inductor quality factor is infinite, and therefore the voltage remaining on the gate-source capacitance Cgs will eventually settle at 2Vcc. However, in practical applications, the internal resistance of the gate-source capacitance Cgs and the quality factor of the first inductor L1 cannot be infinitely large, and meanwhile, the voltage across the gate-source capacitance Cgs is also affected by the on-resistance of the switch, which is actually smaller than 2Vcc.

Referring to fig. 5, under the condition that vcc=10v, the capacitance value of the gate-source capacitance Cgs is 50nF, and the resistance value of the first resistor R1 is adjusted to be 0 Ω, 0.2 Ω,0.5 Ω, and 1 Ω respectively, and the voltage drop change conditions at two ends of the gate-source capacitance Cgs can be obtained under the condition that the corresponding resistance value of the first resistor is obtained: the voltage Vgs across the gate-source capacitance Cgs decreases with increasing first resistance R1 until it is equal to Vcc. Based on the above, given the resistance values of the first inductor L1 and the gate-source capacitor Cgs, the maximum value of the voltage on the gate-source capacitor Cgs can be controlled by reasonably selecting the resistance value of the first resistor R1.

Further, when the first switch circuit 10 is turned off and the second switch circuit 20 is turned on, a reverse charging loop as shown in fig. 6 can be obtained. Referring to fig. 6, the gate-source capacitor Cgs, the first inductor L1, the first resistor R1, the second diode D2, and the second switching circuit 20 may form a closed loop, and the gate-source capacitor Cgs may be reversely charged while being discharged. It will be appreciated that, after the target switching tube Q0 is turned on, the voltage across the gate-source capacitance Cgs is finally stabilized at the on voltage Vgs between the gate G and the source S of the target switching tube Q0, and referring to the foregoing process, the gate driving circuit forms an RLC series resonant circuit, the electric energy stored in the gate-source capacitance Cgs is first transferred to the first inductor L1, that is, the gate-source capacitance Cgs charges the first inductor L1, when the voltage of the gate-source capacitance Cgs is zero, the current on the first inductor L1 rises from zero to the maximum value, and due to the presence of the second diode D2, the electric energy of the first inductor L1 cannot be charged back into the gate-source capacitance Cgs via the gate F, the inductor current will gradually be released through the path and reversely charged into the gate-source capacitance Cgs via the ground, and when the current of the first inductor L1 is zero, the electric energy is stored in the gate-source capacitance Cgs, and the voltage across the gate-source capacitance Cgs is the lowest-Vgs, and the corresponding voltage drop direction is shown in fig. 6.

Ideally, the resistance of the first resistor R1 is 0Ω, the internal resistance of the first inductor L1 is 0Ω, the internal resistance of the gate-source capacitor Cgs is infinity, the conduction voltage drops of the second diode D2 and the second switching circuit 20 are both 0v, and the voltages at the two ends of Cgs are finally stabilized at-Vgs. It will be appreciated that the voltage across the gate-source capacitance Cgs cannot reach-Vgs due to the internal resistance of the first inductance L1 and other parameters.

Taking SiC MOSFET switching tubes as an example, the driving on voltage is typically between 10V and 20V, and the driving off voltage is typically between-5V and 0V, in practical applications, the first resistor R1 in the energy storage regulator sub-circuit 310 needs to be adjusted in combination with the ideal situation described above to consume energy in the LC resonance process, so as to adjust the remaining voltage when the gate-source capacitance Cgs is turned off. Referring to fig. 7, from the time when the second switching circuit is turned on, the voltage Vgs across the gate-source capacitance Cgs starts to decrease. Taking the gate-source capacitance Cgs as 50nF and taking 10nH as an example, the first inductor L1 tests the gate driving circuits with the resistance values of the first resistor R1 of 0Ω,0.2Ω, 0.5Ω and 1Ω respectively, and the obtained results are: as the resistance of the first resistor R1 increases, the residual voltage on the gate-source capacitance Cgs increases (from negative to 0V) until it is equal to 0V.

Based on the above, given the first inductance L1 and the gate-source capacitance Cgs, by reasonably selecting the magnitude of the first resistor R1, the minimum value of the reverse voltage across the gate-source capacitance Cgs can be controlled to ensure that a sufficient reverse voltage is applied between the gate G and the source S of the target switching transistor Q0, thereby reliably turning off the target switching transistor Q0.

In summary, the gate driving circuit provided in this embodiment uses the characteristic that the inductance current cannot be transient and the unidirectional conduction characteristic of the diode to realize that the forward charging of the gate-source capacitor of the switching tube drives the switching tube to be conducted, and the reverse charging of the capacitor of the switch Guan Shanyuan drives the switching tube to be turned off, and simultaneously, the gate-source capacitor stores the reverse voltage, so that the misconduction of the switching tube due to the voltage fluctuation is avoided, and the reliability of the switching tube to be turned off is improved.

Further, in practical applications, the driving voltages allowed by the switching tubes of different types are different, so that the corresponding positive power supply and negative power supply must be replaced to meet the application requirements when the switching tubes of different types are driven in the prior art, or the switching tube to be driven cannot be directly replaced, and if other types of switching tubes are to be driven, the corresponding power supply must be replaced, which is obvious that the cost of the prior art is very high. Compared with the prior art, the gate driving circuit provided by the embodiment of the application can control the two ends of the gate source capacitor of the switching tube to present different voltages by matching proper resistance and inductance, that is, the gate driving circuit can be suitable for different types of switching tubes without replacing a power supply connected with the first switching circuit, thus the gate driving circuit provided by the application is more flexible, has wider application range and has lower cost when meeting the driving requirements of different types of switching tubes.

It should be noted that, in the gate driving circuit provided in the embodiment shown in fig. 3, the first resistor R1 and the first inductor L1 commonly control the voltages at two ends of the parasitic resistor Cgs of the target switching tube Q0, and the gate driving circuit is suitable for an application scenario in which the power supply voltage is used as the driving on voltage and the driving off voltage needs to be adjusted at the same time, for an application scenario in which the driving on voltage and the driving off voltage need to be adjusted at the same time, it is difficult to meet the driving requirement.

To solve this problem, the present application provides a gate driving circuit shown in fig. 8. Based on the embodiment shown in fig. 3, in the gate driving circuit provided in this embodiment, the energy storage adjusting sub-circuit includes a second resistor R2, a third resistor R3, and a second inductor L2.

Referring to fig. 8, one end of the second resistor R2 is connected to the output end of the first unidirectional conduction sub-circuit, that is, the cathode of the first diode D1, and one end of the third resistor R3 is connected to the input end of the second unidirectional conduction sub-circuit, that is, the anode of the second diode D2. One end of the second inductor L2 is connected to the other ends of the second resistor R2 and the third resistor R3, respectively, and the other end of the second inductor L2 is used as a second end of the energy storage adjusting sub-circuit 310 and is connected to the gate G of the target switching tube Q0. As for the connection relationship between the other constituent parts in the present embodiment, reference is made to the foregoing, and a description thereof will not be repeated here.

Further, in the gate driving circuit provided in the present embodiment, the power module V1, the first switching circuit 10, the first diode D1, the second resistor R2, and the second inductor L2 form a forward charging loop of the gate-source capacitor Cgs of the target switching transistor Q0; accordingly, the second inductor L2, the third resistor R3, the second diode D2, and the second switching circuit 20 constitute a reverse charging circuit of the gate-source capacitance Cgs of the target switching transistor Q0. For the forward charging and the reverse charging of the gate-source capacitance Cgs, reference should be made to the description of the foregoing embodiments, which will not be repeated here.

It should be emphasized that, in the gate driving circuit provided in this embodiment, the driving turn-on voltage of the target switching tube can be adjusted by adjusting the second resistor R2, specifically, when the driving turn-on voltage is required to be higher than the power supply voltage, the resistance value of the second resistor R2 should satisfy: When the driving turn-on voltage is required to be equal to the power supply voltage, the resistance value of the second resistor R2 should satisfy: Further, when the driving turn-off voltage is adjusted by adjusting the third resistor R3, the value of the third resistor R3 should satisfy: in practical application, the switch voltage and the drive turn-off voltage can be respectively driven according to the above content, so as to quickly adjust to the required drive voltage.

Furthermore, the application also provides another grid driving circuit. As shown in fig. 9, the gate driving circuit according to the embodiment of fig. 3 further includes a compensation circuit 40, a bleeder circuit 50, and a protection circuit 60. At the same time, alternative implementations of the first switching circuit 10 and of the second switching circuit 20 are also presented. Of course, the newly added circuit in the gate driving circuit provided in this embodiment may be combined with the gate driving circuits provided in the other embodiments, which are not explained one by one herein, and the combination of the obtained technical solutions is also within the scope of the protection of the present application under the condition that the core concept of the present application is not exceeded.

Referring to fig. 9, the first switch circuit 10 provided in the present embodiment includes a first controllable switch Q1 and a first driving sub-circuit 110, where the first driving sub-circuit 110 includes a first buffer B1, a second buffer B2, and a first delay circuit, and the first delay circuit specifically includes a third diode D3, a first capacitor C1, and a fourth resistor R4.

Specifically, the first end of the first controllable switch Q1 is connected to the power module V1 as the first input end of the first switch circuit 10, and the second end of the first controllable switch Q1 is connected to the charging circuit 30 (specifically, the anode of the first diode D1) at the subsequent stage as the output end of the first switch circuit 10.

Further, the input terminal of the first buffer B1 in the first driving sub-circuit 110 is used as the input terminal of the first driving sub-circuit 110 to receive the driving signal. The output terminal of the first buffer B1 is connected to the cathode of the third diode D3, and the anode of the third diode D3 is connected to the input terminal of the second buffer B2. Meanwhile, a fourth resistor R4 is connected in parallel with the third diode D3. One end of the first capacitor C1 is connected to the anode of the third diode D3, the other end of the first capacitor C1 is grounded, and the output end of the second buffer B2 is used as the output end of the first driving sub-circuit 110 and is connected to the control end of the first controllable switch Q1.

In the gate driving circuit provided in this embodiment, the first driving sub-circuit 110 is mainly used for configuring the on-delay and the off-delay of the first controllable switch Q1, and as for the specific working process of the first driving sub-circuit 110, the following description will be omitted herein.

The second switch circuit 20 is similar to the first switch circuit 10 in construction, and as shown in fig. 9, the second switch circuit includes a second controllable switch Q2 and a second driving sub-circuit 210, wherein the second driving sub-circuit 210 includes an inverter B4, a third buffer B3, and a second delay circuit specifically including a fourth diode D4, a second capacitor C2, and a fifth resistor R5.

Specifically, the first end of the second controllable switch Q2 is used as the first input end of the second switch circuit 20, and is directly grounded, and the second end of the second controllable switch Q2 is used as the output end of the second switch circuit 20, and is connected to the charging circuit 30 (specifically, the cathode of the second diode D2 in the charging circuit 30) of the subsequent stage.

Further, the input terminal of the inverter B4 in the second driving sub-circuit 210 is used as the input terminal of the second driving sub-circuit 210, the output terminal of the inverter B4 is connected to the cathode of the fourth diode D4, the anode of the fourth diode D4 is connected to the input terminal of the third buffer B3, meanwhile, the fifth resistor R5 is connected in parallel to the fourth diode D4, one terminal of the second capacitor C2 is connected to the anode of the fourth diode D4, the other terminal of the second capacitor C2 is grounded, and the output terminal of the third buffer B3 is used as the output terminal of the second driving sub-circuit 210 and is connected to the control terminal of the second switching tube Q2.

In the gate driving circuit provided in this embodiment, the second driving sub-circuit 210 is mainly used for configuring the on-delay and the off-delay of the second controllable switch Q2, and the specific operation process of the second driving sub-circuit 210 will be developed in the following description, which will not be described in detail herein.

It should be noted that, compared with the wide bandgap semiconductor device selected for the target switching tube Q0, the specific types of the first controllable switch Q1 and the second controllable switch Q2 are not limited in the present application, and any switch capable of being turned on or off in response to the driving signal of the driving sub-circuit is optional.

It should be further noted that, in the example shown in fig. 9 of this embodiment, the first controllable switch Q1 and the second controllable switch Q2 are both shown as N-type switching tubes, and in practical application, P-type switching tubes may be selected to implement the same, and correspondingly, the target switching tube Q0 is shown as P-type switching tubes, which is also applicable to N-type switching tubes.

As described above, in order to ensure reliable driving of the target switching transistor Q0, the gate driving circuit provided by the present application requires the first switching circuit and the second switching circuit to be alternately turned on, and the following description will be given of the process of alternately turning on the first switching circuit and the second switching circuit in response to the same driving signal in combination with the above and the circuit topology shown in fig. 9.

As shown in fig. 9, the driving signal is a PWM pulse signal having alternating high and low levels.

In the case of inputting a high level signal, the response procedure of the first switch circuit 10 and the second switch circuit 20 is as follows:

In an alternative embodiment, the first buffer B1 in the first switch circuit 10 outputs a high level, and in an alternative embodiment, the first capacitor C1 is selected, the resistance of the fourth resistor R4 is increased, the charging current of the first capacitor C1 becomes smaller, so that the time when the voltage on the first capacitor C1 reaches the on voltage of the second buffer B2 becomes longer, and thus the output of the high level by the second buffer B2 can be delayed, and the on delay of the first switch tube Q1 is increased; conversely, when the resistance of the fourth resistor R4 is reduced, the charging current of the first capacitor C1 will become larger, the time for the voltage on the first capacitor C1 to reach the on voltage of the second buffer B2 becomes shorter, and the output of the high level from the second buffer B2 can be accelerated, thereby reducing the on delay of the first switching tube Q1.

In another alternative embodiment, the fourth resistor R4 is selected, if the capacitance of the first capacitor C1 is increased, the voltage on the first capacitor C1 rises slowly, and the time for the voltage on the first capacitor C1 to reach the on voltage of the second buffer B2 is prolonged, so that the output of the high level by the second buffer B2 can be delayed, thereby increasing the on delay of the first controllable switch Q1; conversely, the capacitance value of the first capacitor C1 is reduced, the voltage on the first capacitor C1 rises rapidly, the time for the voltage on the first capacitor C1 to reach the turn-on voltage of the second buffer B2 is shortened, and the output of the high level by the second buffer B2 can be accelerated, so that the turn-on delay of the first controllable switch Q1 is reduced.

The inverter B4 in the second switch circuit 20 is input to a high level, and outputs a low level, if the second capacitor C2 already stores electric energy (i.e., a period of storing electric energy), the fourth diode D4 is turned on by the residual voltage on the second capacitor C2, the electric quantity on the second capacitor C2 is rapidly released through the fourth diode D4, the voltage on the second capacitor C2 is rapidly reduced, the third buffer B3 rapidly obtains a low level input, and outputs a low level, so as to shorten the turn-off delay of the second switch tube Q2 as much as possible. It will be appreciated that for the first high level, since the second capacitor C2 has not yet stored power, there is no process of discharging power, and accordingly, the second switching tube Q2 is already in an off state.

In the case of inputting a low level signal, the response procedure of the first switch circuit 10 and the second switch circuit 20 is as follows:

The first buffer B1 in the first switch circuit 10 outputs a low level, the residual voltage on the first capacitor C1 makes the third diode D3 turned on, the electric energy on the first capacitor C1 is rapidly released through the third diode D3, the voltage on the first capacitor C1 is rapidly reduced, the second buffer B2 rapidly obtains a low level input, and outputs a low level to the control end of the first controllable switch Q1, so that the turn-off delay of the first controllable switch Q1 is shortened.

The inverter B4 in the second switching circuit 20 outputs a high level to the subsequent stage circuit when a low level is input. Based on this, in an alternative embodiment, the second capacitor C2 is selected, the resistance value of the fifth resistor R5 is increased, the charging current of the second capacitor C2 becomes smaller, the time for the voltage on the second capacitor C2 to reach the turn-on voltage of the third buffer B3 is prolonged, and the output of the high level by the third buffer B3 is delayed, so that the turn-on delay of the second controllable switch Q2 is increased; conversely, the resistance value of the fifth resistor R5 is reduced, the charging current of the second capacitor C2 is increased, the time for the voltage on the second capacitor C2 to reach the on voltage of the third buffer B3 is shortened, and the output of the high level by the third buffer B3 can be accelerated, so that the on delay of the second controllable switch Q2 is reduced.

In another alternative embodiment, the fifth resistor R5 is selected to increase the capacitance of the second capacitor C2, the voltage on the second capacitor C2 rises slowly, the time for the voltage on the second capacitor C2 to reach the turn-on voltage of the third buffer B3 is prolonged, and the output of the third buffer B3 is delayed to a high level, so that the turn-on delay of the second controllable switch Q2 is increased; conversely, the capacitance value of the second capacitor C2 is reduced, the voltage on the second capacitor C2 rises rapidly, the time for the voltage on the second capacitor C2 to reach the turn-on voltage of the third buffer B3 is shortened, and the output of the high level by the third buffer B3 can be accelerated, so that the turn-on delay of the second controllable switch Q2 is reduced.

Based on the above process, by configuring specific selection of each element in the first delay circuit and the second delay circuit, it can be ensured that the driving signals of the first controllable switch Q1 and the second controllable switch Q2 are not high at the same time, that is, the two are alternately conducted, so that the first controllable switch Q1, the second controllable switch Q2, the first diode D1 and the second diode D2 are prevented from forming a channel, and the device is prevented from being damaged due to overcurrent. The phase relationship among the driving signal, the control signal of the first controllable switch Q1, and the control signal of the second controllable switch Q2 can be seen in fig. 10, and it can be understood that the low level duration of the interval between the high levels of the control signal of the first controllable switch Q1 and the control signal of the second controllable switch Q2, i.e. the dead time for ensuring that the first controllable switch Q1 and the second controllable switch Q2 are not turned on simultaneously.

In practical applications, in order to ensure the consistency of the delay circuit, the fourth resistor R4 and the fifth resistor R5 should preferably be high-precision resistors, and correspondingly, the first capacitor C1 and the second capacitor C2 should preferably be high-precision capacitors. As for the first buffer B1, the second buffer B2, the third buffer B3 and the inverter B4, they can be realized with reference to the related art, and the application is not limited thereto.

As for the specific process of the charging circuit 30 for charging the gate-source capacitance Cgs of the target switching tube Q0 in the forward direction and the reverse direction under the condition that the first switching circuit 10 and the second switching circuit 20 are alternately turned on in the present embodiment, reference is made to the related content of the embodiment shown in fig. 3, and the description thereof will not be repeated here.

Further, as can be seen from the foregoing, after the parameters of the first resistor R1 and the first inductor L1 are selected by the charging circuit 30, the range of the driving voltage that can be provided to the target switching tube Q0 by the gate driving circuit is determined, so if the parameters of the gate-source capacitance in the target switching tube Q0 do not satisfy the overall design of the gate driving circuit, or the gate driving circuit is not matched with the target switching tube Q0, the voltage actually applied between the gate and the source of the target switching tube can be adjusted by the compensation circuit 40.

Referring to fig. 9, the compensation circuit 40 includes a third capacitor C3, one end of the third capacitor C3 is connected to the output terminal of the charging circuit 30 as one end of the compensation circuit 40, and the other end of the third capacitor C3 is grounded as the other end of the compensation circuit 40. It can be understood that the compensation circuit 40 is equivalent to connecting the third capacitor C3 in parallel to the two ends of the gate-source capacitor Cgs, and the capacitance between the source G and the gate S of the target switching tube Q0 can be adjusted by the third capacitor C3. Thereby obtaining Vgs voltage meeting the practical application requirements. Of course, in the case of only the first resistor R1, the voltage value across the gate-source capacitance Cgs can also be adjusted by adjusting the inductance of the first inductor L1, and the foregoing is specifically referred to, and will not be repeated here.

The bleeder circuit 50 includes a sixth resistor R6, as shown in fig. 9, one end of the sixth resistor R6 is connected to the output terminal of the charging circuit 30 as one end of the bleeder circuit 50, and the other end of the sixth resistor R6 is grounded as the other end of the bleeder circuit 50. It will be appreciated that if the gate driving circuit is accidentally powered down, the drain capacitor Cgs of the target switching tube Q0 may store electric energy, so as to ensure power safety and avoid the voltage across the gate-source capacitor Cgs from causing the target switching tube Q0 to be misled, and the drain circuit 50 may be configured to release the electric energy of the gate-source capacitor Cgs. It should be noted that, the sixth resistor R6 also affects the voltage values of the two ends of the gate-source capacitor Cgs in the process of driving the target switching tube Q0, and discharges the gate-source capacitor Cgs in the working process, so that the Vgs voltage is reduced, and in order to reduce the influence of the sixth resistor R6 on the driving process of the target switching tube Q0, the value of the sixth resistor R6 should be as large as possible.

The protection circuit 60 includes a first voltage stabilizing tube D5 and a second voltage stabilizing tube D6, and as shown in fig. 9, the cathode of the first voltage stabilizing tube D5 is connected to the output end of the charging circuit 30, the anode of the first voltage stabilizing tube D5 is connected to the anode of the second voltage stabilizing tube D6, and the cathode of the second voltage stabilizing tube D6 is grounded.

Based on the connection relationship, in an ideal case, the conduction voltage drop of the first voltage stabilizing tube D5 and the second voltage stabilizing tube D6 is 0V, based on this, assuming that the voltage stabilizing value of the first voltage stabilizing tube D5 is V _D5, the voltage stabilizing value of the second voltage stabilizing tube D6 is V _D6, when the driving conduction voltage is greater than V _D6, the second voltage stabilizing tube D6 will be turned on, and the driving conduction voltage will be clamped to V _D6; correspondingly, when the driving turn-off voltage is smaller than-V _D5, the first voltage stabilizing tube D5 is conducted, and the driving turn-off voltage clamp is located at-V _D5, so that the target switching tube Q0 is guaranteed not to be damaged due to driving overvoltage under any working condition.

Based on the embodiment shown in fig. 9, when the first resistor r1=0.5Ω, the first inductor l1=10nh, the gate-source capacitor cgs=50nf, the sixth resistor r6=200kΩ, and the second voltage regulator D6 has a turn-on voltage of 23V, and the first voltage regulator D5 has a turn-on voltage of 3V, the operation process of the gate driving circuit provided in the embodiment shown in fig. 9 is subjected to a simulation test, so that the test result shown in fig. 11 can be obtained, and according to the test result shown in fig. 11, the first controllable switch Q1 and the second controllable switch Q2 are alternately turned on, and the change condition of the voltage Vgs at the two ends of the gate-source capacitor Cgs is matched with the change condition of the voltage Vgs.

Further, the present application also provides an electronic device, as shown in fig. 12, where the electronic device provided in this embodiment includes a power module V1, a signal output module 70, a target switching tube Q0, and a gate driving circuit provided in any one of the foregoing embodiments (taking the embodiment shown in fig. 9 as an example).

Referring to fig. 12, a power module V1 is connected to a first input terminal of the first switch circuit 10 in the gate driving circuit, and is configured to provide a power signal to the first switch circuit 10;

The signal output module 70 is connected to the second input terminals of the first switch circuit 10 and the second switch circuit 20 in the gate driving circuit, and is used for outputting driving signals to the first switch circuit 10 and the second switch circuit 20;

the gate driving circuit is connected with the gate of the target switching tube Q0 and is used for responding to the driving signal to drive the target switching tube Q0 to be turned on or turned off.

In practical applications, if the grounding point of the signal output module and the grounding point of the source electrode of the target switching tube Q0 are at different levels, an isolation driving design is required between the signal output module and the gate driving circuit. In one possible embodiment, isolation may be achieved by the transformer shown in fig. 13, and in another possible embodiment, isolation may also be achieved by the optocoupler isolator shown in fig. 14. For the specific implementation of the foregoing two isolation methods, reference may be made to the related art, and details thereof will not be described herein.

Those skilled in the art will appreciate that various modifications and improvements can be made to the disclosure. For example, the various devices or components described above may be implemented in hardware, or may be implemented in software, firmware, or a combination of some or all of the three.

Further, while the present disclosure makes various references to certain elements in a system according to embodiments of the present disclosure, any number of different elements may be used and run on a client and/or server. The units are merely illustrative and different aspects of the systems and methods may use different units.

A flowchart is used in this disclosure to describe the steps of a method according to an embodiment of the present disclosure. It should be understood that the steps that follow or before do not have to be performed in exact order. Rather, the various steps may be processed in reverse order or simultaneously. Also, other operations may be added to these processes.

Those of ordinary skill in the art will appreciate that all or a portion of the steps of the methods described above may be performed by a computer program that instructs associated hardware, and that the program may be stored on a computer readable storage medium, such as a read only memory, etc. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. Accordingly, each module/unit in the above embodiment may be implemented in the form of hardware, or may be implemented in the form of a software functional module. The present disclosure is not limited to any specific form of combination of hardware and software.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The foregoing is illustrative of the present disclosure and is not to be construed as limiting thereof. Although a few exemplary embodiments of this disclosure have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. It is to be understood that the foregoing is illustrative of the present disclosure and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The disclosure is defined by the claims and their equivalents.

Claims

1. A gate driving circuit for driving a target switching tube on or off, comprising: a first switch circuit, a second switch circuit and a charging circuit, wherein,

2. The gate drive circuit of claim 1, wherein the charging circuit comprises: an energy storage regulating sub-circuit, a first unidirectional conduction sub-circuit and a second unidirectional conduction sub-circuit, wherein,

3. The gate drive circuit of claim 2, wherein the tank regulator sub-circuit comprises a first resistor and a first inductor, wherein,

4. The gate drive circuit of claim 2, wherein the tank regulator sub-circuit comprises a second resistor, a third resistor, and a second inductor, wherein,

5. The gate drive circuit of claim 2, wherein the first unidirectional-on sub-circuit comprises a first diode and the second unidirectional-on sub-circuit comprises a second diode.

6. The gate drive circuit of claim 1, further comprising: a bleeder circuit, wherein,

7. The gate drive circuit of claim 1, further comprising: a compensation circuit, wherein,

8. The gate drive circuit of claim 1, further comprising: the protection circuit comprises a first voltage stabilizing tube and a second voltage stabilizing tube, wherein,

and the cathode of the second voltage stabilizing tube is grounded.

9. The gate drive circuit of any one of claims 1 to 8, wherein the first switching circuit comprises a first controllable switch and a first drive sub-circuit, wherein,

10. The gate drive circuit of claim 9, wherein the first drive sub-circuit comprises: a first buffer, a second buffer, and a first delay circuit, the first delay circuit comprising: a third diode, a first capacitor and a fourth resistor, wherein,

the fourth resistor is connected with the third diode in parallel;

11. The gate drive circuit of any one of claims 1 to 8, wherein the second switching circuit comprises a second controllable switch and a second drive sub-circuit, wherein,

12. The gate drive circuit of claim 11, wherein the second drive sub-circuit comprises: an inverter, a third buffer, and a second delay circuit, the second delay circuit comprising: a fourth diode, a second capacitor and a fifth resistor, wherein,

The fifth resistor is connected with the fourth diode in parallel;

13. An electronic device, comprising: a power supply module, a signal output module, a target switching tube, and a gate driving circuit as claimed in any one of claims 1 to 12, wherein,