CN118427003A

CN118427003A - A BOOT program upgrade device, method and electronic device

Info

Publication number: CN118427003A
Application number: CN202310118788.5A
Authority: CN
Inventors: 刘胜捷
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2023-01-31
Filing date: 2023-01-31
Publication date: 2024-08-02
Also published as: WO2024160035A1

Abstract

The embodiment of the application provides a device, a method and electronic equipment for upgrading a BOOT program, wherein the device comprises the following components: the system comprises a first BOOT memory, a second BOOT memory and a control module; the control module is respectively connected with the first BOOT memory and the second BOOT memory, and controls loading of the second BOOT program from the second BOOT memory under the condition that the first BOOT memory is abnormal in loading of the first BOOT program or the version of the first BOOT program is wrong through counting, wherein the version of the first BOOT program is higher than that of the second BOOT program.

Description

BOOT program upgrading device and method and electronic equipment

Technical Field

The present application relates to the field of embedded systems, and in particular, to a BOOT program upgrading device, a BOOT program upgrading method, and an electronic device.

Background

In the embedded system in the fields of telecommunication and communication, the BOOT is used as a bootstrap program of an operating system to finish the minimum initialization of system hardware, and is the basis of a single board CPU system. With more and more functions supported by the BOOT, application scene changes, function expansion and perfection and the like, a new function is often required to be integrated into the original BOOT of the system or related faults (bug) are solved, and the BOOT online upgrading method is widely used.

However, in the BOOT online upgrading process, accidents such as power failure, equipment reset, dead halt or BOOT program error can occur, so that a single board cannot be started normally, and customer service is interrupted; or the BOOT can be normally loaded, but the single-board clock system cannot work normally, and the like, so that the operation of the whole system is influenced, and therefore, how to improve the reliability of the BOOT online upgrade becomes a problem which needs to be solved in the industry.

Disclosure of Invention

The embodiment of the application aims to provide a device, a method, electronic equipment and a storage medium for upgrading a BOOT program, which can improve the reliability of BOOT online upgrade and realize the double error prevention functions of BOOT itself being destroyed and BOOT version errors in the BOOT online upgrade process.

In order to solve the above technical problems, embodiments of the present application are achieved by the following aspects.

In a first aspect, an embodiment of the present application provides an upgrade apparatus for a BOOT program, including: the system comprises a first BOOT memory, a second BOOT memory and a control module; the control module is respectively connected with the first BOOT memory and the second BOOT memory, and controls loading of the second BOOT program from the second BOOT memory under the condition that the first BOOT memory is abnormal in loading of the first BOOT program or the version of the first BOOT program is wrong through counting, wherein the version of the first BOOT program is higher than that of the second BOOT program.

In a second aspect, an embodiment of the present application provides a method for upgrading a BOOT program, including: and under the condition that the first BOOT memory is monitored to load a first BOOT program abnormality or the version error of the first BOOT program by counting of a control module, controlling to load a second BOOT program from a second BOOT memory, wherein the version of the first BOOT program is higher than that of the second BOOT program, and the control module is respectively connected with the first BOOT memory and the second BOOT memory.

In a third aspect, an embodiment of the present application provides an electronic device, including: a memory, a processor, and computer-executable instructions stored on the memory and executable on the processor, which when executed by the processor, perform the steps of: and under the condition that the first BOOT memory is monitored to load a first BOOT program abnormality or the version error of the first BOOT program by counting of a control module, controlling to load a second BOOT program from a second BOOT memory, wherein the version of the first BOOT program is higher than that of the second BOOT program, and the control module is respectively connected with the first BOOT memory and the second BOOT memory.

In a fourth aspect, embodiments of the present application provide a computer readable storage medium for storing computer executable instructions that when executed by a processor perform the steps of: and under the condition that the first BOOT memory is monitored to load a first BOOT program abnormality or the version error of the first BOOT program by counting of a control module, controlling to load a second BOOT program from a second BOOT memory, wherein the version of the first BOOT program is higher than that of the second BOOT program, and the control module is respectively connected with the first BOOT memory and the second BOOT memory.

In the embodiment of the application, the first BOOT memory, the second BOOT memory and the control module are used; the control module is respectively connected with the first BOOT memory and the second BOOT memory, and controls the second BOOT program to be loaded from the second BOOT memory under the condition that the first BOOT memory is abnormally loaded with the first BOOT program or the version of the first BOOT program is wrong through counting, wherein the version of the first BOOT program is higher than that of the second BOOT program, so that the reliability of BOOT online upgrading can be improved, and the double error prevention function of BOOT itself being damaged and BOOT version error in the BOOT online upgrading process is realized.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

Fig. 1 shows a schematic structural diagram of a BOOT program upgrading device according to an embodiment of the present application;

fig. 2 is a schematic diagram of another structure of a BOOT program upgrading apparatus according to an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating another configuration of a BOOT upgrade apparatus according to an embodiment of the present application;

fig. 4 is a schematic flow chart of a BOOT program upgrading method according to an embodiment of the present application;

FIG. 5 is a schematic flow chart of another method for upgrading a BOOT program according to an embodiment of the present application;

FIG. 6 is a schematic flow chart of another method for upgrading a BOOT program according to an embodiment of the present application;

Fig. 7 is a schematic flow chart of another method for upgrading a BOOT program according to an embodiment of the present application;

fig. 8 is a schematic hardware structure of an electronic device for executing the BOOT program upgrading method according to the embodiment of the present application.

Detailed Description

In order to make the technical solution of the present application better understood by those skilled in the art, the technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, shall fall within the scope of the application.

Fig. 1 shows a schematic structural diagram of a BOOT program upgrading device according to an embodiment of the present application. As shown in fig. 1, the upgrade apparatus 100 includes: a first BOOT memory 120, a second BOOT memory 130, and a control module 110.

The control module 110 is respectively connected to the first BOOT memory 120 and the second BOOT memory 130, and the control module 110 controls to load a second BOOT program from the second BOOT memory 130 when it is monitored that the first BOOT memory 120 loads a first BOOT program abnormally or the version of the first BOOT program is wrong through counting, where the version of the first BOOT program is higher than the version of the second BOOT program.

The application can be used in an embedded system started by adopting a BOOT to guide a CPU, and the CPU system of the single board adopts a hardware structure with double-guide FLASH BOOT FLASH as a main and standby hardware structure to realize a fault-tolerant function, such as a first BOOT memory is a main BOOT FLASH and a second BOOT memory is a standby BOOT FLASH; the control module 110, i.e. the monitoring circuit, may be implemented by a complex programmable logic device (Complex Programmable Logic Device, CPLD), or replaced by other programmable logic devices such as programmable array logic (Field Programmable GATE ARRAY, FPGA) according to the actual situation.

In the upgrading process of the BOOT program, the version of the first BOOT program stored in the first BOOT memory 120 (main BOOT) is higher than the version of the second BOOT program stored in the second BOOT memory 130 (standby BOOT), the first BOOT program with a high version is preferentially loaded from the first BOOT memory after the single board is powered on, the control module 110 starts counting from zero, if accidents such as power failure, equipment reset, crash or BOOT program error occur in the process, namely the loading of the first BOOT program is abnormal, the single board cannot be started normally from the first BOOT program, and the counting result exceeds a preset threshold; or if a certain communication service board adopts a B clock scheme, the version of the corresponding first BOOT program cannot be compatible with the B clock scheme single board, so that the first BOOT program can be normally loaded, but the single board clock system cannot normally work, and the counting result exceeds a preset threshold value; under the condition that the two counting results exceed the preset threshold, the control module 110 sends a main-standby switching instruction, and the CPU selects standby BOOT FLASH to start through a chip select signal, that is, controls the second BOOT program to be loaded from the second BOOT memory 130, and the BOOT online upgrade fails, but the single board can still start normally.

In the embodiment of the present application, regarding the counting function of the control module 110, for example, a counter circuit or a timer circuit may be implemented in the CPLD, and the on-line upgrading flow of the BOOT is monitored by counting the counter or timing the timer, so as to improve the reliability of the on-line upgrading of the BOOT, and implement the dual error protection function of the BOOT itself being damaged and the BOOT version being in error during the on-line upgrading process of the BOOT.

The upgrading device of the BOOT program provided by the embodiment of the application comprises a first BOOT memory, a second BOOT memory and a control module; the control module is respectively connected with the first BOOT memory and the second BOOT memory, and controls the second BOOT program to be loaded from the second BOOT memory under the condition that the first BOOT memory is abnormally loaded with the first BOOT program or the version of the first BOOT program is wrong through counting, wherein the version of the first BOOT program is higher than the version of the second BOOT program, and the dual error prevention function of the BOOT itself being destroyed and the BOOT version being wrong in the BOOT online upgrading process is realized.

Fig. 2 shows another schematic structural diagram of a BOOT program upgrading apparatus according to an embodiment of the present application. As shown in fig. 2, the upgrade apparatus 200 includes: a first BOOT memory 120, a second BOOT memory 130, and a control module 110.

The control module 110 includes: a processor 111 and a controller 112; the control end of the processor 111 is connected to the input end of the controller 112, and is configured to send a control signal to the controller 112, where the control signal is used to control the counter in the controller 112 to count; the output end of the controller 112 is connected to the feedback end of the processor 111, and is configured to output a feedback signal to the processor 111, where the feedback signal is determined according to a count result of a counter in the controller 112, and the count result of the counter in the controller 112 is overflow when the first BOOT memory 120 loads a first BOOT program exception or a version error of the first BOOT program; the processor 111 is respectively connected to the first BOOT memory 120 and the second BOOT memory 130, and is configured to control loading of the second BOOT program from the second BOOT memory 130 when the feedback signal indicates that the count result of the counter in the controller 112 is overflow.

Fig. 3 is a schematic structural diagram of another device for upgrading a BOOT program according to an embodiment of the present application. As shown in fig. 3, the upgrade apparatus 300 includes: a first BOOT memory 120, a second BOOT memory 130, and a control module 110.

The controller 112 includes a first counter 1122, a second counter 1123, a counting controller 1121, and an or gate 1124, where a control end of the processor 111 is connected to an input end of the counting controller 1121, a first output end of the counting controller 1121 is connected to an input end of the first counter 1122, and a second output end of the counting controller 1121 is connected to an input end of the second counter 1123, and is configured to send a counting start or counting zero clearing signal to the first counter 1122 or the second counter 1123.

The output end of the first counter 1122 is connected to the first input end of the or circuit 1124, the output end of the second counter 1123 is connected to the second input end of the or circuit 1124, the output end of the or circuit 1124 serves as the output end of the controller 112, and is connected to the feedback end of the processor 111, so as to determine the feedback signal according to the count result of the first counter 1122 and the count result of the second counter 1123; wherein, in the case that the processor 111 loads the first BOOT program exception from the first BOOT memory 120, the count result of the first counter 1122 is overflow; in the case where the version error of the first BOOT program is monitored, the count result of the second counter 1123 is overflow.

The processor 111 is configured to control loading of the second BOOT program from the second BOOT memory 130 when the feedback signal indicates that the count result of the first counter 1122 is overflow or the count result of the second counter 1123 is overflow.

In an embodiment of the present application, the processor 111 may communicate with the counting controller 1121 through a serial peripheral interface (SERIAL PERIPHERAL INTERFACE, SPI), and the controller 112 may access the counting controller 1121 by converting an SPI into a LOCAL BUS (LOCAL BUS) module. As shown in fig. 2 or 3, cs_m is a chip select signal sent by the processor 111 to the first BOOT memory (e.g., the main BOOT FLASH), cs_s is a chip select signal sent by the processor 111 to the second BOOT memory (e.g., the standby BOOT FLASH), CLR1 is a clear signal sent by the processor 111 to the first counter 1122 through the count controller 1121, and CLR2 is a clear signal sent by the processor 111 to the second counter 1122 through the count controller 1121. SW1 and SW2 are output signals corresponding to the first counter 1122 and the second counter 1123, respectively; the controller 112 after SW is SW1 and SW2 is or, sends a main and standby BOOT switching signal, that is, the feedback signal, to the processor 111, where the processor 111 is connected to the first BOOT memory 120 and the second BOOT memory 130 through a data bus, and is configured to control loading of the second BOOT program from the second BOOT memory 130 when the feedback signal indicates that the count result of the first counter 1122 is overflow or the count result of the second counter 1123 is overflow.

In one implementation, the count controller 1121 is configured to send a count zero signal to the first counter 1122 when the processor 111 loads the first BOOT program from the first BOOT memory 120.

In one implementation, the count controller 1121 is further configured to send a count zero signal to the second counter 1123 if it is monitored that the version of the first BOOT program is correct.

In one implementation, the processor 111 is controlled to start from the first BOOT program with both the first counter 1122 and the second counter 1123 cleared.

In one implementation, the first counter 1122 and the second counter 1123 are controlled to start counting by the count controller 1121 upon receiving a reset signal by the processor 111.

Specifically, after the BOOT online upgrade process starts, the processor 111 loads an upgrade version file (first BOOT program) to the main BOOT FLASH (first BOOT memory) through the data bus; the board resets, the processor 111 starts to start from the main BOOT (i.e. the first BOOT program) just after upgrading, and simultaneously the first counter 1122 and the second counter 1123 inside the CPLD start to count; depending on whether the main BOOT file (i.e., the first BOOT program) is intact, whether the version of the main BOOT (i.e., the first BOOT program) is correct, there are several cases:

Case 1: accidents such as single board power-off, abnormal reset and the like occur in the upgrading process, or a BOOT file loaded from a main BOOT FLASH is not perfect, so that the BOOT cannot be normally loaded, a processor cannot clear the first counter 1122 through the counting controller 1121, and finally the first counter 1122 overflows.

Case 2: in the upgrading process, the main BOOT file can be normally loaded, but the version is incorrect, the CPU can only clear the first counter 1122, the second counter 1123 continues to count, and finally the second counter 1123 overflows.

Case 3: during the upgrade process, the main BOOT file can be normally loaded, and the version is correct, and the processor 111 clears the first counter 1122 and the second counter 1123 through the count controller 1121 at the same time.

The controller 112 determines whether to output the active/standby switching signal (i.e., the feedback signal) to the processor 111 according to the above-described different situations. If the condition 3 occurs, the main BOOT is normally loaded, and the upgrade is successful; if any one of the case 1 or the case 2 occurs, the two counters will send out corresponding primary and standby BOOT switching signals SW1 or SW2 after overflowing, send out the primary and standby switching signals SW to the processor 111 after passing through the or logic of the or circuit 1124, reload from the standby BOOT after the single board resets, fail in upgrading the primary BOOT, and the maintainer should check the version file and then re-upgrade.

In the above embodiment of the present application, a counter (i.e. the first counter 1122) for monitoring whether the BOOT program is loaded normally and a counter (i.e. the second counter 1123) for monitoring whether the BOOT version is correct or not are provided in the control module 110, and in the case that the processor 111 loads the first BOOT program from the first BOOT memory 120, the counting result of the first counter 1122 is overflow; in the case that the version error of the first BOOT program is monitored, the counting result of the second counter 1123 is overflow; when the count result of the first counter 1122 is overflow or the count result of the second counter 1123 is overflow, the second BOOT program is loaded from the second BOOT memory 130, that is, the controller 112 sends a primary-standby switch instruction to the processor 111, and the board is restarted from the standby BOOT (that is, the second BOOT program), thereby realizing the dual protection effect of the damaged BOOT and version error prevention in the online upgrade process. In addition, in the embodiment of the application, only CPLD and BOOT software codes can be modified in actual operation, the current double BOOT switching architecture is not changed, and additional devices or hardware modification plates are not added, so that the BOOT on-line upgrading reliability can be improved, and meanwhile, the technical effect of saving cost can be realized.

In one implementation manner, the counter circuit which can be synthesized in the CPLD according to the embodiment of the application can specifically comprise a comparator, an adder, a data selector, a trigger and the like to realize the functions of counting, asynchronous zero clearing and automatic zero clearing of overflow; if the counter overflows, the comparator can control the trigger to generate an overflow signal, so as to control the trigger to generate a main and standby BOOT switching signal, and the specific implementation is not described in detail herein.

Fig. 4 is a schematic flow chart of a method for upgrading a BOOT program according to an embodiment of the present application, where the method may be executed by an electronic device, for example, a terminal device or a server device. In other words, the method may be performed by software or hardware installed at a terminal device or a server device. The service end includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, and the like. As shown in fig. 4, the method may include the following steps.

S402: and controlling to load the second BOOT program from the second BOOT memory under the condition that the first BOOT memory is monitored to load the first BOOT program abnormally or the version error of the first BOOT program by counting of the control module.

The version of the first BOOT program is higher than that of the second BOOT program, and the control module is respectively connected with the first BOOT memory and the second BOOT memory. Specifically, the online upgrade process starts, for example, the single board is reset, starts to start from a main BOOT (for example, a first BOOT program in a first BOOT memory), the control module starts to count, and when the first BOOT memory loads a first BOOT program abnormally or the version of the first BOOT program is wrong, the counting result exceeds a preset threshold value, the control module controls the second BOOT program to be loaded from a second BOOT memory, which means that the single board starts from a standby BOOT, the BOOT program fails to upgrade, and maintenance personnel are required to check the version file to upgrade again.

The method for upgrading the BOOT program provided by the embodiment of the application can be applied to the device for upgrading the BOOT program in any of the previous embodiments, and the second BOOT program is controlled to be loaded from the second BOOT memory under the condition that the first BOOT memory is monitored to load the first BOOT program abnormally or the version of the first BOOT program is wrong by counting the control module, wherein the version of the first BOOT program is higher than the version of the second BOOT program, and the control module is respectively connected with the first BOOT memory and the second BOOT memory, so that the reliability of BOOT online upgrading can be improved, and the double error prevention functions of BOOT itself being destroyed and BOOT version being wrong in the online upgrading process are realized.

Fig. 5 is a schematic flow chart of another method for upgrading a BOOT program according to an embodiment of the present application, where the method may be executed by an electronic device, for example, a terminal device or a server device. In other words, the method may be performed by software or hardware installed at a terminal device or a server device. The service end includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, and the like. As shown in fig. 5, the method may include the following steps.

S501: and determining a feedback signal output to the processor according to the counting result of the counter in the controller.

And under the condition that the first BOOT memory loads the first BOOT program abnormally or the version of the first BOOT program is wrong, the counting result of the counter in the controller is overflow.

S502: and controlling to load the second BOOT program from the second BOOT memory under the condition that the feedback signal indicates that the counting result of the counter in the controller is overflow.

The method for upgrading the BOOT program provided by the embodiment of the application can be applied to the device for upgrading the BOOT program in any of the previous embodiments, and determines the feedback signal output to the processor according to the counting result of the counter in the controller, wherein the counting result of the counter in the controller is overflow under the condition that the first BOOT memory loads the first BOOT program abnormally or the version of the first BOOT program is wrong; and under the condition that the feedback signal indicates that the counting result of the counter in the controller is overflow, controlling the second BOOT program to be loaded from the second BOOT memory, so that the reliability of BOOT online upgrading can be improved, and the double error prevention functions of BOOT itself being destroyed and BOOT version being in error in the BOOT online upgrading process are realized.

Fig. 6 is a schematic flow chart of a method for controlling a program according to an embodiment of the present application, where the method may be performed by an electronic device, for example, a terminal device or a server device. In other words, the method may be performed by software or hardware installed at a terminal device or a server device. The service end includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, and the like. As shown in fig. 6, the method may include the following steps.

S601: and determining the feedback signal according to the counting result of the first counter and the counting result of the second counter.

Under the condition that the processor loads a first BOOT program exception from the first BOOT memory, the counting result of the first counter is overflow; and under the condition that the version error of the first BOOT program is monitored, the counting result of the second counter is overflow.

The method comprises the steps that an online upgrading process is started, a main BOOT is upgraded by a processor through a data bus, a single board is reset, starting from the main BOOT (namely, a first BOOT program in a first BOOT memory), and counting by a first counter and a second counter, wherein the first counter is used for monitoring whether the BOOT program is successfully loaded or not, the second counter is used for monitoring whether the BOOT program version is wrong or not, and in the case that the first BOOT program is abnormally loaded from the first BOOT memory by the processor, the counting result of the first counter is overflow; and under the condition that the version error of the first BOOT program is monitored, the counting result of the second counter is overflow.

S602: and controlling to load the second BOOT program from the second BOOT memory under the condition that the feedback signal indicates that the counting result of the first counter is overflow or the counting result of the second counter is overflow.

And controlling to load a second BOOT program from a second BOOT memory under the condition that the feedback signal indicates that the counting result of the first counter is overflowed or the counting result of the second counter is overflowed, namely, the first BOOT memory is loaded with the first BOOT program abnormally or the version of the first BOOT program is wrong, indicating that the single board is started from a standby BOOT, the upgrading is failed, and requiring maintenance personnel to check the version file to be upgraded again.

The upgrading method of the BOOT program provided by the embodiment of the application can be applied to the upgrading device of the BOOT program in any of the previous embodiments, and the feedback signal is determined according to the counting result of the first counter and the counting result of the second counter, wherein the counting result of the first counter is overflow under the condition that the processor loads the first BOOT program from the first BOOT memory; under the condition that the version error of the first BOOT program is monitored, the counting result of the second counter is overflow; and under the condition that the feedback signal indicates that the counting result of the first counter is overflow or the counting result of the second counter is overflow, controlling the loading of the second BOOT program from the second BOOT memory, improving the reliability of BOOT online upgrading and realizing the double error prevention functions of BOOT itself being destroyed and BOOT version error in the BOOT online upgrading process.

In one implementation, the method further comprises: and under the condition that the processor loads a first BOOT program from the first BOOT memory normally, sending a zero clearing signal to the first counter through a counting controller.

In one implementation, the method further comprises: and sending a zero clearing signal to the second counter through a counting controller under the condition that the processor monitors that the version of the first BOOT program is correct.

In one implementation, the method further comprises: and controlling the first counter and the second counter to start counting by the counting controller under the condition that the processor receives a reset signal.

Fig. 7 is a schematic flow chart of another method for upgrading a BOOT program according to an embodiment of the present application, where the method may be performed by an electronic device, for example, a terminal device or a server device. In other words, the method may be performed by software or hardware installed at a terminal device or a server device. The service end includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, and the like. As shown in fig. 7, the method may include the following steps.

S700: the processor loads a first BOOT program from the first BOOT memory through the data bus for upgrading.

S701: and resetting the single board, starting the system from the first BOOT memory, and starting counting by a counter in the control module.

In the step, under the condition that the processor receives a reset signal, the first counter and the second counter are controlled to start counting by the counting controller.

S7021: and judging whether the first BOOT program is normally loaded.

And under the condition that the processor loads a first BOOT program (main BOOT) from the first BOOT memory (main BOOT FLASH) normally, sending a zero clearing signal to the first counter through a counting controller. And under the condition that the processor loads a first BOOT program exception from the first BOOT memory, the counting result of the first counter is overflow.

S7022: and judging whether the version of the first BOOT program is correct.

And sending a zero clearing signal to the second counter through a counting controller under the condition that the processor judges that the version of the first BOOT program is correct. And under the condition that the processor judges that the version of the first BOOT program is wrong, the counting result of the second counter is overflow.

S7031: and under the condition that the first counter and the second counter are both cleared, controlling the processor to load a first BOOT program from the first BOOT memory.

This step represents the success of the processor loading the main BOOT file.

S7032: and controlling the processor to load a second BOOT program from the second BOOT memory under the condition that the counting result of the first counter is overflow or the counting result of the second counter is overflow.

This step represents that the processor loads the main BOOT file abnormally, and loads the old version BOOT file from the standby BOOT instead.

S7041: the single board is started from the first BOOT memory.

The single board is started from the main BOOT, and the upgrade is successful.

S7042: the single board is started from the second BOOT memory.

I.e. the single board is started from the standby BOOT and the upgrade fails.

S705: and checking the BOOT version file, and re-upgrading.

In the step, after the BOOT upgrading fails, maintenance personnel can check the BOOT version file and upgrade again.

Therefore, the embodiment of the application determines the feedback signal output to the processor according to the counting result of the first counter and the counting result of the second counter; according to the feedback signal, the processor is controlled to load the first BOOT program from the first BOOT memory or load the second BOOT program from the second BOOT memory, so that the error BOOT version is effectively prevented from being upgraded due to human negligence and the like in the upgrading process, double protection of the integrity and the correctness of the BOOT version is realized, the reliability of online BOOT upgrading is improved, no additional devices or complicated hardware circuits are required, and the cost is reduced and the implementation is simple.

The upgrading method of the BOOT program provided by the embodiment of the application can be executed by the upgrading device of the BOOT program described in the previous embodiment, and can realize the same functions and beneficial effects, and is not repeated here.

Fig. 8 is a schematic diagram of a hardware structure of an electronic device for executing the BOOT program upgrading method according to the embodiment of the present application, and with reference to this figure, at a hardware level, the electronic device includes a processor, optionally including an internal bus, a network interface, and a memory. The Memory may include a Memory, such as a Random-Access Memory (RAM), and may further include a non-volatile Memory (non-volatile Memory), such as at least 1 disk Memory. Of course, the electronic device may also include hardware required for other services.

The processor, network interface, and memory may be interconnected by an internal bus, which may be an industry standard architecture (Industry Standard Architecture, ISA) bus, a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The buses may be classified as address buses, data buses, control buses, etc. For ease of illustration, only one bi-directional arrow is shown in the figure, but not only one bus or one type of bus.

And the memory is used for storing programs. In particular, the program may include program code including computer-operating instructions. The memory may include memory and non-volatile storage and provide instructions and data to the processor.

The processor reads the corresponding computer program from the nonvolatile memory into the memory and then runs to form a device for locating the target user on a logic level. A processor executing the program stored in the memory, and specifically configured to execute: and under the condition that the first BOOT memory is monitored to load a first BOOT program abnormality or the version error of the first BOOT program by counting of a control module, controlling to load a second BOOT program from a second BOOT memory, wherein the version of the first BOOT program is higher than that of the second BOOT program, and the control module is respectively connected with the first BOOT memory and the second BOOT memory.

The upgrading device of the BOOT program disclosed in the embodiments shown in fig. 1 to 3 of the present application may be the electronic device, or may be a subsystem of the electronic device including each component of the upgrading device, for example, a processor in the upgrading device may be a processor of the electronic device, or may be a functional component of the processor of the electronic device for implementing the upgrading method disclosed in the embodiments shown in fig. 4 to 7 of the present application, where the first BOOT memory and the second BOOT memory in the upgrading device may be memories in the electronic device.

The processor of the electronic device may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; but may also be a digital signal Processor (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method.

The electronic device may also execute the methods described in the foregoing method embodiments, and implement the functions and beneficial effects of the methods described in the foregoing method embodiments, which are not described herein.

Of course, other implementations, such as a logic device or a combination of hardware and software, are not excluded from the electronic device of the present application, that is, the execution subject of the following processing flows is not limited to each logic unit, but may be hardware or a logic device.

The embodiment of the present application also proposes a computer-readable storage medium storing one or more programs that, when executed by an electronic device comprising a plurality of application programs, cause the electronic device to: and under the condition that the first BOOT memory is monitored to load a first BOOT program abnormality or the version error of the first BOOT program by counting of a control module, controlling to load a second BOOT program from a second BOOT memory, wherein the version of the first BOOT program is higher than that of the second BOOT program, and the control module is respectively connected with the first BOOT memory and the second BOOT memory.

The computer readable storage medium includes Read-Only Memory (ROM), random access Memory (Random Access Memory RAM), magnetic disk or optical disk, etc.

Further, embodiments of the present application also provide a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, implement the following flow: and under the condition that the first BOOT memory is monitored to load a first BOOT program abnormality or the version error of the first BOOT program by counting of a control module, controlling to load a second BOOT program from a second BOOT memory, wherein the version of the first BOOT program is higher than that of the second BOOT program, and the control module is respectively connected with the first BOOT memory and the second BOOT memory.

In summary, the foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. One typical implementation is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims

1. An upgrade apparatus for a BOOT program, comprising: the system comprises a first BOOT memory, a second BOOT memory and a control module;

The control module is respectively connected with the first BOOT memory and the second BOOT memory, and controls loading of the second BOOT program from the second BOOT memory under the condition that the first BOOT memory is abnormal in loading of the first BOOT program or the version of the first BOOT program is wrong through counting, wherein the version of the first BOOT program is higher than that of the second BOOT program.

2. The apparatus of claim 1, wherein the control module comprises: a processor and a controller;

The control end of the processor is connected with the input end of the controller and is used for sending a control signal to the controller, and the control signal is used for controlling the counter in the controller to count;

the output end of the controller is connected with the feedback end of the processor and is used for outputting a feedback signal to the processor, the feedback signal is determined according to the counting result of a counter in the controller, and the counting result of the counter in the controller is overflowed under the condition that the first BOOT memory loads a first BOOT program abnormality or the version of the first BOOT program is wrong;

The processor is respectively connected with the first BOOT memory and the second BOOT memory and is used for controlling the second BOOT program to be loaded from the second BOOT memory under the condition that the feedback signal indicates that the counting result of the counter in the controller is overflow.

3. The method of claim 2, wherein the controller comprises a first counter, a second counter, a counting controller and an or gate, wherein a control end of the processor is connected with an input end of the counting controller, a first output end of the counting controller is connected with the input end of the first counter, and a second output end of the counting controller is connected with the input end of the second counter and is used for sending a counting start or counting zero signal to the first counter or the second counter;

The output end of the first counter is connected with the first input end of the OR gate circuit, the output end of the second counter is connected with the second input end of the OR gate circuit, the output end of the OR gate circuit is used as the output end of the controller and is connected with the feedback end of the processor, and the feedback signal is determined according to the counting result of the first counter and the counting result of the second counter;

Under the condition that the processor loads the first BOOT program from the first BOOT memory, the counting result of the first counter is overflow; under the condition that the version error of the first BOOT program is monitored, the counting result of the second counter is overflow;

and the processor is used for controlling the second BOOT program to be loaded from the second BOOT memory under the condition that the feedback signal indicates that the counting result of the first counter is overflow or the counting result of the second counter is overflow.

4. The apparatus of claim 3 wherein said count controller is configured to send a count zero signal to said first counter in the event that said processor loads said first BOOT program from said first BOOT memory.

5. The apparatus of claim 3, wherein the count controller is further configured to send a count zero signal to the second counter if the version of the first BOOT program is monitored to be correct.

6. The apparatus of claim 3, wherein the processor is controlled to start from the first BOOT program with both the first counter and the second counter cleared.

7. A device according to claim 3, wherein the first counter and the second counter are controlled to start counting by the count controller in case the processor receives a reset signal.

8. A method for upgrading a BOOT program, the method comprising:

And under the condition that the first BOOT memory is monitored to load a first BOOT program abnormality or the version error of the first BOOT program by counting of a control module, controlling to load a second BOOT program from a second BOOT memory, wherein the version of the first BOOT program is higher than that of the second BOOT program, and the control module is respectively connected with the first BOOT memory and the second BOOT memory.

9. The method according to claim 8, characterized in that the method comprises:

Determining a feedback signal output to a processor according to a counting result of a counter in a controller, wherein the counting result of the counter in the controller is overflowed under the condition that the first BOOT memory loads the first BOOT program abnormally or the version of the first BOOT program is wrong;

And controlling to load the second BOOT program from the second BOOT memory under the condition that the feedback signal indicates that the counting result of the counter in the controller is overflow.

10. The method according to claim 9, comprising:

Determining the feedback signal according to the counting result of the first counter and the counting result of the second counter, wherein the counting result of the first counter is overflow under the condition that the processor loads a first BOOT program from the first BOOT memory; under the condition that the version error of the first BOOT program is monitored, the counting result of the second counter is overflow;

And controlling to load the second BOOT program from the second BOOT memory under the condition that the feedback signal indicates that the counting result of the first counter is overflow or the counting result of the second counter is overflow.

11. The method according to claim 9, wherein the method further comprises:

And under the condition that the processor loads a first BOOT program from the first BOOT memory normally, a count zero clearing signal is sent to the first counter through a count controller.

12. The method according to claim 9, wherein the method further comprises:

And under the condition that the processor monitors that the version of the first BOOT program is correct, sending a count zero clearing signal to the second counter through a count controller.

13. The method according to claim 9, wherein the method further comprises:

and controlling the first counter and the second counter to start counting by the counting controller under the condition that the processor receives a reset signal.

14. An electronic device comprising a processor, a memory, and a program or instruction stored on the memory and executable on the processor, which when executed by the processor, implements the upgrade method of any of claims 8-13.

15. A readable storage medium, wherein a program or instructions is stored on the readable storage medium, which when executed by a processor, implements the upgrade method according to any one of claims 8-13.