CN118231436A

CN118231436A - A wiring substrate and a manufacturing method thereof, a light-emitting panel and a display device

Info

Publication number: CN118231436A
Application number: CN202211635502.2A
Authority: CN
Inventors: 胡海峰; 曾亭; 张小祥; 刘欢; 查鑫; 肖涛; 张仁伟; 杨财桂; 柳宵宵; 李鑫
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Ruisheng Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Ruisheng Technology Co Ltd
Priority date: 2022-12-19
Filing date: 2022-12-19
Publication date: 2024-06-21

Abstract

The embodiment of the disclosure provides a wiring substrate, a preparation method thereof, a light-emitting panel and a display device. The wiring substrate comprises a buffer layer, a first metal layer, a first passivation layer, a first organic layer, a second passivation layer, a second metal layer, a third passivation layer, a second organic layer and a fourth passivation layer which are sequentially arranged on one side of the substrate, the ratio range of the thickness of the first metal layer to the thickness of the buffer layer is 5-7, the second metal layer comprises a plurality of connecting ends and a plurality of connecting wires, at least one connecting end is connected with the exposed surface of the first metal wiring through the connecting wires, the second organic layer is provided with a third via hole, and orthographic projection of the connecting ends on the substrate is located in the orthographic projection range of the third via hole on the substrate. According to the technical scheme, stress mutation of the climbing position of the connecting end can be avoided, microcracks are avoided from being generated on the passivation layer, the problem of corner defect of the subsequent gold melting process is improved, the product yield is improved, and the product reliability is improved.

Description

Wiring substrate, preparation method thereof, light-emitting panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to a wiring substrate, a preparation method thereof, a light-emitting panel and a display device.

Background

Organic light emitting diode display (OLED) is a new generation of display technology following liquid crystal display LCDs, and the technology is already mature. Mini LEDs (sub-millimeter light emitting diode chips) and Micro LEDs (Micro light emitting diode chips) have excellent performances of lower power consumption, faster reaction, longer service life, better color saturation contrast and the like. With technological breakthroughs, mini LEDs and Micro LEDs will become the next generation display technology following LCDs, OLEDs.

In order to ensure display brightness, the thickness of the metal wire is continuously increased for Mini LED display products. As the thickness of the metal wire increases, the yield of the Mini LED display product decreases, and there is a reliability risk.

Disclosure of Invention

Embodiments of the present disclosure provide a wiring substrate, a method of manufacturing the same, a light emitting panel, and a display device to solve or alleviate one or more technical problems in the prior art.

As a first aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a wiring substrate including: comprising the following steps:

A substrate base;

a buffer layer located at one side of the substrate base plate;

the first metal layer is positioned on one side of the buffer layer, which is far away from the substrate, and comprises a plurality of first metal wires, and the ratio of the thickness of the first metal layer to the thickness of the buffer layer is 5-7;

the first passivation layer is positioned on one side of the first metal layer, which is away from the substrate base plate;

The first organic layer is positioned on one side of the first passivation layer, which is away from the substrate, and is provided with a first via hole, and the orthographic projection of the first via hole on the substrate and the orthographic projection of the first metal wire on the substrate are at least partially overlapped;

The second passivation layer is positioned on one side of the first organic layer, which is away from the substrate base plate, and is provided with a second via hole penetrating through the second passivation layer and the first passivation layer, and the second via hole exposes part of the surface of the first metal wire;

The second metal layer is positioned on one side of the second passivation layer, which is far away from the substrate base plate, and comprises a plurality of connecting ends and a plurality of connecting wires, wherein at least one connecting end is connected with the exposed surface of the first metal wire through the connecting wire;

the third passivation layer is positioned on one side of the second metal layer, which is away from the substrate base plate;

The second organic layer is positioned on one side of the third passivation layer, which is far away from the substrate, and is provided with a third via hole, and the orthographic projection of the connecting end on the substrate is positioned in the orthographic projection range of the third via hole on the substrate;

and the fourth passivation layer is positioned on one side of the second organic layer, which is away from the substrate base plate, and is provided with a fourth via hole, and at least part of the surface of the connecting end is exposed by the fourth via hole.

In one embodiment, the thickness of the first metal trace ranges from 2.5 μm to 3 μm, and/or the thickness of the buffer layer ranges from 3500 to 5500 a.

In one embodiment, the first passivation layer has a thickness in the range of 2000 to 2800 angstroms; and/or the thickness of the second passivation layer ranges from 2000 to 2800 a; and/or the thickness of the third passivation layer ranges from 2000 to 2800 angstroms; and/or the thickness of the fourth passivation layer ranges from 2000 to 2800.

In one embodiment, the stress range of the first passivation layer is-350 Mpa to-450 Mpa; and/or the stress range of the second passivation layer is-350 Mpa to-450 Mpa; and/or the stress range of the third passivation layer is-350 Mpa to-450 Mpa; and/or the stress range of the fourth passivation layer is-350 Mpa to-450 Mpa.

In one embodiment, the thickness of the first organic layer ranges from 3 μm to 4 μm; and/or the thickness of the second organic layer ranges from 2 μm to 3 μm.

In one embodiment, the thickness of the second metal layer ranges from 0.9 μm to 1 μm.

In one embodiment, the cross section of the connection end on the plane perpendicular to the direction of the substrate is trapezoid, the orthographic projection of the surface of the connection end on the side facing away from the substrate on the substrate is located in the orthographic projection range of the surface of the connection end on the side facing toward the substrate on the substrate, and the orthographic projection of the surface of the connection end on the side facing away from the substrate on the substrate is located in the orthographic projection range of the fourth via hole on the substrate.

As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a method of manufacturing a wiring substrate, including:

depositing a buffer layer on one side of a substrate by physical vapor deposition;

forming a first metal layer on one side of the buffer layer, which is far away from the substrate, wherein the first metal layer comprises a plurality of first metal wires, and the ratio of the thickness of the first metal layer to the thickness of the buffer layer is 5-7;

Forming a first passivation layer on one side of the first metal layer, which is far away from the substrate;

forming a first organic layer on one side of the first passivation layer, which is far away from the substrate, wherein the first organic layer is provided with a first via hole, and the orthographic projection of the first via hole on the substrate at least partially overlaps with the orthographic projection of the first metal wire on the substrate;

Forming a second passivation layer on one side of the first organic layer, which is far away from the substrate, wherein the second passivation layer is provided with a second via hole penetrating through the second passivation layer and the first passivation layer, and a first overlapping area exists between orthographic projection of the second via hole on the substrate and orthographic projection of the first via hole on the substrate, and the first overlapping area exposes part of the surface of the first metal wire;

forming a second metal layer on one side of the second passivation layer, which is far away from the substrate, wherein the second metal layer comprises a plurality of connecting ends and a plurality of connecting wires, and at least one connecting end is connected with the exposed surface of the first metal wire through the connecting wire;

Forming a third passivation layer on one side of the second metal layer, which is away from the substrate;

Forming a second organic layer on one side of the third passivation layer, which is far away from the substrate, wherein the second organic layer is provided with a third via hole, and the orthographic projection of the connecting end on the substrate is positioned in the orthographic projection range of the third via hole on the substrate;

And forming a fourth passivation layer on one side of the second organic layer, which is far away from the substrate, wherein the fourth passivation layer is provided with a fourth via hole, at least part of orthographic projection of the fourth via hole on the substrate is positioned in the orthographic projection range of the third via hole on the substrate, and the fourth via hole penetrates through the fourth passivation layer and the third passivation layer to expose at least part of the surface of the connecting end.

In one embodiment of the present invention, in one embodiment,

Depositing a first passivation layer by adopting a chemical vapor deposition mode, wherein in the deposition process, the flow rate of the silicon hydride gas is 2500-2540 Sccm, the flow rate of the ammonia gas is 8800-8840 Sccm, and the flow rate of the nitrogen gas is 38000-40000 Sccm; and/or the number of the groups of groups,

Depositing a second passivation layer by adopting a chemical vapor deposition mode, wherein in the deposition process, the flow rate of the silicon hydride gas is 2500-2540 Sccm, the flow rate of the ammonia gas is 8800-8840 Sccm, and the flow rate of the nitrogen gas is 38000-40000 Sccm; and/or the number of the groups of groups,

Depositing a third passivation layer by adopting a chemical vapor deposition mode, wherein in the deposition process, the flow rate of the silicon hydride gas is 2500-2540 Sccm, the flow rate of the ammonia gas is 8800-8840 Sccm, and the flow rate of the nitrogen gas is 38000-40000 Sccm; and/or the number of the groups of groups,

And depositing a fourth passivation layer by adopting a chemical vapor deposition mode, wherein in the deposition process, the flow rate of the silicon hydride gas is 2500-2540 Sccm, the flow rate of the ammonia gas is 8800-8840 Sccm, and the flow rate of the nitrogen gas is 38000-40000 Sccm.

In one embodiment of the present invention, in one embodiment,

The curing temperature of the first organic layer is 200-250 ℃ and the curing time is 55-65 minutes; and/or the number of the groups of groups,

The curing temperature of the second organic layer is 200-250 ℃ and the curing time is 55-65 minutes.

As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a light emitting panel, including the wiring substrate in any one of the embodiments of the present disclosure, further including a plurality of light emitting diode chips, where the plurality of light emitting diode chips are correspondingly connected to the first metal wire.

As a fourth aspect of embodiments of the present disclosure, embodiments of the present disclosure provide a display device including the light emitting panel in any one of the embodiments of the present disclosure.

According to the technical scheme, the compressive stress generated by the buffer layer can better compensate the tensile stress generated by the first metal layer, the warping of the substrate is reduced better, the flatness of the wiring substrate is improved, the stress mutation of the wiring substrate is reduced, the stress mutation of the climbing position of the connecting end is avoided, microcracks are avoided from being generated by the passivation layer, the problem of the gold melting unfilled corner in the subsequent gold melting process is improved, the product yield is improved, and the product reliability is improved.

The foregoing summary is for the purpose of the specification only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will become apparent by reference to the drawings and the following detailed description.

Drawings

In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not to be considered limiting of its scope.

FIG. 1A is a schematic diagram of a connection relationship of a light-emitting panel in the related art;

FIG. 1B is a schematic diagram illustrating a connection relationship of a pixel in FIG. 1A;

FIG. 1C is a schematic plan view of a pixel of a wiring substrate in the light-emitting panel shown in FIG. 1A;

FIG. 2 is a graph showing the stress trend of a copper layer with thickness;

fig. 3 is a schematic partial cross-sectional view of a wiring substrate in the related art;

FIG. 4 is an enlarged schematic view of a microscope for the positions of pads in a wiring substrate;

FIG. 5 is a schematic cross-sectional view of A-A in the wiring substrate shown in FIG. 1C in an embodiment of the present disclosure;

FIG. 6 is a schematic cross-sectional view of A-A in the wiring substrate shown in FIG. 1C in another embodiment of the present disclosure;

FIG. 7A is a schematic cross-sectional view of a wiring substrate after forming a first via in an embodiment of the present disclosure;

FIG. 7B is a schematic cross-sectional view of a wiring substrate after forming a second via in an embodiment of the disclosure;

FIG. 7C is a schematic cross-sectional view of a wiring substrate after forming a third via in accordance with one embodiment of the present disclosure;

FIG. 7D is a schematic cross-sectional view of the wiring substrate of FIG. 6 after forming a third via hole therein;

fig. 8A is a graph of test results of the influence of PVX2 variation on warpage and unfilled corners of a wiring substrate;

FIG. 8B is a graph of test results of the effect of organic layer curing on warpage and unfilled corners of a wiring substrate;

fig. 8C is a graph of test results of the influence of the thickness of the buffer layer PVX0 on warpage and unfilled corners of the wiring substrate;

fig. 8D is a graph of test results of the influence of PVX1 variation on warpage and unfilled corners of the wiring substrate.

Reference numerals illustrate:

11. A substrate base; 12. a buffer layer; 13. a first metal wire; 141. a first passivation layer; 142. a second passivation layer; 15. a first organic layer; 161. a connection end; 162. a connecting wire; 171. a third passivation layer; 172. a fourth passivation layer; 18. a second organic layer; 21. a first via; 22. a second via; 23. a third via; 24. and a fourth via.

Detailed Description

Hereinafter, only certain exemplary embodiments are briefly described. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways, and the different embodiments may be combined arbitrarily without conflict, without departing from the spirit or scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.

Herein, the light emitting Diode chip may be a sub-millimeter light emitting Diode (MINI LIGHT EMITTING Diode, abbreviated as Mini LED) chip, or may be a Micro LIGHT EMITTING Diode (Micro LED) chip.

In the related art, the substrate provided with the light emitting diode chip may be an FR4 type Printed Circuit Board (PCB), or may be any one of a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, and the like. The PCB substrate has poor heat dissipation and cannot meet the requirements of large-size products. The glass substrate has good heat dissipation and can meet the requirement of large-size products.

In LED display products, the material of the metal trace comprises copper. In order to ensure the brightness of the display product, the thickness of the metal wire is gradually increased, and the brightness effect is better when the thickness of the metal wire is larger. In the related art, the thickness of the copper layer is greater than 1.8 μm.

Fig. 1A is a schematic diagram of a connection relationship of a light emitting panel in the related art, and fig. 1B is a schematic diagram of a connection relationship of one pixel in fig. 1A. As shown in fig. 1A and 1B, the light emitting panel may include: a substrate base plate 11; a plurality of pixels 31 are located over the substrate 11. The plurality of pixels 31 are arranged in an array in a first direction F1 and a second direction F2, and the first direction F1 and the second direction F2 intersect each other. Referring to fig. 1A and 1B, at least one pixel 31 among the plurality of pixels 31 includes: a sub-pixel 311 and a micro-driving chip 312 for driving each sub-pixel 311 in the pixel 31; each sub-pixel 311 includes at least one light emitting diode chip; the micro driving chip 312 includes: a data signal terminal Da and an address signal terminal Uc.

The light emitting panel may further include M address signal lines S and N data lines D. The address signal line S is located above the substrate 11. Each address signal line Si (0 < i.ltoreq.m, i being a positive integer) is coupled to an address signal terminal Uc of each micro-driving chip 312 of a row of pixels 31 arranged in the first direction F1.

N data lines D are located on the substrate 11. Each data line Dj (0 < j is equal to N, j is a positive integer) is coupled to the data signal end Da of each micro driving chip 312 of a row of pixels arranged in the second direction F2.

It should be noted that the first direction may be a row direction, and the second direction may be a column direction; alternatively, the first direction may be a column direction and the second direction may be a row direction, which is not limited herein. For ease of illustration, in the embodiments of the present disclosure, the first direction is a row direction and the second direction is a column direction.

In fig. 1A and 1B, an example is shown in which each sub-pixel includes one led chip, and in a specific implementation, the sub-pixel may also include more led chips, which is not limited herein.

Illustratively, as shown in fig. 1A, the respective address signal lines Si extend in a first direction F1 and are arranged in a second direction F2; each of the address signal lines Si is located in a gap between two adjacent rows of pixels 31 arranged in the first direction F1.

The light emitting panel may further include M address signal patch cords Q, for example. The M address signal patch cords Q extend along the second direction F2 and are arranged along the first direction F1. The address signal transfer lines Qi (i is 0 < i.ltoreq.m, i is a positive integer) are in one-to-one correspondence with the address signal lines Si, and for example, the address signal transfer line Q1 is in correspondence with the address signal line S1.

The address signal switching line Q and the address signal line S are arranged in different layers, and the address signal switching line Qi is coupled with the corresponding address signal line Si through a first through hole (shown as a black circle at the crossing position of the address signal switching line Qi and the address signal line Si in the figure); the first via hole penetrates through an insulating layer between the address signal patch cord Qi and the address signal line Si.

Illustratively, as shown in fig. 1A, each data line Dj extends in the second direction F2 and is arranged in the first direction F1. The data line Dj is located in a gap between adjacent two rows of pixels 31 arranged in the first direction F1.

Referring to fig. 1A and 1B, the light emitting panel may further include: n power supply signal lines Va and Vb, and N fixed voltage signal lines G.

The micro-drive chip 312 may further include: signal path terminals CH (e.g., CH1, CH2, CH 3) and a fixed voltage signal terminal Gd.

The power signal lines Vaj, vbj are coupled to the first electrodes of the light emitting diode chips of the row of pixels 31 arranged in the second direction F2; the second electrode of each led chip in the pixel 31 is coupled to each signal channel CH of the micro-driver chip 312; the first electrode may be an anode of the light emitting diode chip, and the second electrode may be a cathode of the light emitting diode chip.

The fixed voltage signal line Gj (0 < j.ltoreq.n, j is a positive integer) is coupled to the fixed voltage signal terminals Gd of the micro driving chips 312 of the pixels 31 arranged in the second direction F2.

The power signal line Vaj (or Vbj) (0 < j.ltoreq.N, j is a positive integer) is coupled to the first electrode of the light emitting diode chip, so that the power signal line Vaj (or Vbj) can provide power to the light emitting diode chip, and the second electrode of the light emitting diode chip is coupled to the signal channel terminal CH of the micro driving chip 312, the fixed voltage signal line Gj is coupled to the fixed voltage signal terminal Gd of the micro driving chip 312, and the fixed voltage signal line Gj can provide a fixed voltage signal to the micro driving chip 312 to form a power supply loop. The led chip is a current-driven element, and the micro-driving chip 312 provides a signal path to the coupled led chip through the signal channel CH, so that the led chip realizes different brightness under the control of current signals with different current amplitudes and/or different duty cycles. Alternatively, each power supply signal line Vaj (or Vbj) and each fixed voltage signal line Gj may be provided in a gap between two adjacent pixel columns.

In particular implementations, referring to fig. 1A and 1B, the pixel 31 includes at least: red subpixel R, green subpixel G, and blue subpixel B. The red subpixel R may include at least one red micro light emitting diode chip, the green subpixel G may include at least one green micro light emitting diode chip, and the blue subpixel B may include at least one blue micro light emitting diode chip.

The plurality of power signal lines are divided into a plurality of first power signal lines Vaj and a plurality of second power signal lines Vbj.

The first power signal line Vaj is coupled to a first electrode of each red subpixel R of the row of pixels 31 arranged in the second direction F2.

The second power signal line Vbj is coupled to the first poles of the green and blue sub-pixels G and B of the row of pixels 31 arranged in the second direction F2.

Alternatively, as shown in fig. 1A, the light emitting panel may further include M auxiliary signal lines W. Each of the auxiliary signal lines Wi (i is 0 < M, i is a positive integer) extends in the first direction F1 and is arranged in the second direction F2.

The auxiliary signal line Wi is located in a gap between two adjacent rows of pixels 31 arranged in the first direction F1, avoiding affecting light emission of each sub-pixel.

The auxiliary signal lines Wi and the fixed voltage signal lines Gj are arranged in different layers, and each auxiliary signal line Wi is coupled with at least one fixed voltage signal line Gj through a second through hole (shown as a black circle at the crossing position of the auxiliary signal line Wi and the fixed voltage signal line Gj in the figure); the second via hole penetrates through the insulating layer between the auxiliary signal line Wi and the fixed voltage signal line Gj.

Fig. 1C is a schematic plan view of a pixel of the wiring substrate in the light-emitting panel shown in fig. 1A. The first and second metal traces of the hetero-layer arrangement are shown in fig. 1C. The first metal wirings include power signal lines Vaj and Vbj, a fixed voltage signal line Gj, a data line Dj, and an address signal patch line Qi. The second metal wiring includes an address signal line Si and terminal signal connection lines, which may include connection terminals and connection lines connected to the connection terminals. The connection terminals include red sub-pixel connection terminals R+ and R-, green sub-pixel connection terminals G+ and G-, blue sub-pixel connection terminals B+ and B-, and pixel driving chip connection terminals CH1, CH2, CH3, da, uc, and Gd.

Illustratively, a portion of the area of each connection terminal is exposed, which may be referred to as a pad, and a plurality of pads coupled to the same electronic component may form a pad group. Four pad groups are shown in fig. 1C, a first pad group (pads r+ and R-), a second pad group (pads g+ and G-), a third pad group (pads b+ and B-) and a fourth pad group (pads CH1, CH2, CH3, da, uc and Gd), respectively. The first bonding pad group, the second bonding pad group and the third bonding pad group are respectively coupled with the red light emitting diode chip, the green light emitting diode chip and the blue light emitting diode chip LED, and the fourth bonding pad group is coupled with the micro-driving chip.

Fig. 2 is a schematic diagram showing the variation trend of the stress of the copper layer with the thickness, wherein the abscissa in fig. 2 is the thickness of the Cu thin film, in a unit of emm, and the ordinate is the stress value, in a unit of Mpa. As can be seen from fig. 2, the stress of the copper layer increases with increasing thickness. When a copper layer is formed on a glass substrate, the glass warpage value also increases with increasing stress and thickness of the copper layer. When the warp value of the substrate is too large, the preparation process of the substrate cannot be performed, and the risk of breaking the wafer is increased.

Fig. 3 is a schematic partial cross-sectional view of a wiring substrate in the related art. Herein, when the stress of the film layer is positive stress, it means that the film layer is tensile stress to the substrate, so that the substrate is warped upwards (i.e. warped in the positive direction); when the stress of the film layer is negative, it means that the film layer is compressive to the substrate, and the substrate will warp downward (i.e. warp negatively), as shown in fig. 3. In the embodiments of the present disclosure, when negative warpage is not mentioned, positive warpage is indicated. In fig. 3, the substrate is a Glass (Glass) substrate, the counter stress layer is a silicon nitride (SiN) layer, and a metal layer (e.g., cu film) is disposed over the counter stress layer.

In the related art, in order to reduce warpage of a substrate, stress matching is required for the substrate. As shown in fig. 3, a counter stress layer is provided between a base substrate 11 such as a glass substrate and a copper layer, and the stress generated by the counter stress layer is opposite to the stress generated by the copper layer. For example, the copper layer generates upward warping stress, and the opposite stress layer generates downward warping stress, so that the stress generated by the opposite stress layer can compensate the stress generated by the copper layer, thereby realizing the purpose of reducing the warping of the substrate. Illustratively, the material of the counter stress layer may include silicon nitride (SiN).

In the related art, the warpage of the substrate affects the process, and when the warpage of the substrate is too large (for example, greater than 0.15 mm), the die bonding cannot be performed normally. The substrate is warped too much, so that stress concentration is generated on the substrate, the flatness of the substrate is affected, and the problem of gold transformation unfilled corner occurs.

The Mini LED product has high risk unfilled corner in the gold melting process, and the yield and reliability of the product are seriously affected. Fig. 4 is an enlarged schematic view of a microscope for the positions of pads in a wiring substrate. As shown in fig. 4, in the substrate process, the copper layer (Cu 2) is a patterned film layer, for example, for the connection end, the cross section of the copper layer is trapezoidal in a plane perpendicular to the substrate, and since the passivation layer (PVX 1-2) is disposed on the side of the copper layer close to the substrate and the passivation stacks (PVX 2-1 and PVX 2-2) are disposed on the side of the copper layer far from the substrate, the passivation layer (PVX 1-2) and the passivation stacks (PVX 2-1 and PVX 2-2) are overlapped with each other in the area where the copper layer is not present, so that stress abrupt points are formed therein, and microcracks (as dotted circles in fig. 4) are very likely to occur in the passivation layer.

The gold-plating process includes an activation reaction, a nickel-plating reaction and electroless gold plating. In the activation reaction, palladium (Pd) ions in the first liquid medicine and a copper layer of a surface exposed area (namely a bonding pad) of the connecting end perform displacement reaction, namely a layer of palladium is formed on the surface of the bonding pad; in the nickel melting reaction, palladium and nickel in the second liquid medicine undergo a displacement reaction, and a nickel layer is further formed above the palladium layer; in the electroless gold plating process, the nickel and gold in the third liquid medicine undergo a displacement reaction, and a gold layer grows on the surface of the nickel layer.

When the passivation lamination has microcracks, a part of palladium ions in the liquid medicine enter the microcracks and perform displacement reaction with copper in the activation reaction, so that the concentration of the palladium ions in the liquid medicine is reduced, and therefore, the concentration of the palladium ions performing displacement reaction with copper at the bonding pad is reduced, and particularly, the concentration of the palladium ions is lower at the position, close to the microcracks, of the bonding pad. Furthermore, in the subsequent nickel (Ni) -gold (Au) process, the nickel-gold layer of the bonding pad close to the microcrack position is thinner and even cannot grow, and finally becomes a defect of a corner defect of the gold-melting layer.

Fig. 5 is a schematic cross-sectional view of A-A in the wiring substrate shown in fig. 1C in an embodiment of the present disclosure, and in one embodiment, as shown in fig. 5, the wiring substrate includes a substrate 11, a buffer layer PVX0, a first metal layer, a first passivation layer PVX1-1, a first organic layer OC1, a second passivation layer PVX1-2, a second metal layer, a third passivation layer PVX2-1, a second organic layer OC2, and a fourth passivation layer PVX2-2.

Illustratively, the buffer layer PVX0 may also be referred to as a counter stress layer, the buffer layer PVX0 being located on one side of the substrate base 11. The first metal layer is located on the side of the buffer layer PVX0 facing away from the substrate base plate 11. The first metal layer includes a plurality of first metal traces 13, and the ratio of the thickness of the first metal layer to the thickness of the buffer layer PVX0 ranges from 5 to 6.7 (inclusive). The plurality of first metal traces 13 may include first metal traces 13 for transmitting different signals, e.g., first metal trace 13a may be used for transmitting a first signal and first metal trace 13b may be used for transmitting a second signal. The widths of the first metal traces 13 transmitting different signals may be different, and thus, there are first metal traces 13 of different widths in the wiring substrate.

The first passivation layer PVX1-1 is located on the side of the first metal layer facing away from the substrate base plate 11. The first organic layer OC1 is located on a side of the first passivation layer PVX1-1 facing away from the substrate 11, the first organic layer OC1 being provided with a first via 21, and an orthographic projection of the first via 21 on the substrate 11 at least partially overlaps an orthographic projection of the first metal trace 13 on the substrate 11.

The second passivation layer PVX1-2 is located at a side of the first organic layer OC1 facing away from the substrate base plate 11. The second passivation layer PVX1-2 is provided with a second via 22 penetrating the second passivation layer PVX1-2 and the first passivation layer PVX 1-1. The second via hole 22 exposes a portion of the surface of the first metal trace 13. Illustratively, the orthographic projection of the second via 22 on the substrate 11 and the orthographic projection of the first via 21 on the substrate 11 have a first overlapping region, which exposes a portion of the surface of the first metal trace 13.

The second metal layer is located on the side of the second passivation layer PVX1-2 facing away from the substrate base plate 11. The second metal layer includes a plurality of connection terminals 161 and a plurality of connection lines 162, and at least one connection terminal 161 is connected to the exposed surface of the first metal trace 13 through the connection line 162.

The third passivation layer PVX2-1 is located on the side of the second metal layer facing away from the substrate base plate 11. The second organic layer OC2 is located at a side of the third passivation layer PVX2-1 facing away from the substrate base plate 11. The second organic layer OC2 is provided with a third via 23, and the orthographic projection of the connection terminal 161 on the substrate 11 is located within the range of the orthographic projection of the third via 23 on the substrate 11.

The fourth passivation layer PVX2-2 is located on the side of the second organic layer OC2 facing away from the substrate base plate 11. The fourth passivation layer PVX2-2 is provided with a fourth via 24. The fourth via 24 exposes at least a portion of the surface of the connection terminal. Illustratively, at least a portion of the orthographic projection of the fourth via 24 onto the substrate 11 is within the orthographic projection of the third via 23 onto the substrate 11. The fourth via 24 penetrates the fourth passivation layer PVX2-2 and the third passivation layer PVX2-1 to expose at least a portion of the surface of the connection terminal 161.

According to the wiring substrate disclosed by the embodiment of the invention, the buffer layer PVX0 can generate stress opposite to the first metal layer, the buffer layer PVX0 generates compressive stress on the substrate, the first metal layer generates tensile stress on the substrate, the ratio range of the thickness of the first metal layer to the thickness of the buffer layer PVX0 is set to be 5-7, so that the compressive stress generated by the buffer layer PVX0 can better compensate the tensile stress generated by the first metal layer, the warping of the substrate is better reduced, the flatness of the wiring substrate is improved, the stress mutation of the wiring substrate is reduced, the stress mutation of the connecting end 161 is avoided, the microcrack generated by the passivation layer is avoided, the problem of the gold melting unfilled corner in the subsequent gold melting process is improved, the product yield is improved, and the product reliability is improved.

Illustratively, the orthographic projection of the fourth via 24 onto the substrate 11 is within the orthographic projection of the third via 23 onto the substrate 11. In the embodiment of the disclosure, the orthographic projection of the connection end 161 on the substrate 11 is located within the orthographic projection range of the third via 23 on the substrate 11, and the orthographic projection of the fourth via 24 on the substrate 11 is located within the orthographic projection range of the third via 23 on the substrate 11, which is beneficial to improving the surface area of the connection end 161 exposed by the fourth via 24, so that the area of the Ni-Au layer can be increased and the die bonding yield can be improved in the subsequent gold plating process.

In one embodiment, as shown in fig. 5, the third via 23 corresponds to the connection terminals 161, that is, one connection terminal 161 is provided with a third via 23, and a portion of the second organic layer OC2 remains between the adjacent connection terminal 161a and the adjacent connection terminal 161b coupled to the same electronic component.

Fig. 6 is a schematic cross-sectional view of A-A in the wiring substrate shown in fig. 1C in another embodiment of the present disclosure. In one embodiment, as shown in fig. 6, the plurality of connection terminals coupled to the same electronic component corresponds to one third via 23, or, the plurality of connection terminals in one pad group corresponds to one third via 23, or, the orthographic projection of the plurality of connection terminals coupled to the same electronic component on the substrate is located within the orthographic projection range of the same third via 23 on the substrate, or, the orthographic projection of the plurality of connection terminals in one pad group on the substrate is located within the range of the same third via 23. Thus, there is no second organic layer OC2 between adjacent connection terminals coupled with the same electronic component.

Illustratively, the ratio of the thickness of the first metal layer to the thickness of the buffer layer PVX0 ranges from 5 to 7 (inclusive). Illustratively, the ratio of the thickness of the first metal layer to the thickness of the buffer layer PVX0 may be any one of 5 to 7. For example, the ratio of the thickness of the first metal layer to the thickness of the buffer layer PVX0 may be 5, 5.4, 6, 6.7, or 7.

In one embodiment, the material of the buffer layer PVX0 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Illustratively, the material of the buffer layer PVX0 may include silicon nitride, for example, the material of the buffer layer PVX0 is silicon nitride.

In one embodiment, the thickness of the first metal trace 13 ranges from 2.5 μm to 3 μm (inclusive). Illustratively, the thickness of the first metal trace 13 may be any value from 2.5 μm to 3 μm, for example, the thickness of the first metal trace 13 may be 2.5 μm, 2.76 μm, or 3 μm.

In one embodiment, the material of the first metal trace 13 may include copper. The first metal trace 13 may include a first molybdenum-niobium alloy layer (MoNb), a copper layer, and a second molybdenum-niobium alloy layer, which are sequentially stacked. That is, the first metal trace 13 may have a stacked structure of Monb/Cu/Monb. When the first metal wirings 13 are of a stacked structure of MoNb/Cu/MoNb, the thickness of the MoNb layers may be 300 a m, the thickness of the Cu layers may be 2.7 μm, and the thickness of the first metal wirings 13 may be expressed as 300/27000/300 a m, for example.

In one embodiment, the thickness of the buffer layer PVX0 may range from 3500 to 5500 Emeter. Illustratively, the thickness of the buffer layer PVX0 may be any value from 3500 to 5500 angstroms. For example, the thickness of the buffer layer PVX0 may be 3500, 4000, 4500, 5000, or 5500 meter.

The thickness range of the buffer layer PVX0 is 3500-5500 microns, the thickness of the first metal wire 13 is 2.5-3 microns, the compressive stress generated by the buffer layer PVX0 can better compensate the tensile stress generated by the first metal layer, the warping amount of the substrate is better reduced, the flatness of the wiring substrate is improved, the stress mutation of the wiring substrate is reduced, the problem of the gold-melting unfilled corner in the subsequent gold-melting process is favorably improved, the product yield is improved, and the reliability risk is reduced.

In one embodiment, the material of the first passivation layer PVX1-1 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Illustratively, the material of the first passivation layer PVX1-1 may include silicon nitride, for example, the material of the first passivation layer PVX1-1 is silicon nitride.

In one embodiment, the thickness of the first passivation layer PVX1-1 ranges from 2000 to 2800 (inclusive) angstroms. Illustratively, the thickness of the first passivation layer PVX1-1 may be any value from 2000 to 2800 Emi, for example, the thickness of the first passivation layer PVX1-1 may be 2000, 2400 or 2800 Emi.

In one embodiment, the stress of the first passivation layer PVX1-1 is-350 MPa to-450 MPa, for example, the stress of the first passivation layer PVX1-1 is-400 MPa. That is, the compressive stress of the first passivation layer PVX1-1 on the substrate is 350MPa to 450MPa.

The stress of the first passivation layer PVX1-1 is-350 Mpa to-450 Mpa, and the stress can further compensate the tensile stress generated by the first metal layer and the second metal layer, so that the warping amount of the substrate is further reduced, the flatness of the wiring substrate is improved, the product yield is further improved, and the reliability risk is reduced.

In one embodiment, the first passivation layer PVX1-1 may be deposited using a chemical vapor deposition method. In the process of depositing the first passivation layer PVX1-1, the flow rate of the silicon tetrahydride gas is 2500 Sccm-2540 Sccm (inclusive), the flow rate of the ammonia gas is 8800 Sccm-8840 Sccm (inclusive), and the flow rate of the nitrogen gas is 38000 Sccm-40000 Sccm (inclusive). The gap between the substrate and the electrode is 700mils to 900mils (inclusive). Illustratively, the flow rate of the silicon hydride gas is 2520Sccm, the flow rate of the ammonia gas is 8820Sccm, the flow rate of the nitrogen gas is 39000Sccm, and the gap between the substrate and the electrode is 800mils. The stress of the first passivation layer PVX1-1 formed in this way satisfies-350 MPa to-450 MPa.

In one embodiment, the material of the second passivation layer PVX1-2 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Illustratively, the material of the second passivation layer PVX1-2 may include silicon nitride, for example, the material of the second passivation layer PVX1-2 is silicon nitride.

In one embodiment, the thickness of the second passivation layer PVX1-2 ranges from 2000 to 2800 (inclusive) angstroms. Illustratively, the thickness of the second passivation layer PVX1-2 may be any value from 2000 to 2800 Emi, for example, the thickness of the second passivation layer PVX1-2 may be 2000, 2400 or 2800 Emi.

In one embodiment, the stress of the second passivation layer PVX1-2 is-350 MPa to-450 MPa, for example, the stress of the second passivation layer PVX1-2 is-400 MPa. That is, the compressive stress of the second passivation layer PVX1-2 on the substrate is 350Mpa to 450Mpa.

The stress of the second passivation layer PVX1-2 is-350 Mpa to-450 Mpa, and the stress can further compensate the tensile stress generated by the first metal layer and the second metal layer, so that the warping amount of the substrate is further reduced, the flatness of the wiring substrate is improved, the product yield is further improved, and the reliability risk is reduced.

In one embodiment, the second passivation layer PVX1-2 may be deposited using a chemical vapor deposition process. In the process of depositing the second passivation layer PVX1-2, the flow rate of the silicon hydride gas is 2500 Sccm-2540 Sccm (inclusive), the flow rate of the ammonia gas is 8800 Sccm-8840 Sccm (inclusive), and the flow rate of the nitrogen gas is 38000 Sccm-40000 Sccm (inclusive). The gap between the substrate and the electrode is 700mils to 900mils (inclusive). Illustratively, the flow rate of the silicon hydride gas is 2520Sccm, the flow rate of the ammonia gas is 8820Sccm, the flow rate of the nitrogen gas is 39000Sccm, and the gap between the substrate and the electrode is 800mils.

In one embodiment, the material of the third passivation layer PVX2-1 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Illustratively, the material of the third passivation layer PVX2-1 may include silicon nitride, for example, the material of the third passivation layer PVX2-1 is silicon nitride.

In one embodiment, the thickness of the third passivation layer PVX2-1 ranges from 2000 to 2800 (inclusive) angstroms. Illustratively, the thickness of the third passivation layer PVX2-1 may be any value from 2000 to 2800 Emi, for example, the thickness of the third passivation layer PVX2-1 may be 2000, 2400 or 2800 Emi.

In one embodiment, the stress of the third passivation layer PVX2-1 is-350 MPa to-450 MPa, for example, the stress of the third passivation layer PVX2-1 is-400 MPa. That is, the third passivation layer PVX2-1 has a compressive stress of 350MPa to 450MPa on the substrate.

The stress of the third passivation layer PVX2-1 is-350 Mpa to-450 Mpa, and the stress can further compensate the tensile stress generated by the first metal layer and the second metal layer, so that the warping amount of the substrate is further reduced, the flatness of the wiring substrate is improved, the product yield is further improved, and the reliability risk is reduced.

In one embodiment, the third passivation layer PVX2-1 may be deposited using a chemical vapor deposition method. In the process of depositing the third passivation layer PVX2-1, the flow rate of the silicon tetrahydride gas is 2500 Sccm-2540 Sccm (inclusive), the flow rate of the ammonia gas is 8800 Sccm-8840 Sccm (inclusive), and the flow rate of the nitrogen gas is 38000 Sccm-40000 Sccm (inclusive). The gap between the substrate and the electrode is 700mils to 900mils (inclusive). Illustratively, the flow rate of the silicon hydride gas is 2520Sccm, the flow rate of the ammonia gas is 8820Sccm, the flow rate of the nitrogen gas is 39000Sccm, and the gap between the substrate and the electrode is 800mils.

In one embodiment, the material of the fourth passivation layer PVX2-2 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Illustratively, the material of the fourth passivation layer PVX2-2 may include silicon nitride, for example, the material of the fourth passivation layer PVX2-2 is silicon nitride.

In one embodiment, the thickness of the fourth passivation layer PVX2-2 ranges from 2000 to 2800 angstroms (inclusive). Illustratively, the thickness of the fourth passivation layer PVX2-2 may be any value from 2000 to 2800 Emi, for example, the thickness of the fourth passivation layer PVX2-2 may be 2000, 2400 or 2800 Emi.

In one embodiment, the stress of the fourth passivation layer PVX2-2 is-350 MPa to-450 MPa, for example, the stress of the fourth passivation layer PVX2-2 is-400 MPa. That is, the fourth passivation layer PVX2-2 has a compressive stress of 350MPa to 450MPa on the substrate.

The stress of the fourth passivation layer PVX2-2 is-350 Mpa to-450 Mpa, and the stress can further compensate the tensile stress generated by the first metal layer and the second metal layer, so that the warping amount of the substrate is further reduced, the flatness of the wiring substrate is improved, the product yield is further improved, and the reliability risk is reduced.

In one embodiment, the fourth passivation layer PVX2-2 may be deposited using a chemical vapor deposition process. In the process of depositing the fourth passivation layer PVX2-2, the flow rate of the silicon hydride gas is 2500 Sccm-2540 Sccm (inclusive), the flow rate of the ammonia gas is 8800 Sccm-8840 Sccm (inclusive), and the flow rate of the nitrogen gas is 38000 Sccm-40000 Sccm (inclusive). The gap between the substrate and the electrode is 700mils to 900mils (inclusive). Illustratively, the flow rate of the silicon hydride gas is 2520Sccm, the flow rate of the ammonia gas is 8820Sccm, the flow rate of the nitrogen gas is 39000Sccm, and the gap between the substrate and the electrode is 800mils.

In one embodiment, as shown in fig. 5, the orthographic projection of the first via 21 on the substrate 11 is located within the orthographic projection range of the first metal trace 13 on the substrate 11. Illustratively, the orthographic projection of the second via 22 onto the substrate 11 is within the orthographic projection of the first via 21 onto the substrate 11. Thus, the second via hole 22 may expose more surface of the first metal trace 13, and reduce the connection resistance between the connection line 162 and the first metal trace 13.

In one embodiment, the material of the first organic layer OC1 may include an organic material, such as photoresist, polyimide, and the like. The thickness of the first organic layer OC1 may range from 3 μm to 4 μm (inclusive). Illustratively, the thickness of the first organic layer OC1 may be any value from 3 μm to 4 μm. For example, the thickness of the first organic layer OC1 may be 3 μm, 3.5 μm or 4 μm.

In one embodiment, the material of the second organic layer OC2 may include an organic material, such as photoresist, polyimide, and the like. The thickness of the second organic layer OC2 may range from 2 μm to 3 μm (inclusive). The thickness of the second organic layer OC2 may be any value of 2 μm to 3 μm, for example. For example, the thickness of the second organic layer OC2 may be 2 μm, 2.5 μm or 3 μm.

It is understood that the organic material may include an organic resin and a volatilizable solvent. The content of the organic resin in the organic material is 15% -20% (inclusive). The organic resin may include an acrylic monomer. The acrylic monomer may form an acrylic polymer upon curing.

In one embodiment, the thickness of the second metal layer ranges from 0.9 μm to 1 μm (inclusive). Illustratively, the thickness of the second metal layer may be any value from 0.9 μm to 1 μm, for example, the thickness of the second metal layer may be 0.9 μm, 0.95 μm, or 1 μm.

In one embodiment, the material of the second metal layer may include copper. The second metal layer may include a first molybdenum niobium alloy layer (MoNb), a copper layer, and a second molybdenum niobium alloy layer, which are sequentially stacked. That is, the second metal layer may have a stacked structure of Monb/Cu/Monb. When the second metal layer is a stacked structure of MoNb/Cu/MoNb, the thickness of the first molybdenum-niobium alloy layer may be 300 a m, the thickness of the Cu layer may be 9000 a m, and the thickness of the second molybdenum-niobium alloy layer may be 150 a m, wherein the first molybdenum-niobium alloy layer is adjacent to the second passivation layer PVX1-2, for example. The thickness of the second metal layer may be expressed as 300/9000/150 a/m.

In one embodiment, as shown in fig. 5 or 6, the connection terminal 161 has a trapezoidal cross section on a plane perpendicular to the direction of the substrate 11. Orthographic projection of the surface of the connection terminal 161 on the side facing away from the substrate 11 on the substrate 11 is located within an orthographic projection range of the surface of the connection terminal 161 on the side facing toward the substrate 11 on the substrate 11, so that the cross section of the connection terminal 161 is orthotrapezoid, as shown in fig. 5 or 6. The orthographic projection of the surface of the connection terminal 161 on the side facing away from the substrate 11 on the substrate 11 is within the range of the orthographic projection of the fourth via 24 on the substrate 11.

With such a structure, the fourth via hole 24 can completely expose the upper surface of the connection end 161, so that the area of the Ni-Au layer can be further increased and the die bonding yield can be improved in the subsequent gold plating process.

The embodiment of the disclosure also provides a preparation method of the wiring substrate. The method may comprise the steps of:

in step S11, a buffer layer PVX0 is deposited on one side of the substrate base plate 11 using physical vapor deposition (Physical Vapor Deposition, PVD).

In step S12, a first metal layer is formed on a side of the buffer layer PVX0 facing away from the substrate 11, the first metal layer including a plurality of first metal traces 13, and a ratio of a thickness of the first metal layer to a thickness of the buffer layer PVX0 ranges from 5 to 7.

In step S13, a first passivation layer PVX1-1 is formed on a side of the first metal layer facing away from the base substrate 11.

In step S14, a first organic layer OC1 is formed on a side of the first passivation layer PVX1-1 facing away from the substrate 11, the first organic layer OC1 being provided with a first via 21, and an orthographic projection of the first via 21 on the substrate 11 at least partially overlaps an orthographic projection of the first metal trace 13 on the substrate 11.

In step S15, a second passivation layer PVX1-2 is formed on the side of the first organic layer OC1 facing away from the substrate 11, the second passivation layer PVX1-2 is provided with a second via hole 22 penetrating through the second passivation layer PVX1-2 and the first passivation layer PVX1-1, and a first overlapping area exists between the orthographic projection of the second via hole 22 on the substrate 11 and the orthographic projection of the first via hole 21 on the substrate 11, and the first overlapping area exposes a part of the surface of the first metal trace 13.

In step S16, a second metal layer is formed on a side of the second passivation layer PVX1-2 facing away from the substrate 11, the second metal layer including a plurality of connection terminals 161 and a plurality of connection lines 162, at least one connection terminal 161 being connected to an exposed surface of the first metal trace 13 through the connection line 162.

In step S17, a third passivation layer PVX2-1 is formed on the side of the second metal layer facing away from the base substrate 11.

In step S18, a second organic layer OC2 is formed on the side of the third passivation layer PVX2-1 facing away from the substrate 11, the second organic layer OC2 being provided with a third via 23, and the orthographic projection of the connection terminal 161 on the substrate 11 is located within the range of the orthographic projection of the third via 23 on the substrate 11.

In step S19, a fourth passivation layer PVX2-2 is formed on the side of the second organic layer OC2 facing away from the substrate 11, the fourth passivation layer PVX2-2 being provided with a fourth via 24, at least part of the orthographic projection of the fourth via 24 on the substrate 11 being located within the orthographic projection of the third via 23 on the substrate 11, the fourth via 24 penetrating the fourth passivation layer PVX2-2 and the third passivation layer PVX2-1 to expose at least part of the surface of the connection terminal 161.

In one embodiment, the first passivation layer PVX1-1 is deposited by chemical vapor deposition (ChemicalVaporDeposition, CVD). During the deposition, the flow rate of the silicon hydride gas is 2500Sccm to 2540Sccm (inclusive), the flow rate of the ammonia gas is 8800Sccm to 8840Sccm (inclusive), and the flow rate of the nitrogen gas is 38000Sccm to 40000Sccm (inclusive). The gap between the substrate and the electrode is 700mils to 900mils (inclusive). Illustratively, the flow rate of the silicon hydride gas is 2520Sccm, the flow rate of the ammonia gas is 8820Sccm, the flow rate of the nitrogen gas is 39000Sccm, and the gap between the substrate and the electrode is 800mils.

In one embodiment, the second passivation layer PVX1-2 is deposited by chemical vapor deposition. During the deposition, the flow rate of the silicon hydride gas is 2500Sccm to 2540Sccm (inclusive), the flow rate of the ammonia gas is 8800Sccm to 8840Sccm (inclusive), and the flow rate of the nitrogen gas is 38000Sccm to 40000Sccm (inclusive). The gap between the substrate and the electrode is 700mils to 900mils (inclusive). Illustratively, the flow rate of the silicon hydride gas is 2520Sccm, the flow rate of the ammonia gas is 8820Sccm, the flow rate of the nitrogen gas is 39000Sccm, and the gap between the substrate and the electrode is 800mils.

In one embodiment, the third passivation layer PVX2-1 is deposited by chemical vapor deposition. During the deposition, the flow rate of the silicon hydride gas is 2500Sccm to 2540Sccm (inclusive), the flow rate of the ammonia gas is 8800Sccm to 8840Sccm (inclusive), and the flow rate of the nitrogen gas is 38000Sccm to 40000Sccm (inclusive). The gap between the substrate and the electrode is 700mils to 900mils (inclusive). Illustratively, the flow rate of the silicon hydride gas is 2520Sccm, the flow rate of the ammonia gas is 8820Sccm, the flow rate of the nitrogen gas is 39000Sccm, and the gap between the substrate and the electrode is 800mils.

In one embodiment, the fourth passivation layer PVX2-2 is deposited by chemical vapor deposition. During the deposition, the flow rate of the silicon hydride gas is 2500Sccm to 2540Sccm (inclusive), the flow rate of the ammonia gas is 8800Sccm to 8840Sccm (inclusive), and the flow rate of the nitrogen gas is 38000Sccm to 40000Sccm (inclusive). The gap between the substrate and the electrode is 700mils to 900mils (inclusive). Illustratively, the flow rate of the silicon hydride gas is 2520Sccm, the flow rate of the ammonia gas is 8820Sccm, the flow rate of the nitrogen gas is 39000Sccm, and the gap between the substrate and the electrode is 800mils.

In one embodiment, the curing temperature of the first organic layer OC1 is 200-250℃and the curing time is 55-65 minutes.

In one embodiment, the second organic layer OC2 has a cure temperature of 200℃to 250℃and a cure time of 55 minutes to 65 minutes.

The technical solution of the embodiments of the present disclosure is further described below through a process of manufacturing a wiring substrate shown in fig. 5. It should be understood that, as used herein, the term "patterning" includes processes such as photoresist coating, mask exposure, development, etching, photoresist stripping, etc. when the patterned material is inorganic or metal, and processes such as mask exposure, development, etc. when the patterned material is organic, evaporation, deposition, coating, etc. are all well-known processes in the related art.

In step S11, a buffer layer PVX0 is deposited on one side of the substrate 11 by physical vapor deposition, as shown in fig. 7A, fig. 7A is a schematic cross-sectional view of the wiring substrate after forming a first via hole according to an embodiment of the present disclosure. Illustratively, the material of the buffer layer PVX0 is silicon nitride. Illustratively, the thickness of the buffer layer PVX0 is 5000 angstroms.

In step S12, a first metal layer is formed on the side of the buffer layer PVX0 facing away from the substrate 11, where the first metal layer includes a plurality of first metal traces 13, and the ratio of the thickness of the first metal layer to the thickness of the buffer layer PVX0 ranges from 5 to 7, as shown in fig. 7A. Illustratively, a first metal thin film may be deposited on a side of the buffer layer PVX0 facing away from the substrate base plate 11; the first metal film is patterned to form a plurality of first metal traces 13. The first metal tracks 13 are illustratively a stacked structure of Monb/Cu/Monb, wherein the thickness of the Monb layers may each be 300 a, and the thickness of the Cu layers may be 2.7 μm.

In step S13, a first passivation layer PVX1-1 is formed on a side of the first metal layer facing away from the base substrate 11, as shown in fig. 7A. For example, the first passivation layer PVX1-1 may be deposited by chemical vapor deposition, in which the flow rate of the silicon hydride gas is 2500Sccm to 2540Sccm (inclusive), the flow rate of the ammonia gas is 8800Sccm to 8840Sccm (inclusive), and the flow rate of the nitrogen gas is 38000Sccm to 40000Sccm (inclusive). The gap between the substrate and the electrode is 700mils to 900mils (inclusive). Illustratively, the flow rate of the silicon hydride gas is 2520Sccm, the flow rate of the ammonia gas is 8820Sccm, the flow rate of the nitrogen gas is 39000Sccm, and the gap between the substrate and the electrode is 800mils. Illustratively, the material of the first passivation layer PVX1-1 is silicon nitride. The first passivation layer PVX1-1 has a thickness of 2400A. The stress of the first passivation layer PVX1-1 formed in the embodiment of the disclosure is-400 Mpa, so that the tensile stress generated by the first metal layer can be further compensated, the warping amount of the substrate is further reduced, the flatness of the wiring substrate is improved, the product yield is further improved, and the reliability risk is reduced.

In step S14, a first organic layer OC1 is formed on a side of the first passivation layer PVX1-1 facing away from the substrate base plate 11. The first organic layer OC1 is provided with a first via 21, and the orthographic projection of the first via 21 on the substrate 11 overlaps with the orthographic projection portion of the first metal trace 13 on the substrate 11, as shown in fig. 7A. In this embodiment, the orthographic projection of the first via 21 on the substrate 11 is within the range of the orthographic projection of the first metal trace 13 on the substrate 11. Illustratively, a first organic material may be coated on a side of the first passivation layer PVX1-1 facing away from the substrate base plate 11; curing the first organic material through a curing process to form a first organic layer OC1; removing the first organic layer OC1 at the position of the first via hole 21 by exposure and development to form the first via hole 21; the first organic layer OC1 is post-baked.

Illustratively, the first organic material is a solution comprising an organic resin. The first organic material may comprise an organic resin and a volatilizable solvent. The content of the organic resin in the first organic material is 15% -20% (inclusive). The organic resin may include an acrylic monomer. The acrylic monomer may form an acrylic polymer upon curing.

In one embodiment, the curing temperature is 200 ℃ to 260 ℃ during the curing process. Illustratively, the curing temperature may be 200 ℃, 230 ℃, 250 ℃, or 260 ℃. The curing time is 55 minutes to 65 minutes, and may be 55 minutes, 60 minutes, or 65 minutes, for example. In the presently disclosed embodiments, the curing temperature is about 250 ℃ and the curing time is about 60 minutes. The thickness of the first organic layer OC1 was 3.5 μm.

Setting the curing temperature to be 200-260 ℃ and the curing time to be 55-65 minutes can enable the gas in the first organic layer OC1 to be more fully released, and prevent the stress mutation caused by the release of the gas in the subsequent process of the first organic layer OC1

In step S15, a second passivation layer PVX1-2 is formed on the side of the first organic layer OC1 facing away from the substrate base plate 11. The second passivation layer PVX1-2 is provided with a second via hole 22 penetrating through the second passivation layer PVX1-2 and the first passivation layer PVX1-1, and a first overlapping area exists between the orthographic projection of the second via hole 22 on the substrate 11 and the orthographic projection of the first via hole 21 on the substrate 11, and the first overlapping area exposes a part of the surface of the first metal trace 13, as shown in fig. 7B, fig. 7B is a schematic cross-sectional view after forming the second via hole in the wiring substrate according to an embodiment of the disclosure.

Illustratively, the second passivation layer PVX1-2 may be deposited by chemical vapor deposition on the side of the first organic layer OC1 facing away from the substrate base plate 11; the second passivation layer PVX1-2 is patterned, and the second passivation layer PVX1-2 and the first passivation layer PVX1-1 at the position of the second via hole 22 are removed to form the second via hole 22. The orthographic projection of the second via 22 on the substrate 11 is within the orthographic projection range of the first via 21 on the substrate 11. The second via hole 22 exposes a portion of the surface of the first metal trace 13.

During the deposition, the flow rate of the silicon hydride gas is 2500Sccm to 2540Sccm (inclusive), the flow rate of the ammonia gas is 8800Sccm to 8840Sccm (inclusive), and the flow rate of the nitrogen gas is 38000Sccm to 40000Sccm (inclusive). The gap between the substrate and the electrode is 700mils to 900mils (inclusive). Illustratively, the flow rate of the silicon hydride gas is 2520Sccm, the flow rate of the ammonia gas is 8820Sccm, the flow rate of the nitrogen gas is 39000Sccm, and the gap between the substrate and the electrode is 800mils.

The material of the second passivation layer PVX1-2 is silicon nitride. The second passivation layer PVX1-2 has a thickness of 2400A. The stress of the second passivation layer PVX1-2 formed in the embodiment of the disclosure is-400 Mpa, so that the tensile stress generated by the first metal layer can be further compensated, the warping amount of the substrate is further reduced, the flatness of the wiring substrate is improved, the product yield is further improved, and the reliability risk is reduced.

In step S16, a second metal layer is formed on a side of the second passivation layer PVX1-2 facing away from the substrate 11, where the second metal layer includes a plurality of connection terminals 161 and a plurality of connection lines 162, at least one connection terminal 161 is connected to an exposed surface of the first metal trace 13 through the connection line 162, as shown in fig. 7C and fig. 7D, fig. 7C is a schematic cross-sectional view after forming a third via in the wiring substrate according to an embodiment of the present disclosure, and fig. 7D is a schematic cross-sectional view after forming the third via in the wiring substrate shown in fig. 6.

Illustratively, a second metal thin film may be deposited on a side of the second passivation layer PVX1-2 facing away from the substrate base plate 11; the second metal film is patterned to form a second metal layer including a plurality of connection terminals 161 and a plurality of connection lines 162. Illustratively, the second metal trace is a stacked structure of Monb/Cu/Monb, the second metal trace has a thickness of about 300 a/9000 a/150 a, and the Monb layer adjacent to the second passivation layer PVX1-2 has a thickness of about 300 a.

In view of the process of the second metal layer, the connection terminal 161 is formed to have a trapezoid cross section on a plane perpendicular to the direction of the substrate 11. Orthographic projection of the surface of the connection terminal 161 on the side facing away from the substrate 11 on the substrate 11 is located within an orthographic projection range of the surface of the connection terminal 161 on the side facing toward the substrate 11 on the substrate 11, and thus, the cross section of the connection terminal 161 is a regular trapezoid, as shown in fig. 7C and 7D.

In step S17, a third passivation layer PVX2-1 is formed on the side of the second metal layer facing away from the substrate base plate 11, as shown in fig. 7C and 7D. For example, the third passivation layer PVX2-1 may be deposited by chemical vapor deposition, in which the flow rate of the silicon hydride gas is 2500Sccm to 2540Sccm (inclusive), the flow rate of the ammonia gas is 8800Sccm to 8840Sccm (inclusive), and the flow rate of the nitrogen gas is 38000Sccm to 40000Sccm (inclusive). The gap between the substrate and the electrode is 700mils to 900mils (inclusive). Illustratively, the flow rate of the silicon hydride gas is 2520Sccm, the flow rate of the ammonia gas is 8820Sccm, the flow rate of the nitrogen gas is 39000Sccm, and the gap between the substrate and the electrode is 800mils.

The third passivation layer PVX2-1 is illustratively silicon nitride. The third passivation layer PVX2-1 has a thickness of 2400A. The stress of the third passivation layer PVX2-1 formed in the embodiment of the disclosure is-400 Mpa, so that the tensile stress generated by the first metal layer can be further compensated, the warping amount of the substrate is further reduced, the flatness of the wiring substrate is improved, the product yield is further improved, and the reliability risk is reduced.

In step S18, a second organic layer OC2 is formed on the side of the third passivation layer PVX2-1 facing away from the substrate 11, the second organic layer OC2 being provided with a third via 23, and the orthographic projection of the connection terminal 161 on the substrate 11 is located within the range of the orthographic projection of the third via 23 on the substrate 11, as shown in fig. 7C and 7D.

In this embodiment, the orthographic projection of the connection terminal 161 on the substrate 11 is within the range of the orthographic projection of the third via 23 on the substrate 11, as shown in fig. 7C and 7D.

By way of example, a second organic material may be applied to the side of the first passivation layer PVX1-1 facing away from the substrate base plate 11; curing the second organic material through a curing process to form a second organic layer OC2; removing the second organic layer OC2 at the position of the third via hole 23 by exposure and development to form the third via hole 23; the second organic layer OC2 is post-baked.

Illustratively, the second organic material is a solution comprising an organic resin. The second organic material may comprise an organic resin and a volatilizable solvent. In the second organic material, the content of the organic resin is 15% -20% (inclusive). The organic resin may include an acrylic monomer. The acrylic monomer may form an acrylic polymer upon curing.

In one embodiment, the curing temperature is 200 ℃ to 260 ℃ during the curing process. Illustratively, the curing temperature may be 200 ℃, 230 ℃, 250 ℃, or 260 ℃. The curing time is 55 minutes to 65 minutes, and may be 55 minutes, 60 minutes, or 65 minutes, for example. In the presently disclosed embodiment, the curing temperature is about 230 ℃ and the curing time is about 60 minutes. The thickness of the second organic layer OC2 was 2.5 μm.

Setting the curing temperature to 200-260 ℃ and the curing time to 55-65 minutes can enable the gas in the second organic layer OC2 to be released more fully, and prevent the first organic layer OC1 from releasing the gas in the subsequent process to cause stress mutation.

In step S19, a fourth passivation layer PVX2-2 is formed on the side of the second organic layer OC2 facing away from the substrate base plate 11. The fourth passivation layer PVX2-2 is provided with a fourth via 24, the orthographic projection of the fourth via 24 on the substrate 11 is within the range of the orthographic projection of the third via 23 on the substrate 11, the fourth via 24 penetrates the fourth passivation layer PVX2-2 and the third passivation layer PVX2-1, and the fourth via 24 exposes at least a part of the surface of the connection terminal 161.

Illustratively, the orthographic projection of the upper surface of the connection terminal 161 on the substrate 11 is within the range of the orthographic projection of the fourth via 24 on the substrate 11, so that the fourth via 24 may expose the upper surface of the connection terminal 161, as shown in fig. 5 and 6.

In one embodiment, the method of manufacturing a wiring substrate may further include performing a gold plating process at the pad position.

In the related art, as shown in fig. 4, referring to fig. 5 and 6, a plurality of passivation layers are stacked at a climbing position of the connection end 161, that is, at a side position of the connection end 161, so that the overall thickness of the passivation film is changed, a strain abrupt change is generated at the climbing position of the connection end 161, and a region where the strain abrupt change is generated in the related art is marked in fig. 5 and 6 by a virtual coil, resulting in the occurrence of microcracks in the passivation layer. During the gold formation, when copper (Cu) is exchanged with palladium (Pd), the palladium concentration changes at the cracks, resulting in insufficient activation. Furthermore, in the subsequent nickel (Ni) -gold (Au) process, nickel cannot grow normally at the crack position, so that the thickness of the Ni-Au layer at the crack position is thinner or even no Ni-Au layer exists, and finally the defect of the gold melting layer is shown.

The thickness of the buffer layer PVX0 is set to 3500-5500 meter, and the buffer layer PVX0 is formed by adopting a physical vapor deposition mode; the thicknesses of the first passivation layer PVX1-1, the second passivation layer PVX1-2, the third passivation layer PVX2-1 and the fourth passivation layer PVX2-2 and the gas flow in chemical vapor deposition are set so that the stress of the first passivation layer PVX1-1, the second passivation layer PVX1-2, the third passivation layer PVX2-1 and the fourth passivation layer PVX2-2 on the substrate is about-400 Mpa; and the curing time of the first organic layer OC1 and the second organic layer OC2 was prolonged to about 60 minutes. The wiring substrate greatly reduces the warping of the wiring substrate, reduces the warping amount of the wiring substrate to below 0.05mm, improves the flatness of the wiring substrate, reduces the stress abrupt change of the wiring substrate, avoids the stress abrupt change of the climbing position of the connecting end 161, improves the problem of gold melting unfilled corners in the gold melting process, greatly improves the product yield and improves the product reliability.

Herein, the English of the Buffer layer is Buffer, and PVX1 comprises PVX1-1 and PVX1-2; PVX2 includes PVX2-1 and PVX2-2; a first metal layer Cu1, a second metal layer Cu2.

Fig. 8A is a graph of test results of the influence of PVX2 variation on warpage and unfilled corners of a wiring substrate. In FIG. 8A, PVX0 has a thickness of 2400 angstroms; PVX1-1 has a thickness of 2400 Emi and a stress of +50MPa; PVX1-2 has a thickness of 3000 a.m and a stress of +50MPa. The condition represented by A1 is that the thickness of PVX2-1 and PVX2-2 is 2400 Emi, and the stress is +50Mpa; b1 is represented by PVX2-1 and PVX2-2, wherein the thickness of each PVX2-1 and PVX2-2 is 4000 Emi, and the stress is +50Mpa; c1 represents the condition that the thickness of PVX2-1 and PVX2-2 is 4000 Emi and the stress is-400 Mpa. Curve 1 is a warp curve of the wiring substrate, and curve 2 is a unfilled corner defective rate curve.

Fig. 8B is a graph of test results of the effect of the curing of the organic layer on warpage and unfilled corners of the wiring substrate. In FIG. 8B, PVX0 has a thickness of 5000 angstroms; the stress of PVX1 is-400 Mpa; PVX2 stress is-400 MPa. The conditions represented by D were a cure temperature of OC1 of 250℃and a cure time of 30 minutes, a cure temperature of OC2 of 230℃and a cure time of 30 minutes. E represents the condition that the curing temperature of OC1 is 230 ℃, the curing time is 60 minutes, the curing temperature of OC2 is 200 ℃, and the curing time is 60 minutes. Curve 3 is a warp curve of the wiring substrate, and curve 4 is a unfilled corner defective rate curve.

Fig. 8C is a graph of test results of the influence of the thickness of the buffer layer PVX0 on warpage and unfilled corners of the wiring substrate. In FIG. 8C, the PVX1 stress is +50MPa; PVX2 stress is +50MPa. F represents conditions that the thicknesses of the buffer layers PVX0 are 2400 Emi, and G represents conditions that the thicknesses of the buffer layers PVX0 are 5000 Emi. Curve 5 is a warp curve of the wiring substrate, and curve 6 is a unfilled corner defective rate curve.

Fig. 8D is a graph of test results of the influence of PVX1 variation on warpage and unfilled corners of the wiring substrate. In fig. 8D, PVX0 has a thickness of 2400 a/m; PVX2-1 has a thickness of 1500 Emi and a stress of-400 MPa; PVX2-2 has a thickness of 4000 Emi and a stress of-400 MPa. The condition represented by A2 is that the stress of PVX1-1 and PVX1-2 is +50Mpa; b2 is represented by PVX1-1 stress of +50Mpa and PVX1-2 stress of-400 Mpa; the conditions represented by C2 are that the stress of PVX1-1 and PVX1-2 is-400 Mpa. Curve 7 is a warp curve of the wiring substrate, and curve 8 is a unfilled corner defective rate curve.

Through the test, when PVX2-1 and PVX2-2 are positive stresses, PVX2-2 and PVX0 are thickened in thickness, which reduces warpage of the wiring substrate, as shown in FIGS. 8A to 8D. When PVX2-1 and PVX2-2 are positive stresses, changing the curing temperatures and times of OC1 and OC2 has less influence on warpage of the wiring substrate. When PVX2-1 and PVX2-2 are negative stresses, the stress of PVX2-1 and PVX2-2 is adjusted from +50Mpa to-400 Mpa, so that the warping of the substrate is reduced to less than 0.05mm; when the thickness of the buffer layer PVX0 is 2400 Emi, PVX1-2 can be adjusted to a negative stress, and warpage of the substrate can be reduced to less than 0.05mm.

Through the test, in connection with fig. 8A to 8D, the smaller the warpage of the wiring substrate is, the incidence of unfilled corner failure or the number of unfilled corners is reduced accordingly. Under the condition of the same warping level, the thickness of PVX0 is about 5000 Emi, PVX1 and PVX2 are all negative stresses, meanwhile OC1 curing time is prolonged, and the incidence rate of unfilled corners is about 0 when testing 108 substrates.

The inventors of the present invention compared warpage of wiring substrates of different parameters for each film layer, as shown in table 1.

TABLE 1

TABLE 2

The inventors of the present invention examined the distribution of the number of unfilled corners of 108 pieces (pcs) after the gold plating test of each wiring substrate in table 1, as shown in table 2. As can be seen from tables 1 and 2, the number of wiring boards with the unfilled corner number of 0 using the wiring board of the scheme of 1.3 was 108, that is, the unfilled corner number of each of the 108 wiring boards was 0. The number of wiring boards with the unfilled corner number of 0 was 10 pieces, that is, the unfilled corner number of each of the 10 pieces of wiring boards was 0; the number of wiring boards having a number of unfilled corners of 1 to 5 is 2, that is, the number of unfilled corners of each of the 2 wiring boards is1 to 5. As can be seen from the comparison in Table 2, the wiring substrate adopting the technical scheme of the embodiment of the disclosure greatly improves the problem of gold transformation unfilled corner in the gold transformation process and improves the product yield.

The embodiment of the disclosure further provides a light-emitting panel, which may include the wiring substrate in any embodiment of the disclosure, and further includes a light-emitting diode chip, where the light-emitting diode chip is connected with the corresponding first metal wire. The light emitting panel may be a transparent light emitting panel.

The embodiments of the present disclosure also provide a display device including the light emitting panel in any one of the embodiments of the present disclosure. The display device may be a transparent display device.

The light emitting panel in the embodiment of the disclosure may be mounted in a display device as a display panel, or may be mounted in a display device as a light source, and the display device may be: electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, wearable display device, etc.

The luminescent panel in the embodiments of the present disclosure may also be used as a luminescent light source in a lighting product. Based on the inventive concept of the foregoing embodiments, the present disclosure also provides a display device including a display panel employing the foregoing embodiments. The display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

The luminescent panel in the embodiments of the present disclosure may also be used as a luminescent light source in a lighting product.

In the description of the present specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present disclosure.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present disclosure, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; the device can be mechanically connected, electrically connected and communicated; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

In this disclosure, unless expressly stated or limited otherwise, a first feature being "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is less level than the second feature.

The above disclosure provides many different embodiments or examples for implementing different structures of the disclosure. The components and arrangements of specific examples are described above in order to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present disclosure. Furthermore, the present disclosure may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed.

The above is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think of various changes or substitutions within the technical scope of the disclosure, which should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A wiring substrate, comprising:

A substrate base;

a buffer layer located at one side of the substrate base plate;

The first metal layer is positioned on one side of the buffer layer, which is away from the substrate base plate, and comprises a plurality of first metal wires, wherein the ratio of the thickness of the first metal layer to the thickness of the buffer layer is 5-7;

the second metal layer is positioned on one side of the second passivation layer, which is away from the substrate base plate, and comprises a plurality of connecting ends and a plurality of connecting wires, wherein at least one connecting end is connected with the exposed surface of the first metal wire through the connecting wire;

The second organic layer is positioned on one side of the third passivation layer, which is away from the substrate, and is provided with a third via hole, and the orthographic projection of the connecting end on the substrate is positioned in the orthographic projection range of the third via hole on the substrate;

And the fourth passivation layer is positioned on one side of the second organic layer, which is away from the substrate base plate, and is provided with a fourth via hole, and the fourth via hole exposes at least part of the surface of the connecting end.

2. The wiring substrate according to claim 1, wherein a thickness of the first metal wiring ranges from 2.5 μm to 3 μm, and/or a thickness of the buffer layer ranges from 3500 to 5500 μm.

3. The wiring substrate according to claim 1, wherein a thickness of the first passivation layer ranges from 2000 to 2800 a; and/or the thickness of the second passivation layer ranges from 2000 to 2800 angstroms; and/or the thickness of the third passivation layer ranges from 2000 to 2800 angstroms; and/or the thickness of the fourth passivation layer ranges from 2000 to 2800.

4. The wiring substrate according to claim 1, wherein a stress range of the first passivation layer is-350 Mpa to-450 Mpa; and/or the stress range of the second passivation layer is-350 Mpa to-450 Mpa; and/or the stress range of the third passivation layer is-350 Mpa to-450 Mpa; and/or the stress range of the fourth passivation layer is-350 Mpa to-450 Mpa.

5. The wiring substrate according to claim 1, wherein a thickness of the first organic layer ranges from 3 μm to 4 μm; and/or the thickness of the second organic layer ranges from 2 μm to 3 μm.

6. The wiring board according to claim 1, wherein a thickness of the second metal layer is in a range of 0.9 μm to 1 μm.

7. The wiring substrate according to claim 1, wherein a cross section of the connection terminal on a plane perpendicular to the substrate direction is trapezoidal, an orthographic projection of a surface of the connection terminal on a side facing away from the substrate on the substrate is located within an orthographic projection range of a surface of the connection terminal on a side facing toward the substrate on the substrate, and an orthographic projection of a surface of the connection terminal on a side facing away from the substrate on the substrate is located within an orthographic projection range of the fourth via on the substrate.

8. A method for producing a wiring board, comprising:

forming a first passivation layer on one side of the first metal layer, which is away from the substrate base plate;

Forming a second passivation layer on one side of the first organic layer, which is far away from the substrate, wherein the second passivation layer is provided with a second via hole penetrating through the second passivation layer and the first passivation layer, a first overlapping area exists between orthographic projection of the second via hole on the substrate and orthographic projection of the first via hole on the substrate, and part of the surface of the first metal wire is exposed in the first overlapping area;

forming a third passivation layer on one side of the second metal layer, which is away from the substrate base plate;

And forming a fourth passivation layer on one side of the second organic layer, which is far away from the substrate, wherein the fourth passivation layer is provided with a fourth via hole, at least part of the orthographic projection of the fourth via hole on the substrate is positioned in the orthographic projection range of the third via hole on the substrate, and the fourth via hole penetrates through the fourth passivation layer and the third passivation layer to expose at least part of the surface of the connecting end.

9. The method of claim 8, wherein the step of determining the position of the first electrode is performed,

10. The method of claim 8, wherein the step of determining the position of the first electrode is performed,

11. A light-emitting panel comprising the wiring substrate according to any one of claims 1 to 7, and further comprising a light-emitting diode chip, the light-emitting diode chip being correspondingly connected to the first metal wiring.

12. A display device comprising the light-emitting panel according to claim 11.