CN117438303A - Semiconductor structure and preparation method thereof - Google Patents

Abstract

This application provides a semiconductor structure and a preparation method thereof. The preparation method includes: providing an epitaxial structure with a cathode formed on it; forming a dielectric layer on the epitaxial structure and the cathode; and removing part of the dielectric layer and an epitaxial structure of a predetermined thickness corresponding to the part of the dielectric layer to form an interrupted epitaxial structure. An anode groove of the two-dimensional electron gas in the anode groove; an anode is formed on the surface of the anode groove and the surface of the dielectric layer connected to the surface of the anode groove; at least the anode on the top surface of the dielectric layer is removed. The above preparation method of the semiconductor structure can effectively reduce or eliminate the overlap between the anode and the two-dimensional electron gas, thereby reducing or eliminating the parasitic capacitance generated by the overlap between the two, and improving device performance.

Description

Semiconductor structures and preparation methods

Technical field

The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof.

Background technique

Gallium nitride (GaN), as a wide-bandgap semiconductor material, has great electrical performance advantages. The aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterojunction structure has strong spontaneous polarization and piezoelectric properties. The ionization effect will induce a high concentration of two-dimensional electron gas on the GaN side close to the interface. Since the electrons are confined in the potential well and there are very few impurities in this area, the ionized impurity scattering and alloy disorder scattering are relatively small. Small, two-dimensional electron gases have extremely high mobility and electron saturation rates. In addition, due to the inherent wide bandgap properties of GaN materials, its critical breakdown field strength is extremely large, making it suitable for making high-power microwave diodes. Reducing the capacitance of gallium nitride microwave diodes is the main way to improve the operating frequency and efficiency of the device. .

The current lateral gallium nitride microwave diode introduces an etching groove under the anode, so that the heterojunction structure is destroyed, the capacitance in the etching groove area is eliminated, and the device capacitance is greatly reduced, as shown in Figure 1 . However, this method will still introduce some parasitic capacitance, affecting device performance.

Contents of the invention

Based on this, it is necessary to provide an improved semiconductor structure and its preparation method to address the problem of parasitic capacitance of lateral gallium nitride microwave diodes.

In a first aspect, this application provides a method for preparing a semiconductor structure, which method includes:

providing an epitaxial structure with a cathode formed thereon;

forming a dielectric layer on the epitaxial structure and the cathode;

removing a portion of the dielectric layer and an epitaxial structure of a predetermined thickness corresponding to the portion of the dielectric layer to form an anode groove that interrupts the two-dimensional electron gas in the epitaxial structure;

An anode is formed on the surface of the anode groove and the surface of the dielectric layer connected to the surface of the anode groove;

Remove at least the anode on the top surface of the dielectric layer.

The above preparation method of the semiconductor structure can effectively reduce or eliminate the overlap between the anode and the two-dimensional electron gas by removing the anode on the top surface of the dielectric layer, thereby reducing or eliminating the parasitic capacitance generated by the overlap between the two and improving device performance.

In one embodiment, forming a dielectric layer on the epitaxial structure and the cathode includes: forming the dielectric layer on the epitaxial structure and the cathode through a deposition process; wherein, the dielectric layer The deposition thickness is greater than the thickness of the cathode.

In one embodiment, the deposition thickness h of the dielectric layer satisfies 300nm<h≤1000nm; or satisfies 300nm<h≤600nm.

In one embodiment, removing at least the anode on the top surface of the dielectric layer includes: removing the anode higher than the top surface of the dielectric layer through a grinding or polishing process.

In one embodiment, removing at least the anode on the top surface of the dielectric layer includes: removing part of the dielectric layer and part of the anode from top to bottom through a grinding or polishing process, so that the anode is in contact with the two-dimensional electrons. The orthographic projection of the plane where the gas is located has no overlap with the two-dimensional electron gas.

In one embodiment, forming an anode on the surface of the anode groove and the surface of the dielectric layer connected to the surface of the anode groove includes: forming a pattern on the dielectric layer and the epitaxial structure a photoresist layer; forming an anode metal layer on the dielectric layer, the epitaxial structure and the patterned photoresist layer through a deposition process; removing the patterned photoresist layer and the pattern through a stripping process The anode metal layer on the photoresist layer is retained, and the anode metal layer on the dielectric layer and the epitaxial structure is retained to form the anode.

In one embodiment, after at least removing the anode on the top surface of the dielectric layer, the method further includes: etching the dielectric layer on the cathode to expose at least part of the top surface of the cathode to the air.

In a second aspect, the present application also provides a semiconductor structure, which includes: an epitaxial structure and a cathode and an anode provided on the epitaxial structure;

Wherein, the epitaxial structure is provided with a groove, at least part of the anode is provided in the groove, and the groove interrupts the two-dimensional electron gas in the epitaxial structure;

Wherein, the orthographic projection of the anode on the plane where the two-dimensional electron gas is located has no overlap with the two-dimensional electron gas.

In the above semiconductor structure, since the orthographic projection of the anode on the plane of the two-dimensional electron gas does not overlap with the two-dimensional electron gas, it can effectively reduce or eliminate the overlap between the anode and the two-dimensional electron gas, thereby reducing or eliminating the overlap between the two. The parasitic capacitance generated improves device performance.

In one embodiment, a dielectric layer is provided between the anode and the cathode.

In one embodiment, the anode includes a first metal layer and a second metal layer that are stacked along the thickness direction of the epitaxial structure, and the first metal layer is located between the epitaxial structure and the second metal layer. Wherein, the material of the first metal layer is a low work function metal, the thickness of the first metal layer ranges from 30 nm to 400 nm, and the thickness of the second metal layer is less than or equal to 400 nm.

Description of the drawings

In order to more clearly explain the embodiments of this specification or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only These are some of the embodiments described in this specification. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting any creative effort.

Figure 1 is a schematic structural diagram of an existing gallium nitride microwave diode;

Figure 2 is a step flow chart of a preparation method according to an embodiment of the present application;

Figure 3 shows a schematic diagram of the epitaxial structure in the preparation method according to an embodiment of the present application;

Figure 4 shows a schematic structural diagram of a cathode formed in a preparation method according to an embodiment of the present application;

Figure 5 shows a schematic structural diagram of device isolation formed in a preparation method according to an embodiment of the present application;

Figure 6 shows a schematic structural diagram of a dielectric layer formed in a preparation method according to an embodiment of the present application;

Figure 7 shows a schematic structural diagram of forming an anode groove in a preparation method according to an embodiment of the present application;

Figure 8 shows a schematic structural diagram of an anode formed in a preparation method according to an embodiment of the present application;

Figure 9 shows a schematic structural diagram of removing the anode in the preparation method of an embodiment of the present application;

Figure 10 shows a schematic structural diagram of removing the anode in the preparation method of another embodiment of the present application;

Figure 11 shows a schematic structural diagram of removing the anode in the preparation method of another embodiment of the present application;

Figure 12 shows a schematic structural diagram of the dielectric on the cathode after etching in the preparation method according to an embodiment of the present application.

Component label description:

100’, traditional gallium nitride microwave diode, 10’, epitaxial structure, 20’, cathode, 30’, anode;

100. Semiconductor structure, 10. Epitaxial structure, 11. Substrate, 12. Buffer layer, 13. Channel layer, 14. Barrier layer, 20. Cathode, 30. Mesa isolation structure, 40. Dielectric layer, 50. Anode Groove, 60, anode.

Detailed ways

In order to facilitate understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention may be more thorough and complete.

It should be noted that when an element is referred to as being "fixed" to another element, it can be directly on the other element or intervening elements may also be present. When an element is said to be "connected" to another element, it can be directly connected to the other element or there may also be intervening elements present. As used herein, the terms "vertical", "horizontal", "left", "right", "upper", "lower", "front", "rear", "circumferential" and similar expressions are based on the appended The orientations or positional relationships shown in the figures are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have specific orientations, be constructed and operated in specific orientations, and therefore cannot be understood as limiting the present invention. Limitations of Invention.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which the invention belongs. The terminology used herein in the description of the invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The present application provides an improved semiconductor structure that improves device performance (such as the frequency characteristics of the device) by reducing or eliminating the overlap of the anode and the two-dimensional electron gas to reduce or eliminate the parasitic capacitance generated by the overlap of the two.

In one embodiment, as shown in FIG. 12 , the semiconductor structure 100 of the present application includes an epitaxial structure 10 and a cathode 20 and an anode 60 provided on the epitaxial structure 10 . The epitaxial structure 10 includes a substrate 11 and a buffer layer 12, a channel layer 13, and a barrier layer 14 that are sequentially arranged along the thickness direction of the substrate 11, and are close to the interface between the channel layer 13 and the barrier layer 14. A high concentration of two-dimensional electron gas 2DEG is induced on one side of the channel layer 13 . For example, the anode 60 may be finger-shaped or circular in plan view, and the cathode 20 is located near the anode 60. Optionally, the distance between the cathode 20 and the anode 60 is less than or equal to 20 μm.

Further, the epitaxial structure 10 is provided with grooves, at least part of the anode 60 is located in the grooves of the epitaxial structure 10, and the grooves interrupt the two-dimensional electron gas 2DEG in the epitaxial structure 10, thereby eliminating the capacitance in the groove area.

Furthermore, the orthographic projection of the anode 60 on the plane where the two-dimensional electron gas 2DEG is located has no overlap with the two-dimensional electron gas 2DEG. For example, "the orthographic projection of the anode 60 on the plane where the two-dimensional electron gas 2DEG is located does not overlap with the two-dimensional electron gas 2DEG" can mean that the anode 60 and the two-dimensional electron gas 2DEG do not form an overlapping positional relationship, or it can also mean that the anode The relative area of 60 and the two-dimensional electron gas 2DEG is 0. In this way, it is beneficial to reduce the parasitic capacitance of the semiconductor structure 100 and improve the performance of the device.

In the above semiconductor structure, since the orthographic projection of the anode 60 on the plane of the two-dimensional electron gas 2DEG does not overlap with the two-dimensional electron gas 2DEG, the overlap between the anode 60 and the two-dimensional electron gas 2DEG can be effectively reduced or eliminated, thereby reducing or eliminating The parasitic capacitance generated by the overlap of the two improves device performance.

In other embodiments, with continued reference to FIG. 12 , a dielectric layer 40 is further disposed between the anode 60 and the cathode 20 . The dielectric layer 40 serves as a passivation layer, which can effectively suppress device current collapse and avoid device performance degradation. For example, the dielectric layer 40 may be an insulating medium such as silicon nitride (SiN) or silicon dioxide (SiO ₂ ).

In other embodiments, continuing to refer to FIG. 12 , the bottom surface of the groove of the epitaxial structure is located 5 nm to 25 nm below the interface between the channel layer 13 and the barrier layer 14 . In this way, it is helpful to ensure that the groove can interrupt the two-dimensional electron gas 2DEG. If the bottom surface of the groove is located within 5 nm below the interface between the channel layer 13 and the barrier layer 14, it is still easy to generate a large parasitic capacitance. In addition, considering the actual process implementation, it needs to be over-etched by 10 nm to 20 nm; if it continues to be deep, although It has little impact on device performance, but will increase preparation time and cost. In summary, etching the groove to a position 5 nm to 25 nm below the interface between the channel layer 13 and the barrier layer 14 can reduce the parasitic capacitance without increasing the preparation time and cost.

In other embodiments, the anode 60 includes a first metal layer and a second metal layer stacked along the thickness direction of the epitaxial structure 10 , the first metal layer is located between the epitaxial structure 10 and the second metal layer, wherein the first metal layer The material of the metal layer is a low work function metal, the thickness of the first metal layer ranges from 30 nm to 400 nm, and the thickness of the second metal layer is less than or equal to 400 nm. Optionally, the material of the first metal layer includes at least one of molybdenum (Mo), tungsten (W), and nickel (Ni), and the material of the second metal layer includes gold (Au). By making the thickness of each metal layer meet the above range, on the one hand, it can be avoided that the metal layer is not able to cover the groove well during preparation due to the metal being too thin (for example, the metal does not contact the epitaxial structure 10 at the bottom edge corner of the groove). tightness and poor continuity). On the other hand, it can also avoid the problem of discontinuity in the metal layer itself caused by too thin metal.

In other embodiments, the substrate 10 is a silicon carbide (SiC) substrate with a thickness of 100 μm ~ 600 μm or a sapphire substrate with a thickness of 100 μm ~ 600 μm or a silicon (Si) substrate with a thickness of 100 μm ~ 1000 μm or 100 μm ~ 600 μm. Gallium Nitride (GaN) substrate.

In other embodiments, the buffer layer 12 uses a gallium nitride (GaN) buffer layer with a thickness of 1 μm to 6 μm or an aluminum gallium nitride (AlGaN) gradient buffer layer with a thickness of 1 μm to 6 μm.

In other embodiments, the channel layer 13 uses an unintentionally doped gallium nitride (GaN) channel layer with a thickness of 100 nm to 400 nm.

The present application also provides a method for preparing the semiconductor structure as described above. This preparation method reduces or eliminates the overlap between the anode and the two-dimensional electron gas by removing at least the anode on the top surface of the dielectric layer, thereby reducing or eliminating the parasitic capacitance generated by the overlap between the two, and improving device performance (such as the frequency characteristics of the device) .

In one embodiment, as shown in Figure 2, the preparation method includes the following steps:

S100. Provide an epitaxial structure with a cathode formed thereon.

For example, as shown in FIG. 4 , a cathode 20 is provided on the epitaxial structure 10 . The epitaxial structure 10 may include a substrate 11 and a buffer layer 12 , a channel layer 13 , and a barrier layer 14 sequentially arranged along the thickness direction of the substrate 11 , and near the interface between the channel layer 13 and the barrier layer 14 A high concentration of two-dimensional electron gas 2DEG is induced on the side close to the channel layer 13 .

S200. Form a dielectric layer on the epitaxial structure and the cathode.

For example, as shown in FIG. 6 , the dielectric layer 40 may be deposited on the epitaxial structure 10 and the cathode 20 through a plasma enhanced chemical vapor deposition process. For example, the dielectric layer 40 includes an insulating medium such as silicon nitride (SiN) or silicon dioxide (SiO ₂ ).

S300. Remove part of the dielectric layer and the epitaxial structure with a predetermined thickness corresponding to the part of the dielectric layer to form an anode groove that interrupts the two-dimensional electron gas in the epitaxial structure.

For example, glue leveling, baking, exposure, and development can be performed sequentially on the dielectric layer 40 to form a patterned photoresist layer, and then the dielectric layer 40 is etched to the surface of the barrier layer 14 through etching technology, and then the dielectric layer 40 is etched to the surface of the barrier layer 14 through The etching technology further etches the barrier layer 14 and the channel layer 13 (that is, the epitaxial structure of a predetermined thickness) corresponding to the removed dielectric layer 40 until it is 5 nm to 25 nm below the interface between the barrier layer 14 and the channel layer 13. That is to say, the value range of the predetermined thickness can be the thickness of the barrier layer 14 plus 5 nm to 25 nm; then the current structure is placed in acetone, absolute ethanol, and deionized water solution for ultrasonic cleaning for a predetermined time, and finally it is cleaned with nitrogen Blow dry to complete the production of the anode groove 50 as shown in Figure 7. It can be seen that the anode groove 50 interrupts the two-dimensional electron gas 2DEG in the epitaxial structure 10, reducing the parasitic capacitance without being too deep, saving preparation time and cost. Optionally, the distance between the cathode 20 and the anode groove 50 is less than or equal to 20 μm.

S400. Form an anode on the surface of the anode groove and the surface of the dielectric layer connected to the surface of the anode groove.

Due to errors in the photolithography process, the photoresist cannot be coated exactly to the edge of the anode groove 50 . Therefore, in order to ensure that the anode completely covers the anode groove 50 , a portion extending outside the anode groove 50 needs to be retained during photolithography (such as with The anode groove 50 is connected to the anode on the surface of the dielectric layer 40 , thereby forming an anode portion (shown by a dotted circle) overlapping the two-dimensional electron gas 2DEG as shown in FIG. 8 . On the other hand, by making the deposition thickness of each metal layer meet the above range, on the one hand, it can be avoided that the metal layer is too thin and cannot cover the anode groove 50 well during preparation (for example, at the bottom edge corner of the anode groove 50 This prevents problems such as loose contact and poor continuity between the metal and the epitaxial structure 10. On the other hand, it can also avoid the problem of discontinuity of the metal layer itself caused by the metal being too thin.

Exemplarily, step S400 may include the following steps: S410, forming a patterned photoresist layer on the dielectric layer 40 and the epitaxial structure 10; S420, forming a patterned photoresist layer on the dielectric layer 40, the epitaxial structure 10 and the patterned photoresist layer through a deposition process. An anode metal layer is formed on the photoresist layer; S430, the patterned photoresist layer and the anode metal layer on the patterned photoresist layer are removed through a stripping process, leaving the dielectric layer and the anode metal layer on the epitaxial structure to form an anode 60.

For example, in a specific embodiment, glue leveling, baking, exposure, and development can be performed sequentially on the structure of the anode groove 50 after etching, and magnetron sputtering equipment or electron beam evaporation equipment can be used to etch the anode groove 50 . The surface of the tank 50 is first deposited with low work function metal molybdenum (Mo) or tungsten (W) or nickel (Ni) with a thickness of 30 nm to 400 nm, and then metal gold Au with a thickness of 0 to 400 nm is deposited, and then soaked in an acetone solution to form a photoresist area. The metal is peeled off, and then the epitaxial wafer is placed in clean acetone, absolute ethanol, and deionized water solution for ultrasonic cleaning for a predetermined time, and finally dried with nitrogen to complete the production of the anode 60 as shown in Figure 8. Optionally, the anode can be made of Schottky metal or other metals suitable for preparing anodes.

S500: Remove at least the anode on the top surface of the dielectric layer.

For example, as shown in FIG. 10 , the anode on the top surface of the dielectric layer 40 can be removed through an etching process to reduce the parasitic capacitance of the device. For example, as shown in FIG. 11 , the anode higher than the top surface of the dielectric layer 40 can also be removed through a grinding or polishing process to reduce the parasitic capacitance of the device, which is beneficial to simplifying the anode removal process. For example, as shown in FIG. 9 , part of the dielectric layer and part of the anode can also be removed from top to bottom through a grinding or polishing process, so that the orthographic projection of the anode 60 on the plane where the two-dimensional electron gas 2DEG is located is consistent with the two-dimensional electron gas 2DEG. There is no overlapping part to reduce the parasitic capacitance of the device, which is beneficial to further thinning the structure and does not increase the complexity of the process. For example, the back side of the structure can be bonded to a grinding disc and then the front side of the structure can be ground to achieve the grinding effect shown in Figure 9 or Figure 11. The structure can then be debonded and put into clean acetone and anhydrous water in sequence. Ultrasonically clean in ethanol and deionized water solutions for a predetermined time, and finally blow dry with nitrogen to complete partial anode removal as shown in Figure 9 or Figure 11. By using a grinding or polishing process to remove the anode overlapping the two-dimensional electron gas, it is simple, effective and feasible, and the device yield is also high.

The above preparation method of the semiconductor structure can effectively reduce or eliminate the overlap of the anode 60 and the two-dimensional electron gas 2DEG by removing the anode on the top surface of the dielectric layer 40, thereby reducing or eliminating the parasitic capacitance generated by the overlap of the two, and improving the device performance.

In other embodiments, before step S100, there are also steps:

S100”, cleaning epitaxial structure.

For example, the epitaxial structure is first soaked in a hydrofluoric acid (HF) solution or a hydrogen chloride (HCl) solution for a predetermined time, and then placed in an acetone solution, anhydrous ethanol solution, and deionized water for ultrasonic cleaning for a predetermined time, and finally cleaned with Blow dry with nitrogen to complete the production of a clean epitaxial structure 10 as shown in Figure 3 .

In other embodiments, before step S100, there are also steps:

S100’, making the device cathode.

For example, the clean epitaxial structure 10 can be smoothed, baked, exposed, and developed in sequence, and electron beam evaporation equipment can be used to deposit titanium (Ti)/aluminum (Al)/nickel (Ni) on the epitaxial structure 10 /Gold (Au) metal stack, then soak the structure in an acetone solution to peel off the metal in the photoresist area, and then put the structure into acetone, absolute ethanol, and deionized water solution for ultrasonic cleaning for a predetermined time, and use nitrogen After drying, it is placed in a rapid annealing furnace for annealing to form the device cathode 20 as shown in Figure 4. Optionally, the cathode 20 can be made of ohmic contact metal, or other metals suitable for preparing cathodes.

In other embodiments, before step S200, the steps are also included:

S200’, making the countertop isolation structure.

For example, on the epitaxial structure 10 after the cathode is fabricated, glue spreading, baking, exposure, and development are performed in sequence, and then the two end regions (or areas outside the mesa) of the epitaxial structure 10 are etched through an etching process, and then the structure is Put it into acetone, absolute ethanol, and deionized water solution for ultrasonic cleaning for a predetermined time, and blow dry with nitrogen to complete the production of the table isolation structure 30 as shown in Figure 5.

In other embodiments, in step S200, in order to ensure that the device structure (such as the cathode metal) is not damaged when the anode is removed on the table in the subsequent process, the deposition thickness of the dielectric layer 40 needs to be greater than the thickness of the cathode 20. This ensures that the cathode The thickness of the dielectric layer between 20 and the anode groove 50 is greater than the thickness of the cathode 20 to avoid damage to the device structure during the subsequent anode removal process. For example, the deposition thickness h of the dielectric layer 40 satisfies 300nm<h≤1000nm; or satisfies 300nm<h≤600nm. By controlling the deposition thickness to be greater than 300 nm, it can be ensured that the thickness of the dielectric layer 40 is greater than the thickness of the cathode 20, thereby avoiding damage to the cathode 20 during the subsequent anode removal process. At the same time, the deposition thickness of the dielectric layer 40 is less than or equal to 1000 nm, which can avoid the dielectric layer being damaged. 40 is too thick and affects the film formation quality; in addition, by controlling the deposition thickness of the dielectric layer 40 to be less than or equal to 600 nm, material waste can be reduced and subsequent process time can be saved.

In other embodiments, the preparation method further includes the following steps after step S500:

S600. Etch the dielectric layer on the cathode so that at least part of the top surface of the cathode is exposed to the air.

For example, the structure of the anode after being fabricated is sequentially subjected to glue leveling, baking, exposure, and development, and the through hole area is etched to the metal surface of the cathode through an etching process, and then the structure is sequentially placed in acetone, absolute ethanol, Ultrasonically clean in a deionized water solution for a predetermined time, and finally blow dry with nitrogen to complete the preparation of the semiconductor structure 100 as shown in FIG. 12 .

The technical features of the above-described embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, All should be considered to be within the scope of this manual.

The above-mentioned embodiments only express several implementation modes of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the scope of protection of the patent of the present invention should be determined by the appended claims.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising:

providing an epitaxial structure formed with a cathode;

forming a dielectric layer on the epitaxial structure and the cathode;

removing part of the dielectric layer and the epitaxial structure with a preset thickness corresponding to the part of the dielectric layer to form an anode groove for interrupting two-dimensional electron gas in the epitaxial structure;

forming an anode on the surface of the anode groove and the surface of the dielectric layer connected with the surface of the anode groove;

and removing at least the anode on the top surface of the dielectric layer.

2. The method of claim 1, wherein forming a dielectric layer over the epitaxial structure and the cathode comprises:

forming the dielectric layer on the epitaxial structure and the cathode through a deposition process; wherein, the deposition thickness of the dielectric layer is larger than the thickness of the cathode.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein a deposition thickness h of the dielectric layer satisfies 300nm < h.ltoreq.1000 nm; or, the wavelength of 300nm < h is less than or equal to 600nm.

4. The method for manufacturing a semiconductor structure according to claim 1 or 2, wherein the removing at least the anode on the top surface of the dielectric layer comprises:

and removing the anode above the top surface of the dielectric layer through grinding or polishing process.

5. The method for manufacturing a semiconductor structure according to claim 1 or 2, wherein the removing at least the anode on the top surface of the dielectric layer comprises:

and removing part of the dielectric layer and part of the anode from top to bottom through grinding or polishing process, so that orthographic projection of the anode on the plane where the two-dimensional electron gas is located and the two-dimensional electron gas have no overlapping part.

6. The method of manufacturing a semiconductor structure according to claim 1, wherein forming an anode on a surface of the anode groove and a surface of a dielectric layer connected to the surface of the anode groove comprises:

forming a patterned photoresist layer on the dielectric layer and the epitaxial structure;

forming an anode metal layer on the dielectric layer, the epitaxial structure and the patterned photoresist layer through a deposition process;

and removing the patterned photoresist layer and the anode metal layer on the patterned photoresist layer through a stripping process, and reserving the dielectric layer and the anode metal layer on the epitaxial structure to form the anode.

7. The method of claim 1, further comprising, after removing at least the anode on the top surface of the dielectric layer:

and etching the dielectric layer on the cathode to expose at least part of the top surface of the cathode to air.

8. A semiconductor structure, comprising: an epitaxial structure, and a cathode and an anode arranged on the epitaxial structure;

wherein,

the epitaxial structure is provided with a groove, at least part of the anode is positioned in the groove, and the groove interrupts two-dimensional electron gas in the epitaxial structure;

wherein,

and the orthographic projection of the anode on the plane where the two-dimensional electron gas is located is not overlapped with the two-dimensional electron gas.

9. The semiconductor structure of claim 8, wherein a dielectric layer is disposed between the anode and the cathode.

10. The semiconductor structure of claim 8, wherein the anode comprises a first metal layer and a second metal layer stacked along a thickness direction of the epitaxial structure, the first metal layer is located between the epitaxial structure and the second metal layer, wherein a material of the first metal layer is a low work function metal, a thickness of the first metal layer ranges from 30nm to 400nm, and a thickness of the second metal layer is less than or equal to 400nm.