CN116844994A - A process and equipment for full wafer deposition - Google Patents
A process and equipment for full wafer deposition Download PDFInfo
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- CN116844994A CN116844994A CN202210295724.8A CN202210295724A CN116844994A CN 116844994 A CN116844994 A CN 116844994A CN 202210295724 A CN202210295724 A CN 202210295724A CN 116844994 A CN116844994 A CN 116844994A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/12—Preparing bulk and homogeneous wafers
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Abstract
本发明公布了一种用于全晶圆沉积的工艺和设备，设备包括包括结晶炉、切片机、抛光机、氧化炉、化学气相沉积机、涂胶机、曝光机、显影机、光刻机、蚀刻机和离子注入机；工艺包括以下步骤：晶圆成形、衬底成形、图形光刻、蚀刻、掺杂和成品处理，本发明公开了晶圆沉积过程中需要使用的各种设备，从而使得具体操作的时候，可以对设备需求进行全方位的把握；本发明公开了晶圆沉积过程中的工艺步骤，并对各个不同的工艺步骤进行具体的设计，从而可以高效、高质量的完成晶圆的生产和制造。
The invention discloses a process and equipment for full wafer deposition. The equipment includes a crystallization furnace, a slicer, a polishing machine, an oxidation furnace, a chemical vapor deposition machine, a glue coating machine, an exposure machine, a developing machine, and a photolithography machine. , etching machine and ion implanter; the process includes the following steps: wafer forming, substrate forming, pattern photolithography, etching, doping and finished product processing. The invention discloses various equipment needed to be used in the wafer deposition process, thereby This enables an all-round understanding of equipment requirements during specific operations; the present invention discloses the process steps in the wafer deposition process, and conducts specific designs for each different process step, so that the wafer deposition can be completed efficiently and with high quality. Circle production and manufacturing.
Description
Technical Field
The invention relates to the technical field of semiconductor production, in particular to a process and equipment for full wafer deposition.
Background
The wafer refers to a silicon wafer used for manufacturing a silicon semiconductor circuit, the original material is silicon, the wafer is a front-end material for manufacturing chips, and the quality of the formed wafer directly influences the quality of the subsequent chips.
The deposition process refers to forming a film-like substrate material on the surface of a wafer, which includes two types of physical vapor deposition and chemical vapor deposition, and the substrate on the wafer is generally manufactured by a chemical vapor deposition method.
The patent application number is: chinese patent CN202111435268.4 discloses a wafer deposition process method for CVD apparatus, comprising: a preheating position is arranged in the CVD reaction chamber; preheating a wafer at a preheating position of a CVD reaction chamber before deposition processing; after the preheating is completed, the wafer is placed on a processing machine to carry out deposition processing. The wafer deposition processing method can reduce the fragmentation rate during the wafer CVD deposition processing, thereby being capable of assisting in improving the utilization rate of CVD equipment.
However, the above patent discloses a method for depositing a substrate on a wafer, and the wafer deposition process further includes a plurality of pre-processes, post-processes and auxiliary devices, which do not fully design the entire production process of the wafer deposition.
Disclosure of Invention
In order to solve the problems, the invention provides a process and equipment for full wafer deposition, and the invention is realized by the following technical scheme.
An apparatus for full wafer deposition includes a crystallization furnace, a microtome, a polisher, an oxidation furnace, a chemical vapor deposition machine, a gumming machine, an exposure machine, a developing machine, a lithography machine, an etching machine, and an ion implanter.
A process for full wafer deposition, the process comprising the steps of:
s1: forming a wafer, namely forming a flaky single crystal wafer by using a silicon raw material;
s2: forming a substrate, namely forming the substrate on the surface of a wafer;
s3: pattern photoetching, namely transferring the pattern on the mask plate to a substrate;
s4: etching, namely removing the substrate except the pattern formed in the step S3 by an etching machine;
s5: doping, namely doping the area near the surface of the wafer by an ion implanter so as to change the concentration and the conductivity type of the entrapping element of the wafer;
s6: and (5) processing a finished product.
Further, the step S1 includes the following substeps:
t1: forming a crystal bar, dissolving a silicon raw material in a crystallization furnace, infiltrating silicon crystal seeds, and pulling out the seeds to form a cylindrical crystal bar;
t2: slicing, namely slicing the crystal bar into slice wafers through a slicing machine;
t3: and (3) wafer processing, namely polishing and polishing the wafer by a polishing machine, and cleaning the wafer.
Further, the step S2 includes the following substeps:
t1: oxidizing, namely putting the wafer processed in the step S3 into an oxidizing furnace to enable the wafer to be oxidized according to the expected design;
t2: and (3) vapor deposition, namely putting the wafer subjected to the oxidization in the step (T1) into a reaction chamber of a chemical vapor deposition machine, introducing vapor containing a gaseous reactant or a liquid reactant forming the substrate element and reaction shielding gas into the reaction chamber, and performing chemical reaction on the surface of the wafer to generate a deposited film, wherein the deposited film is the substrate.
Further, in the step S3, the method includes the following substeps:
t1: spreading glue, namely spreading photoresist on a substrate through a glue spreader;
t2: exposing, namely exposing the photoresist through an exposure machine;
t3: developing, and projecting the graph on the mask onto the photoresist through a developing machine;
t4: and e, photoetching, namely, engraving a pattern consistent with the mask plate on the substrate through a photoetching machine.
Further, in the step S6, during the processing of the finished product, a Wafer Acceptability Test (WAT) and a needle test are sequentially performed on the processed wafer, and after the test is completed, the wafer is packaged after sequentially performing a cutting and wire bonding procedure.
Further, the packaged wafer also needs to undergo IC testing and burn-in testing.
The beneficial effects of the invention are as follows:
1. the invention discloses various devices which are required to be used in the wafer deposition process, so that the device requirement can be comprehensively grasped during specific operation;
2. the invention discloses a process step in the wafer deposition process, and specific designs are carried out on different process steps, so that the production and the manufacture of the wafer can be completed with high efficiency and high quality.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the drawings that are needed in the description of the specific embodiments will be briefly described below, it being obvious that the drawings in the following description are only some examples of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1: the invention discloses a flow diagram of a process for full wafer deposition;
fig. 2: the flow of the wafer forming step and the equipment matching schematic diagram are provided;
fig. 3: the process and equipment matching schematic diagram of the substrate forming step are provided;
fig. 4: the invention discloses a flow of graphic photoetching steps and a schematic diagram of equipment matching.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1-4, an apparatus for full wafer deposition includes a crystallization furnace, a microtome, a polisher, an oxidation furnace, a chemical vapor deposition machine, a gumming machine, an exposure machine, a development machine, a lithography machine, an etching machine, and an ion implanter.
Through designing various equipment that needs to use in the wafer deposition process for carry out all-round assurance to required equipment, be convenient for carry out equipment management and control, also make the production link can go on in order.
A process for full wafer deposition, the process comprising the steps of:
s1: forming a wafer, namely forming a flaky single crystal wafer by using a silicon raw material;
in step S1, the following sub-steps are included:
t1: forming a crystal bar, dissolving a silicon raw material in a crystallization furnace, infiltrating silicon crystal seeds, and pulling out the seeds to form a cylindrical crystal bar;
t2: slicing, namely slicing the crystal bar into slice wafers through a slicing machine;
t3: and (3) wafer processing, namely polishing and polishing the wafer by a polishing machine, and cleaning the wafer.
The silicon raw material is manufactured into a crystal bar of a monocrystal through a crystallization furnace, the temperature of the crystallization furnace and the pulling speed of a seed crystal are reasonably controlled in the process of crystal bar forming, so that the formed crystal bar is complete, and then the crystal bar is subjected to circular knife treatment, so that the crystal bar forms a required diameter.
Slicing the crystal bar by a slicing machine, screening, and removing partial gaps or surface concave parts.
The wafer is polished through the polishing machine, two sides of the wafer are polished, flatness is controlled through the roughometer, and the polished thickness is controlled through the caliper.
S2: forming a substrate, namely forming the substrate on the surface of a wafer;
in step S2, the following sub-steps are included:
t1: oxidizing, namely putting the wafer processed in the step S3 into an oxidizing furnace to enable the wafer to be oxidized according to the expected design;
t2: and (3) vapor deposition, namely putting the wafer subjected to the oxidization in the step (T1) into a reaction chamber of a chemical vapor deposition machine, introducing vapor containing a gaseous reactant or a liquid reactant forming the substrate element and reaction shielding gas into the reaction chamber, and performing chemical reaction on the surface of the wafer to generate a deposited film, wherein the deposited film is the substrate.
And oxidizing the wafer by an oxidizing furnace to provide an oxidizing environment meeting the requirements, so that the wafer is oxidized according to the expected design.
Putting the wafer into a reaction chamber of a chemical vapor deposition machine, introducing vapor containing gaseous reactants or liquid reactants forming the substrate elements and reaction shielding gas into the reaction chamber, and performing chemical reaction on the surface of the wafer to generate a deposited film, wherein the deposited film is the substrate.
S3: pattern photoetching, namely transferring the pattern on the mask plate to a substrate;
in step S3, the following sub-steps are included:
t1: spreading glue, namely spreading photoresist on a substrate through a glue spreader;
t2: exposing, namely exposing the photoresist through an exposure machine;
t3: developing, and projecting the graph on the mask onto the photoresist through a developing machine;
t4: and e, photoetching, namely, engraving a pattern consistent with the mask plate on the substrate through a photoetching machine.
Through smearing the photoresist on the substrate through the spreading machine, need pay attention to when smearing whether the thickness of smearing is even, through control smearing head uniform velocity and go on realizing even smearing, after smearing the completion, need detect, if smear disqualified then scrape the photoresist from new smearing.
Optical development generally includes photoresist coating, baking, light alignment, exposure and development steps. Dry etching is the most commonly used etching method, which uses gas as the main etching medium, and the reaction is driven by plasma. Etching is the removal of some unwanted material portions of the surface.
S4: etching, namely removing the substrate except the pattern formed in the step S3 by an etching machine;
s5: doping, namely doping the area near the surface of the wafer by an ion implanter so as to change the concentration and the conductivity type of the entrapping element of the wafer;
s6: and (5) processing a finished product.
In step S6, during the processing of the finished product, firstly, a Wafer Acceptability Test (WAT) and a needle test are sequentially performed on the processed wafer, and after the test is completed, the wafer is packaged after sequentially performing a cutting and wire bonding procedure.
The packaged wafer also needs to undergo IC testing and burn-in testing.
Before WAT test, the finished product is treated by chemical mechanical polishing, which is a combined technology of mechanical polishing and acid-base solution type chemical polishing, so that the surface of the wafer is flat, and the subsequent process is convenient. During polishing, the slurry is between the wafer and the polishing pad. Factors affecting CMP are: the pressure of the polishing head and the wafer flatness, the rotational speed, the chemical composition of the slurry, etc.
The preferred embodiments of the invention disclosed above are intended only to assist in the explanation of the invention. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (7)
1. An apparatus for full wafer deposition comprising a crystallization furnace, a microtome, a polisher, an oxidation furnace, a chemical vapor deposition machine, a gumming machine, an exposure machine, a developing machine, a lithography machine, an etching machine, and an ion implanter.
2. A process for full wafer deposition according to claim 1, comprising the steps of:
s1: forming a wafer, namely forming a flaky single crystal wafer by using a silicon raw material;
s2: forming a substrate, namely forming the substrate on the surface of a wafer;
s3: pattern photoetching, namely transferring the pattern on the mask plate to a substrate;
s4: etching, namely removing the substrate except the pattern formed in the step S3 by an etching machine;
s5: doping, namely doping the area near the surface of the wafer by an ion implanter so as to change the concentration and the conductivity type of the entrapping element of the wafer;
s6: and (5) processing a finished product.
3. A process for full wafer deposition according to claim 2, characterized in that in step S1, it comprises the following sub-steps:
t1: forming a crystal bar, dissolving a silicon raw material in a crystallization furnace, infiltrating silicon crystal seeds, and pulling out the seeds to form a cylindrical crystal bar;
t2: slicing, namely slicing the crystal bar into slice wafers through a slicing machine;
t3: and (3) wafer processing, namely polishing and polishing the wafer by a polishing machine, and cleaning the wafer.
4. A process for full wafer deposition according to claim 3, characterized in that in step S2, the following sub-steps are included:
t1: oxidizing, namely putting the wafer processed in the step S3 into an oxidizing furnace to enable the wafer to be oxidized according to the expected design;
t2: and (3) vapor deposition, namely putting the wafer subjected to the oxidization in the step (T1) into a reaction chamber of a chemical vapor deposition machine, introducing vapor containing a gaseous reactant or a liquid reactant forming the substrate element and reaction shielding gas into the reaction chamber, and performing chemical reaction on the surface of the wafer to generate a deposited film, wherein the deposited film is the substrate.
5. A process for full wafer deposition according to claim 4, characterized in that in step S3, it comprises the following sub-steps:
t1: spreading glue, namely spreading photoresist on a substrate through a glue spreader;
t2: exposing, namely exposing the photoresist through an exposure machine;
t3: developing, and projecting the graph on the mask onto the photoresist through a developing machine;
t4: and e, photoetching, namely, engraving a pattern consistent with the mask plate on the substrate through a photoetching machine.
6. The process for full wafer deposition according to claim 5, wherein in step S6, the finished product is processed by performing Wafer Acceptance Testing (WAT) and probing in sequence on the processed wafer, and after the testing, performing dicing and wire bonding in sequence, and packaging.
7. The process for full wafer deposition as claimed in claim 6, wherein the packaged wafer is further subjected to IC testing and burn-in testing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210295724.8A CN116844994A (en) | 2022-03-23 | 2022-03-23 | A process and equipment for full wafer deposition |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210295724.8A CN116844994A (en) | 2022-03-23 | 2022-03-23 | A process and equipment for full wafer deposition |
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| CN116844994A true CN116844994A (en) | 2023-10-03 |
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| CN202210295724.8A Pending CN116844994A (en) | 2022-03-23 | 2022-03-23 | A process and equipment for full wafer deposition |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0470784A2 (en) * | 1990-08-10 | 1992-02-12 | Motorola Inc. | Method for selectively depositing a thin film |
| US6055460A (en) * | 1997-08-06 | 2000-04-25 | Advanced Micro Devices, Inc. | Semiconductor process compensation utilizing non-uniform ion implantation methodology |
| JP2010050353A (en) * | 2008-08-22 | 2010-03-04 | Shin Etsu Handotai Co Ltd | Semiconductor wafer, method of manufacturing the same, and method of evaluating the same |
| CN108303766A (en) * | 2018-01-12 | 2018-07-20 | 浙江富春江光电科技有限公司 | A kind of planar optical waveguide wafer production technology method |
| CN108550534A (en) * | 2018-05-08 | 2018-09-18 | 广西桂芯半导体科技有限公司 | A kind of processing method of semiconductor |
-
2022
- 2022-03-23 CN CN202210295724.8A patent/CN116844994A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0470784A2 (en) * | 1990-08-10 | 1992-02-12 | Motorola Inc. | Method for selectively depositing a thin film |
| US6055460A (en) * | 1997-08-06 | 2000-04-25 | Advanced Micro Devices, Inc. | Semiconductor process compensation utilizing non-uniform ion implantation methodology |
| JP2010050353A (en) * | 2008-08-22 | 2010-03-04 | Shin Etsu Handotai Co Ltd | Semiconductor wafer, method of manufacturing the same, and method of evaluating the same |
| CN108303766A (en) * | 2018-01-12 | 2018-07-20 | 浙江富春江光电科技有限公司 | A kind of planar optical waveguide wafer production technology method |
| CN108550534A (en) * | 2018-05-08 | 2018-09-18 | 广西桂芯半导体科技有限公司 | A kind of processing method of semiconductor |
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