CN116467982B - An Impedance Matching Network Topology Design Method for a Broadband RF Amplifier - Google Patents

An Impedance Matching Network Topology Design Method for a Broadband RF Amplifier

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CN116467982B
CN116467982B CN202310245753.8A CN202310245753A CN116467982B CN 116467982 B CN116467982 B CN 116467982B CN 202310245753 A CN202310245753 A CN 202310245753A CN 116467982 B CN116467982 B CN 116467982B
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network
impedance
parallel
parasitic capacitance
transmission matrix
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CN116467982A (en
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彭林
徐泽基
张志浩
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Guangdong University of Technology
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/36—Indexing scheme relating to amplifiers the amplifier comprising means for increasing the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Computer Hardware Design (AREA)
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Abstract

本发明公开了一种宽带射频放大器的阻抗匹配网络拓扑设计方法，从晶体管的等效模型入手，通过在P1dB处load_pull仿真所得的Zopt提取出切实所需的Ropt与并联寄生电容Cout数值，进而将现有技术方案框架内不得不应对的棘手频变Zopt匹配问题简化成单点间的阻抗变换，降低了实现难度，同时省去繁琐的迭代优化过程，提高了设计效率。另外，本发明给出了完善的补偿网络设计流程，能以所需的实施形式、在任意指定的带宽内很好地降低并联寄生电容Cout对终端阻抗Zload到恒定的最优本征负载电阻Ropt变换的影响，涉及的待定元件参数均有相应明晰的推导式以便于快速求解。

This invention discloses an impedance matching network topology design method for a broadband RF amplifier. Starting from the equivalent model of the transistor, it extracts the required values of Ropt and parallel parasitic capacitance Cout from the Zopt obtained by load_pull simulation at P1dB. This simplifies the challenging frequency-varying Zopt matching problem inherent in existing technologies into a single-point impedance transformation, reducing implementation difficulty and eliminating tedious iterative optimization processes, thus improving design efficiency. Furthermore, this invention provides a complete compensation network design process, which can effectively reduce the impact of parallel parasitic capacitance Cout on the transformation of the terminal impedance Zload to the constant optimal intrinsic load resistance Ropt within any specified bandwidth, in the desired implementation form. All parameters of the undetermined components have clear derivations for rapid solution.

Description

Impedance matching network topology design method for broadband radio frequency amplifier
Technical Field
The invention relates to the technical field of broadband radio frequency amplifier design, in particular to an impedance matching network topology design method of a broadband radio frequency amplifier.
Background
An effective, flexible and cost-controllable spectrum coverage solution is one of the main evolution directions in the industry, and due to the consideration of rapid capacity expansion and network deployment of mobile and wireless communication systems, the current communication network is and will be in a networking state with multiple systems and multiple standards coexisting for a long time. In addition, in order to achieve the goals of high capacity, high speed and low time delay, the new generation 5G system must gradually extend from Sub-6GHz to the millimeter wave frequency band which can provide larger bandwidth resources. Accordingly, the development and popularization of a wideband radio frequency front-end module capable of supporting multimode and multifrequency has become necessary, wherein core components involved are a Power Amplifier (PA) and a low-noise amplifier (LNA) for realizing signal amplification of transmission and reception channels.
The essence of the wideband rf amplifier design is to construct a wideband impedance matching network to achieve a series of optimal fundamental load impedances Z opt required to regulate the transistor in a specified continuous wideband, thereby enabling the transistor to operate in the desired state at different frequency points. Generally, Z opt at discrete frequencies is determined by load-pull simulation of a transistor, and an optimal impedance track formed by sequentially connecting acquired Z opt in increasing frequency order is an impedance matching effect that should be realized by the matching network as much as possible.
The main stream matching design concept is to choose one of the tradeoffs in a series of Z opt or to re-formulate a center impedance Z ctr based on the distribution of Z opt to approximately represent the performance balance matching point in the broadband. Let the selected impedance be r+jx, its quality factor q=x/R, if Q is less than the upper limit Q of the undetermined matching network, Q max, calculated from the equation Q max＝f0/BW, where f 0 is the center frequency of the design band BW, the entire design band BW can be fully covered by the multi-stage cascade matching circuit. Next to the implementation level, the exact impedance transformation from terminal Z load (e.g. standard system load 50Ω) to r+jx can be accomplished by graphically and intuitively determining the network topology in an area smaller than the Q max line with the aid of a smith chart, see for example fig. 1.
The prior art scheme has good applicability to the application scenario of the radio frequency amplifier with small bandwidth requirement, namely, the situation of low Z opt discreteness. However, for the increasingly popular multi-band and multi-system compatible large-bandwidth communication system, the amplifier design will face the problem that Z opt at low and high side frequency points is far away, and the limitation of the compromise impedance matching strategy is remarkable at the moment, because the performance of a certain frequency domain in the band is inevitably sacrificed, and although the deficiency can be relieved to a certain extent by repeatedly tuning, optimizing or adding more matching elements to the preliminarily built matching structure by means of CAD software, the problem is that the conventional practical experience is relied on, and the wideband flat response meeting the expectations cannot be realized quickly and at low cost.
In fact, the discreteness of Z opt over frequency is mainly due to the effect of the output parasitic capacitance C out of the transistor. The prior publications have indicated that the equivalent output impedance model of the transistor can be built in the form of a parallel R optCout network, but the optimal intrinsic load resistance R opt of the active device in the equivalent model is often based on classical load line theory, which is based on many ideal assumptions and ignores consideration of bias levels, so that the resulting R opt will be relatively large. The parasitic parameter C out is extracted by small signal simulation or actual measurement, however, C out is a nonlinear quantity and has different values under different excitation conditions, and the equipment such as a base station which is in inverse reality operation is always in a large signal output state, so that a certain error can be generated in the design of the amplifier by adopting the traditional small signal parameter extraction method.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides an impedance matching network topology design method of a broadband radio frequency amplifier.
In order to achieve the above purpose, the technical scheme provided by the invention is as follows:
an impedance matching network topology design method of a broadband radio frequency amplifier, comprising:
A series of optimal fundamental wave load impedance Z opt in a broadband obtained based on load-pull simulation is equivalent to a parallel R optCout network model;
Based on a parallel R optCout network model, extracting an optimal intrinsic load resistance R opt and a parallel parasitic capacitance C out which are practically needed from an optimal fundamental load impedance Z opt obtained by load-pull simulation at a 1dB gain compression point;
The compensation network is designed to reduce the influence of the parallel parasitic capacitance C out on impedance matching, so that the target of broadband impedance matching is simplified from the track of the optimal fundamental wave load impedance Z opt following frequency variation to single-point impedance transformation from the terminal impedance Z load to the constant optimal intrinsic load resistance R opt, and the impedance matching network topology can be obtained through a Smith chart track method.
Further, extracting the optimal intrinsic load resistance R opt and the parallel parasitic capacitance C out actually required according to the optimal fundamental load impedance Z opt includes:
The optimal intrinsic load resistance R opt required for the transistor in the P1dB state is derived from the Z opt back-thrust at the center frequency point f 0 with its own parallel parasitic capacitance C out as follows:
In the above formula, re () is a real part taking function, im () is an imaginary part taking function, To take the conjugate of Z opt.
Further, the design of the compensation network comprises:
a1, acquiring a transmission matrix of a compensation network;
a2, solving a solution of a transmission matrix when the signal reaches the matching network from the compensation network without loss;
And A3, solving design parameters of the network N s to be designed through the solution of the transmission matrix, thereby obtaining the compensation network.
Further, obtaining the transmission matrix of the compensation network includes:
the compensation network is known to have symmetrical properties according to the conjugate matching principle, and then the transmission matrix of the compensation network is obtained according to the topology of the schematic diagram:
Wherein, the The transmission matrix, j representing the imaginary number, ω being the angular frequency,For the transmission matrix of the network N s to be designed, a 1、B1、C1 is a design parameter,The transmission matrix is jb parallel elements, b is susceptance.
Further, when the signal reaches the matching network from the compensating network without loss, Z out＝Zmn＝Ropt,Zout is the impedance obtained by the compensating network, the terminal Z load is the impedance transformed by the matching network, and R opt is the optimal intrinsic load resistance of the equivalent load at the two ends of the compensating network, and the following relation is obtained:
Γ out is the reflection coefficient.
Further, the establishment condition of the relational expression includes:
if and only if the constraint b=c=0 or is satisfied Equation of timeThis is true.
Further, susceptance b of parallel element jb is equal in value to the product of angular frequency ω and parallel parasitic capacitance C out, i.e., b=ωc out, thereby finishing:
A=A1+jB1b
B=B1
C=j2A1b-B1b2+C1。
Further, when the design parameters of the network N s to be designed are determined by solving the transmission matrix, when A, B, C is determined, the constraint b=c=0 and Are respectively equivalent to B 1＝j2A1b-B1b2+C1 =0,Thereby obtaining the design parameters of the network N s to be designed.
Compared with the prior art, the scheme has the following principle and advantages:
The scheme provides different broadband design ideas, namely, starting from an equivalent model of the transistor, the practically required R opt and parallel parasitic capacitance C out values are extracted through Z opt obtained through load-pull simulation at a 1dB gain compression point (namely, a linear and nonlinear juncture), so that the troublesome frequency change Z opt matching problem which has to be dealt with in the framework of the prior art is simplified into impedance transformation between single points, the realization difficulty is reduced, the complicated iterative optimization process is omitted, and the design efficiency is improved.
The implementation of the strategy should properly deal with the parallel parasitic capacitance C out, therefore, the scheme gives a perfect compensation network design flow, can well reduce the influence of the parallel parasitic capacitance C out on the conversion from the terminal impedance Z load to the constant optimal intrinsic load resistance R opt in any specified bandwidth in a required implementation form, and the related undetermined element parameters all have corresponding clear derivation formulas so as to be convenient for quick solving.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the services required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the figures in the following description are only some embodiments of the present invention, and that other figures can be obtained according to these figures without inventive effort to a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art method for graphically and intuitively determining a matching network topology in an area less than the line Q max with the aid of a Smith chart;
FIG. 2 is a schematic diagram of a die output circuit with a compensation network;
FIG. 3 is a schematic diagram of a lumped low pass compensation network;
FIG. 4 is a schematic diagram of a distributed low-pass compensation network;
FIG. 5 is a graph showing the reflection coefficient Γ out of a lumped low-pass compensation network and a distributed low-pass compensation network;
FIG. 6 is a graph comparing the forward transmission coefficients S 21 between two ends of the lumped low-pass compensation network and the distributed low-pass compensation network;
FIG. 7 is a schematic diagram of a lumped bandpass compensation network;
FIG. 8 is a schematic diagram of the reflection coefficient Γ out of the lumped band-pass compensation network;
fig. 9 is a schematic diagram of the forward transmission coefficient S 21 of the lumped band-pass compensation network.
Detailed Description
The invention is further illustrated by the following examples:
the method for designing the impedance matching network topology of the broadband radio-frequency amplifier according to the embodiment comprises the following steps:
s1, a series of optimal fundamental wave load impedance Z opt in a broadband obtained based on load-pull simulation is equivalent to a parallel R optCout network model;
S2, based on a parallel R optCout network model, extracting an optimal intrinsic load resistance R opt and a parallel parasitic capacitance C out which are practically needed from an optimal fundamental load impedance Z opt obtained by load-pull simulation at a 1dB gain compression point, wherein the process is as follows:
The optimal intrinsic load resistance R opt required for the transistor in the P1dB state is derived from the Z opt back-thrust at the center frequency point f 0 with its own parallel parasitic capacitance C out as follows:
In the above formula, re () is a real part taking function, im () is an imaginary part taking function, To take the conjugate of Z opt.
S3, designing a compensation network, reducing the influence of parallel parasitic capacitance C out on impedance matching, simplifying the target of broadband impedance matching from the track of optimal fundamental wave load impedance Z opt following frequency variation to single-point impedance transformation from terminal impedance Z load to constant optimal intrinsic load resistance R opt, thereby obtaining the topology of the impedance matching network through a Smith chart track method (the Smith chart can only realize transformation between two determined impedances, the traditional scheme needs to carry out single-point to series of frequency-variable impedance transformation, namely single-point to multiple-point, and the invention compensates the parallel parasitic capacitance C out, simplifies the broadband matching to single-point, thus completing all the designs by the simplest and intuitive circular chart method);
this step is illustrated with a field-effect transistor (FET) as a typical device development, with a die output circuit with a compensation network schematically shown in fig. 2. wherein the output part of the FET is approximated by an ideal voltage-controlled current source VCCS and a parallel parasitic capacitance C out in parallel, the transmission matrix component is A, B, The compensation networks of C and D absorb C out, the impedance obtained by looking at the compensation network from the VCCS plane is Z out, the corresponding reflection coefficient is gamma out, and the impedance of the terminal impedance Z load after being transformed by the matching network is Z mn. When the compensation network is equivalently hooked to the same load R opt at both ends, to ensure that the energy transmission between the ports is maximized, it is known from the conjugate matching principle that the compensation network needs to have a symmetrical property (a=d), and then the susceptance b of the parallel element jb is equal to the product of the angular frequency ω and C out in value, and the undetermined design network N s is also necessarily symmetrical and accordingly defines the 4 parameters of the transmission matrix thereof as a 1、B1、C1 and a 1 in sequence. If the effect of the parallel parasitic capacitance C out is perfectly compensated, the rf amplified signal is transferred from the VCCS end to the input side of the matching network without any mismatch loss, and the transistor sees the required R opt, i.e. Z out＝Zmn＝Ropt, the following relation is given:
equation (5) holds if and only if constraint (7) or (8) is satisfied.
R=C=0 (7)
In summary, the transmission matrix of the compensation network specifically achieves:
Known b=ωc out, the finishing yields:
A=A1+jB1b
B=B1
C=j2A1b-B1b2+C1 (10)
Let constraints (7) and (8) be further equivalent to:
B1＝j2A1b-B1b2+C1=0 (11)
Thereby obtaining the design parameters of the network N s to be designed.
3 Embodiments are given below, each based on R opt and C out, which are 26 Ω and 0.27pF, respectively, so that those skilled in the art can better understand the present invention and make reasonable use and expansion.
1) The lumped low-pass compensation network, N s is a series inductor;
when the simplest series inductance L s is selected to implement N s, as shown in fig. 3, there are:
A1=1
B1＝jωLs
C1=0 (13)
Substituting the data of equation (13) into constraints (11) and (12), and obtaining the result after finishing:
Obviously, equation (14) holds when ω=0, and in fact, at the direct current point, the parallel parasitic capacitance C out is equivalent to an open circuit without introducing any disturbance. Another compensation frequency point, here for example 32GHz, is custom-defined, and the series inductance L s can be found to be 122pH according to the analytical formula (15).
2) The distributed low-pass compensation network, N s is a section of series transmission line;
When the frequency is increased to the millimeter wave band, the lumped inductance is no longer suitable for implementation and needs to be replaced by a transmission line. In case 1), N s is replaced by a transmission line with characteristic impedance Z 01 and electrical length θ 1 at angular frequency ω, and the symmetrical parallel element of equivalent parallel parasitic capacitance C out is also approximated by an open transmission line with characteristic impedance Z 02 and electrical length θ 2 at angular frequency ω, as shown in FIG. 4, where:
substituting the data of equation (17) into constraints (11) and (12), and obtaining the result after finishing:
Since θ 1 can be further expressed as equation (20), where v p is the phase velocity and l 1 is the physical length of the transmission line, then it is known that relationship (18) holds when ω=0 in combination with equation (16).
In addition, to ensure the realizability of the network N s to be designed, the denominator of equation (19) must be positive, so that Z 01 must be chosen to be less than Z 01,min given by, for example, constraint (21).
Similarly, another compensation frequency point is customized, here for example, 32GHz, at which Z 01,min =15Ω, and assuming Z 01＝Z02 =50Ω is selected, θ 1 and θ 2 can be found to be 28.3 ° and 69.8 ° according to the analytical formulas (16) and (19), respectively.
Cases 1) and 2) of reflection coefficient Γ out and forward transmission coefficient S 21 between the two ends are shown in fig. 5 and 6, respectively, from which it is clearly reflected that the proposed compensation network can mitigate the effect of parallel parasitic capacitance C out over a full low-pass wide frequency range from DC to the specified 32GHz, and as designed, achieve conjugate matching at 0 and 32GHz to maximize energy transfer (Γ out＜＜0,S21 =0), the two frequencies being so-called perfect compensation points.
It should be mentioned that, to further expand the compensation bandwidth or enhance the compensation effect, the topology of the network N s to be designed may be complicated as required, such as a 3-element T-type L-C-L network. The number of elements can only be positive odd n, and (n+3)/2 perfect compensation points can be introduced due to the symmetrical structure. Therefore, except for the zero frequency point meeting the constraint condition (11), the (n+1)/2 perfect compensation points can be customized and substituted into the constraint condition (12), and the (n+1)/2 nonlinear equation sets can be established, so that the (n+1)/2 undetermined element parameters are obtained, and the design of the network N s to be designed is completed.
3) Lumped bandpass compensation network
Based on the low-pass compensation network design method and the filter theory, the band-pass compensation network can be obtained, and the band-pass compensation network is briefly described by taking the bandwidth of 22-32GHz as an example. The band-pass network is derived from a low-pass prototype, and the serial and parallel elements in the band-pass network are replaced by serial and parallel LC resonant networks resonating at the angular frequency omega 0, wherein omega 0 is the geometric average value of low and high side frequency points omega 1 and omega 2 of a design frequency band.
From the filter theory, the identity transformation between the low-pass and band-pass networks should satisfy the relation (23), where ω c is the corner frequency of the low-pass prototype network.
ωcL＝(ω2-ω1)L (23)
In other words, designing a band-pass type compensation network of 22-32GHz should first result in a low-pass type compensation network of DC-10GHz, and then be converted to a band-pass type by resonance, i.e. according to equation (23). The network topology and the component parameters are shown in fig. 7, and the corresponding frequency response characteristics are given in fig. 8 and 9.
The above embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention, so variations in shape and principles of the present invention should be covered.

Claims (4)

1. An impedance matching network topology design method for a broadband radio frequency amplifier is characterized by comprising the following steps:
Will be based on Simulation to obtain a series of optimal fundamental wave load impedance in broadbandEquivalent to parallel connectionA network model;
Based on parallel connection Network model, compressed by 1dB gain at pointOptimal fundamental wave load impedance obtained by simulationExtracting the optimal intrinsic load resistance practically requiredParasitic capacitance in parallel with;
Designing compensation network to reduce parallel parasitic capacitanceThe influence on impedance matching is caused so that the target of broadband impedance matching is from the optimal fundamental wave load impedance following the frequency variationTrace reduction to self-termination impedanceTo a constant optimal intrinsic load resistanceThe impedance transformation between single points of the (2) is performed so as to obtain the impedance matching network topology by a Smith chart track method;
Designing a compensation network, comprising:
a1, acquiring a transmission matrix of a compensation network;
a2, solving a solution of a transmission matrix when the signal reaches the matching network from the compensation network without loss;
A3, solving the network to be designed through the transmission matrix To obtain a compensation network;
The acquiring the transmission matrix of the compensation network comprises:
the compensation network is known to have symmetrical properties according to the conjugate matching principle, and then the transmission matrix of the compensation network is obtained according to the topology of the schematic diagram:
;
Wherein, the Is a parallel parasitic capacitanceIs used for the transmission matrix of the (c),Representing the imaginary number of the product,In order to be of an angular frequency,For networks to be designedIs used for the transmission matrix of the (c),Are all the design parameters of the device,Is thatThe transmission matrix of the parallel elements,Is susceptance;
when the signal reaches the matching network from the compensation network without loss, ,To compensate for the impedance of the network, terminalsFor the impedance after transformation by the matching network,In order to compensate the optimal intrinsic load resistance of the equivalent load of the two ends of the network, the following relation is provided:
;
;
Is the reflection coefficient;
parallel element Susceptance of (2)Equal in value to angular frequencyParasitic capacitance in parallel withThe product of (a), i.eThereby finishing to obtain:
。
2. The method of impedance matching network topology design of a wideband radio frequency amplifier of claim 1, wherein the impedance matching network topology design is based on an optimal fundamental load impedance Extracting the optimal intrinsic load resistance practically requiredParasitic capacitance in parallel withComprising:
From the center frequency point Where (a)Deriving the optimal intrinsic load resistance required for the transistor in the P1dB state by back-steppingParasitic capacitance in parallel with itselfThe formula is as follows:
;
;
In the above-mentioned method, the step of, In order to take the real part function,In order to take the function of the imaginary part,To take outIs a conjugate of (c).
3. The method for designing an impedance matching network topology of a broadband radio frequency amplifier according to claim 1, wherein the condition for establishment of the relation comprises:
if and only if the constraint is satisfied Or (b)Equation of timeThis is true.
4. The method for designing an impedance matching network topology of a broadband radio frequency amplifier according to claim 1, wherein the network to be designed is obtained by solving a transmission matrixWhen the design parameters of (a) are obtainedIn the case of (a), constraint conditions are to be satisfiedAndThe equivalent is respectively:、 thereby obtaining the network to be designed Is set, and the design parameters of (a) are set.
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CN115186588A (en) * 2022-07-12 2022-10-14 杭州电子科技大学 Power amplifier design method based on multi-objective particle swarm optimization

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