CN116346035B

CN116346035B - Annular RC oscillating circuit

Info

Publication number: CN116346035B
Application number: CN202310289374.9A
Authority: CN
Inventors: 毛洪卫; 赵显西; 勇智强
Original assignee: Beijing Jialyu Electronic Co ltd
Current assignee: Beijing Jialyu Electronic Co ltd
Priority date: 2023-03-23
Filing date: 2023-03-23
Publication date: 2024-02-09
Anticipated expiration: 2043-03-23
Also published as: CN116346035A

Abstract

The application discloses annular RC oscillation circuit includes: the ring oscillation circuit is used for generating an oscillation clock signal, the enabling input end of the ring oscillation circuit is connected with the enabling signal, the output end of the phase inverter is one path of oscillation clock signal output end, and the other path of phase-delay phase-inversion clock signal output end is connected with one path of input end of the forced charge-discharge circuit; the two signal input ends of the forced charge-discharge circuit are respectively connected with an oscillation clock signal and a delayed reverse clock signal which are output by the ring oscillation circuit, and the output ends of the forced charge-discharge circuit are connected with the charging voltage of the ring oscillation circuit; and the power supply input end of the output shaping circuit is connected with the power supply voltage, the signal input end of the output shaping circuit is connected with the oscillation clock signal output by the ring oscillation circuit, and the output end of the output shaping circuit outputs a final clock signal. The annular RC oscillation circuit provided by the embodiment of the application can overcome the problems that the existing annular RC oscillator is not full-swing oscillation and is difficult to stabilize the oscillation frequency, and solves the technical problem under the condition that the complexity of the circuit is not increased.

Description

Annular RC oscillating circuit

Technical Field

The application relates to the technical field of integrated circuits, in particular to a ring RC oscillating circuit.

Background

Clock generation circuitry is an integral part of modern integrated circuit systems. In electronic engineering design, a high-precision clock circuit is generally generated by an external crystal oscillator, and under the application of not very high requirements on clock signals, the clock signals are mainly generated by an on-chip oscillator circuit, and a ring oscillator is widely applied to circuit design due to simple structure and low power consumption, but has obvious defects, an internal node is similar to sine wave oscillation and is not full swing oscillation, so that the frequency is uncontrollable, and the current starvation type ring oscillation and relaxation oscillation structure increases the complexity and the power consumption of the circuit due to the requirement of additional reference charging current or reference voltage, a comparator and the like.

Disclosure of Invention

The embodiment of the application provides a ring RC oscillation circuit, which is used for solving the problems that the existing ring RC oscillator is not full-swing oscillation and is difficult to stabilize the oscillation frequency, and solves the problems under the condition of not increasing the complexity of the circuit.

The embodiment of the application provides a ring RC oscillating circuit, which comprises:

the ring oscillation circuit is used for generating an oscillation clock signal, the power supply input end of the ring oscillation circuit is connected with a power supply voltage, the enabling input end of the ring oscillation circuit is connected with an enabling signal, the output end of the phase inverter is an oscillation clock signal output end which is connected with the signal input end of the output shaping circuit and one input end of the forced charge and discharge circuit, the other phase of the ring oscillation circuit is connected with one input end of the forced charge and discharge circuit, and the charging voltage of the oscillator is a signal input end and is connected with the output end of the forced charge and discharge circuit;

the power supply voltage of the forced charge-discharge circuit is connected with the power supply input end, the two signal input ends are respectively connected with an oscillation clock signal and a delayed reverse clock signal which are output by the ring oscillation circuit, the output end of the forced charge-discharge circuit is connected with the charging voltage of the ring oscillation circuit, and the forced charge-discharge circuit is used for forcedly filling or discharging charges into the ring oscillation circuit at the clock reverse edge so that the charging voltage of the ring oscillation circuit is full in swing between the power supply voltage and the signal ground;

and the power supply input end of the output shaping circuit is connected with the power supply voltage, the signal input end of the output shaping circuit is connected with the oscillation clock signal output by the ring oscillation circuit, and the output end of the output shaping circuit outputs a final clock signal.

Optionally, the ring oscillation circuit includes an RC delay circuit, where the RC delay circuit includes a second PMOS transistor P2, a second NMOS transistor N2, an eighth PMOS transistor P8, a first resistor R1, and a first capacitor C1, where:

the source electrode of the eighth PMOS tube P8 is connected with the power supply voltage VDD, the grid electrode of the eighth PMOS tube P8 is connected with an enabling signal, and the drain electrode of the eighth PMOS tube P8 is connected to the source electrode of the second PMOS tube P2;

the grid electrode of the second PMOS tube P2 is connected with the grid electrode of the second NMOS tube N2, and the drain electrode of the second PMOS tube P2 is connected with the drain electrode of the second NMOS tube N2;

the source electrode of the second NMOS transistor N2 is grounded, and the drain electrode thereof is grounded through the series connection of the first resistor R1 and the first capacitor C1.

Optionally, the ring oscillation circuit further includes: the first PMOS pipe P1, the first NMOS pipe N1, the third PMOS pipe P3, the third NMOS pipe N3, the eighth NMOS pipe N8 and the second capacitor C2, wherein:

the source electrode of the first PMOS tube P1 is connected with the power supply voltage VDD, the grid electrode of the first PMOS tube P1 is connected with the grid electrode of the first NMOS tube N1, and the drain electrode of the first PMOS tube P1 is connected to the drain electrode of the first NMOS tube N1;

the source electrode of the first NMOS tube N1 is grounded, the drain electrode of the first NMOS tube N1 is grounded through the second capacitor C2, and the drain electrode of the first NMOS tube N1 outputs a delayed reverse clock signal;

the source electrode of the eighth NMOS tube N8 is grounded, the grid electrode is connected with an enabling signal, and the drain electrode is grounded through the first capacitor C1;

the source electrode of the third PMOS tube P3 is connected with the power supply voltage VDD, the grid electrode of the third PMOS tube P3 is connected with the grid electrode of the third NMOS tube N3, and the drain electrode of the third PMOS tube P3 is connected with the drain electrode of the third NMOS tube N3;

the source electrode of the third NMOS tube N3 is grounded, and the drain electrode of the third NMOS tube N3 outputs an oscillation clock signal.

Optionally, the forced charge-discharge circuit includes: a fourth NMOS tube N4-a seventh NMOS tube N7, a fourth PMOS tube P4-a seventh PMOS tube P7, wherein;

a source electrode of the fourth PMOS tube P4 is connected with the power supply voltage VDD, a grid electrode of the fourth PMOS tube P4 is connected with a grid electrode of the fourth NMOS tube N4 and connected with an oscillation clock signal, and a drain electrode of the fourth PMOS tube P5 is connected with a source electrode of the fifth PMOS tube P5;

the grid electrode of the fifth PMOS tube P5 is connected with the fifth NMOS tube N5 and is connected with a delayed reverse clock signal, the grid electrodes of the fifth PMOS tube P5 and the seventh NMOS tube N7 are also connected with the grid electrodes of the seventh PMOS tube P7 and the seventh NMOS tube N7, and the drain electrode of the fifth PMOS tube P5 is connected with the drain electrode of the fifth NMOS tube N5;

a source of the fifth NMOS transistor N5 is connected to a drain of the fourth NMOS transistor N4;

a source electrode of the fourth NMOS tube N4 is grounded;

a source electrode of the sixth PMOS tube P6 is connected with the power supply voltage VDD, a grid electrode of the sixth PMOS tube P6 is connected with a grid electrode of the sixth NMOS tube N6 and connected with an oscillation clock signal, and a drain electrode of the sixth PMOS tube P7 is connected with a source electrode of the seventh PMOS tube P7;

a seventh PMOS tube P7, the grid electrode of which is connected with the seventh NMOS tube N7 and is connected with a delayed reverse clock signal, and the drain electrode of which is connected with the drain electrode of the seventh NMOS tube N7;

a source of the seventh NMOS transistor N7 is connected to a drain of the sixth NMOS transistor N6;

and the source electrode of the sixth NMOS tube N6 is grounded.

Optionally, the output shaping circuit includes a first inverter and a second inverter connected in series, wherein after the first inverter is connected in series, an input end of the first inverter is connected to an oscillating clock signal, and an output end of the second inverter outputs a final clock signal.

The embodiment of the application also provides electronic equipment comprising the annular RC oscillating circuit.

In addition, the circuit adopts single-stage RC delay, so that the circuit structure is simplified, and the area of the circuit is effectively reduced.

The foregoing description is only an overview of the technical solutions of the present application, and may be implemented according to the content of the specification in order to make the technical means of the present application more clearly understood, and in order to make the above-mentioned and other objects, features and advantages of the present application more clearly understood, the following detailed description of the present application will be given.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

FIG. 1 is a schematic illustration of a conventional ring RC oscillator circuit;

FIG. 2 is an example of a conventional ring RC oscillator circuit key node simulation waveform;

FIG. 3 is an architecture example of a ring RC oscillating circuit of an embodiment of the present application;

fig. 4 is a circuit configuration example of a ring RC oscillation circuit of the embodiment of the present application;

fig. 5 is a simulation waveform example of a ring RC oscillating circuit according to an embodiment of the present application.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The conventional annular RC oscillation circuit is shown in fig. 1, and because of the structural limitation, an odd-level RC reverse-phase charge-discharge structure and at least three-level RC structure are needed, the simulation waveform diagram of key nodes is shown in fig. 2, and because of the unique charge-discharge property of the capacitor, 3-5 RC time constants are needed for charge and discharge to VDD and GND, and the three-level annular RC can only provide 1.5-scale RC, the simulation result shows that the intermediate potential swing is between 0.74 and 4V, the capacitor cannot be fully utilized, and the frequency is easy to change along with the power supply voltage.

An embodiment of the present application provides a ring RC oscillating circuit, as shown in fig. 3, including:

the ring oscillation circuit 308 is configured to generate an oscillation clock signal, the power input terminal of the ring oscillation circuit is connected to a power voltage, the enable input terminal is connected to an enable signal, the output terminal of the inverter is an output terminal of one path of oscillation clock signal 304, the ring oscillation circuit is connected to the signal input terminal of the output shaping circuit 310 and one path of input terminal of the forced charge/discharge circuit 309, the output terminal of the other path of delayed inversion clock signal 305 is connected to one path of input terminal of the forced charge/discharge circuit 309, and the oscillator charge voltage 306 is a path of signal input terminal and is connected to the output terminal of the forced charge/discharge circuit 309.

And the forced charge-discharge circuit 309, the power supply voltage of which is connected with the power supply input end, and the two signal input ends of which are respectively connected with the oscillation clock signal 304 and the delayed phase inversion clock signal 305 output by the ring oscillation circuit, and the output end of which is connected with the ring oscillation circuit charging voltage 306, is used for forcedly filling or discharging charges into the ring oscillation circuit at the clock inversion edge, so that the ring oscillation circuit 308 charging voltage is enabled to have full swing between the power supply voltage and the signal ground.

And the power supply input end of the output shaping circuit 310 is connected with the power supply voltage 301, the signal input end of the output shaping circuit is connected with the oscillation clock signal 304 output by the ring oscillation circuit 308, and the output end of the output shaping circuit outputs a final clock signal.

In some embodiments, the ring oscillator circuit includes an RC delay circuit 307, the RC delay circuit 307 includes a second PMOS transistor P2, a second NMOS transistor N2, an eighth PMOS transistor P8, a first resistor R1, and a first capacitor C1, wherein:

In some embodiments, the ring oscillator circuit 308 further comprises: the first PMOS pipe P1, the first NMOS pipe N1, the third PMOS pipe P3, the third NMOS pipe N3, the eighth NMOS pipe N8 and the second capacitor C2, wherein:

the source of the third NMOS transistor N3 is grounded, and the drain thereof outputs the oscillation clock signal 304.

In some embodiments, the forced charge-discharge circuit 309 comprises: a fourth NMOS tube N4-a seventh NMOS tube N7, a fourth PMOS tube P4-a seventh PMOS tube P7, wherein;

a source electrode of the fourth NMOS tube N4 is grounded;

and the source electrode of the sixth NMOS tube N6 is grounded.

In some embodiments, the output shaping circuit 310 includes a first inverter I1 and a second inverter I2 connected in series, wherein after the series connection, an input terminal of the first inverter I1 is connected to the oscillating clock signal, and an output terminal of the second inverter I2 outputs the final clock signal.

In the ring RC oscillating circuit of the embodiment of the present application, as shown in fig. 3 and fig. 4, when not enabled, enx=vdd, the enable control pipe P8 is turned off, the N8 is turned on, the nodes Vc and clkn_td are all discharged to GND, and the outputs clk and out are at high level, and the power consumption of the circuit is 0; in the enable case, enx=gnd, the enable pipe P8 is turned on, N8 is turned off, and under the influence of the node capacitances C1, C2, the level at which each node remains in the disabled state: clk=vdd, clkn_td=gnd, and vc=gnd, so N1, P2, P3, and P8 tubes in the ring oscillation circuit are on, and N2, N3, and P1 tubes are off. Because clk and clkn_td are in level inversion, the forced charge-discharge circuit has no conductive branches (four branches P4, P5, P6, P7, N4, N5;

n6, N7, the control signals of the two pipes on each branch are inverted, not conducted at the same time, no current is generated), and the current is zero. Therefore, VDD charges the main delay capacitor C1 through the paths P8, P2, and R1, and the voltage Vc of the upper plate of the capacitor gradually increases, satisfying the following formula:

charging: vflip=vdd [1-exp ] ^(-t1/RC) ](1)

Where Vfp is the flip threshold of the inverter consisting of P3, N3, which is VDD/2.

After the delay t1, the Vc potential is charged to Vflp to reach the inversion threshold, the clk signal is turned to GND, at the moment, N1 is cut off, P1 is conducted, the node clkn_td is pulled high, but because of the small delay capacitor C2, the clkn_td is still kept at a low level within a small period of time after the falling edge of the clk signal, at the moment, the forced charge and discharge circuit is in phase as the two control signals clkn_td are in GND, so that the two paths of charge branches P4 and P5 are realized; p6 and P7 are conducted, and discharge branches N4 and N5 are connected; n6 and N7 are turned off, the power supply VDD is charged with large current by the charging path, vc potential is forcedly charged from Vflip to VDD, and the partial delay is negligible due to the large current. After a small delay caused by C2, the clkn_td signal becomes VDD, the clk and clkn_td levels become inverted signals, and the four forced charge and discharge branches are all turned off. N2, N3, P1 pipe in the ring oscillation circuit is switched on, N1, P2, P3, P8 pipe is cut off, enter the discharge phase, vc discharges to GND through R1, N2, because Vc has been forced to charge to VDD, discharge phase satisfies the following formula:

discharge phase: vflip=vdd x exp ^(-t2/RC) (2)

After the delay t2, the Vc potential is discharged from VDD to Vflp, the inversion threshold is reached, the clk signal is inverted to VDD, at the moment, N1 is conducted, P1 is cut off, the node clkn_td is required to be pulled down, and the clkn_td is kept at a high level in a small period of time after the rising edge of clk due to the existence of a small delay capacitor C2, at the moment, the forced charge-discharge circuit is in phase due to two control signals clkn_td, and both control signals clkn_td are in phase and are VDD, so that two paths of discharge branches N4 and N5; n6 and N7 are conducted, and the charging paths P4 and P5 are connected; p6, P7 turn off, discharge the heavy current by this passageway, discharge Vc potential from Vflp to GND by force, after the small delay that C2 brought, clkn_td signal becomes GND, clk and clkn_td level become the reverse signal again at this moment, four way forced charge and discharge branch road turn off. In the ring oscillation circuit, a P2 tube is conducted, an N2 tube is cut off, a charging stage is entered, VDD charges a main delay capacitor C1 through P8, P2 and R1 paths, and each MOS tube returns to the stage before enabling charging.

The two processes are repeated to obtain a square wave signal clk with a certain frequency, the square wave signal clk is used as the input of an output shaping circuit, and the square wave signal clk is shaped by a two-stage inverter to obtain a clock signal with a certain driving capability to be output from OUT.

As described above, the full swing of the plate voltage Vc on the capacitor C1 between VDD and GND varies during the charge and discharge, and the solution is obtained by combining equation (1), equation (2) and vflip=vdd/2:

where f is the clock signal oscillation frequency. The theoretical output frequency of the oscillating circuit is irrelevant to the power supply voltage, and the influence of temperature on the oscillating frequency can be reduced by using resistors with different temperature characteristics in series.

Fig. 5 is a waveform diagram of a simulation of key nodes of a ring RC oscillating circuit provided in the embodiment of the present application, where the full swing of Vc is changed, and clkn_td has a delay of about 0.5us, so as to ensure that the forced charge and discharge functions can be completely completed. The area of a capacitor C1+C2+C3 in the traditional annular RC oscillation circuit is the same as that of a capacitor C1 in FIG. 4, but the middle level is changed at 0.74-4V, the delay is only 7.3us, the oscillation delay of the embodiment of the application is 10.0us, and the full swing is charged and discharged, so that the capacitance value of the capacitor is fully utilized, the circuit adopts single-stage RC delay, only one main delay capacitor is needed, and compared with the traditional three-stage annular oscillation circuit with three capacitors, the unnecessary capacitance isolation area is saved.

Compared with the traditional ring oscillation circuit, the frequency is stable, the theoretical output frequency of the oscillation circuit is irrelevant to the power supply voltage, the influence of temperature on the oscillation frequency can be reduced by using resistors with different temperature characteristics in series, and compared with the current starvation type ring oscillation and relaxation oscillation structure with stable oscillation frequency, the oscillation circuit has the advantages that additional reference charging current or reference voltage, a comparator and the like are not needed, and the circuit structure is simple and low in power consumption.

The full swing amplitude of the charging intermediate level of the oscillating circuit is changed between the power supply and the ground, the utilization rate of the capacitance value of the capacitor in the RC loop is improved, and compared with a traditional ring oscillator, the area of the capacitor required for reaching the same delay is reduced.

Compared with the traditional three-stage ring-shaped oscillating circuit with three capacitors, the oscillating circuit provided by the embodiment of the application adopts single-stage RC delay, only one main delay capacitor is needed, and unnecessary capacitor isolation area is saved.

It should be noted that, in the embodiments of the present disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the present application and the scope of the protection of the claims, which fall within the protection of the present application.

Claims

1. A ring RC oscillating circuit, comprising:

the power supply input end of the output shaping circuit is connected with the power supply voltage, the signal input end of the output shaping circuit is connected with the oscillation clock signal output by the ring oscillation circuit, and the output end of the output shaping circuit outputs a final clock signal;

the ring oscillation circuit comprises an RC delay circuit, wherein the RC delay circuit comprises a second PMOS tube P2, a second NMOS tube N2, an eighth PMOS tube P8, a first resistor R1 and a first capacitor C1, and the RC delay circuit comprises:

the source electrode of the second NMOS tube N2 is grounded, and the drain electrode of the second NMOS tube N2 is connected to one end of the first resistor R1;

the first capacitor C1 is connected between the drain electrode of the eighth NMOS tube N8 and the ground;

the ring oscillator circuit further includes: the first PMOS pipe P1, the first NMOS pipe N1, the third PMOS pipe P3, the third NMOS pipe N3, the eighth NMOS pipe N8 and the second capacitor C2, wherein:

the source electrode of the first PMOS tube P1 is connected with the power supply voltage VDD, the grid electrode of the first PMOS tube P1 is connected with the grid electrode of the first NMOS tube N1, and the drain electrode of the first PMOS tube P1 is connected with the drain electrode of the first NMOS tube N1, the grid electrode of the second PMOS tube P2 and the grid electrode of the second NMOS tube N2;

the source electrode of the first NMOS tube N1 is grounded, the drain electrode of the first NMOS tube N1 is grounded through the second capacitor C2, the drain electrode of the first NMOS tube N1 is connected to the grid electrode of the second PMOS tube P2 and the grid electrode of the second NMOS tube N2, and the drain electrode of the first NMOS tube N1 outputs a delayed reverse clock signal;

the source electrode of the eighth NMOS tube N8 is grounded, the grid electrode of the eighth NMOS tube N8 is connected with an enabling signal, the drain electrode of the eighth NMOS tube N8 is grounded through the first capacitor C1, and the drain electrode of the eighth NMOS tube N8 is used as an oscillator charging voltage and serves as a signal input end;

the source electrode of the third PMOS tube P3 is connected with the power supply voltage VDD, the grid electrode of the third PMOS tube P3 is connected with the grid electrode of the third NMOS tube N3, the grid electrode of the third PMOS tube P3 is also connected to the other end of the first resistor R1, and the drain electrode of the third PMOS tube P3 is connected to the drain electrode of the third NMOS tube N3;

the source electrode of the third NMOS transistor N3 is grounded, the gate electrode of the third NMOS transistor N3 is connected to the gate electrode of the third PMOS transistor P3, the other end of the first resistor R1, and the drain electrode of the eighth NMOS transistor N8, and the drain electrode thereof outputs an oscillation clock signal.

2. The ring RC oscillating circuit of claim 1, wherein the forced charge-discharge circuit comprises: a fourth NMOS tube N4-a seventh NMOS tube N7, a fourth PMOS tube P4-a seventh PMOS tube P7, wherein;

the grid electrode of the fifth PMOS tube P5 is connected with the fifth NMOS tube N5 and is connected with a delayed reverse clock signal, the grid electrodes of the fifth PMOS tube P5 and the seventh NMOS tube N7 are also connected with the grid electrodes of the seventh PMOS tube P7 and the seventh NMOS tube N7, and the drain electrodes of the fifth PMOS tube P5, the seventh PMOS tube P7, the seventh NMOS tube N7 and the eighth NMOS tube N8 are connected with the drain electrodes of the seventh NMOS tube P7 and the seventh NMOS tube N8;

a fifth NMOS tube N5, the source of which is connected to the drain of the fourth NMOS tube N4, the drain of which is connected to the drain of the fifth PMOS tube P5, the drain of the seventh PMOS tube P7, the drain of the seventh NMOS tube N7, and the drain of the eighth NMOS tube N8;

a source electrode of the fourth NMOS tube N4 is grounded;

and the source electrode of the sixth NMOS tube N6 is grounded.

3. The ring RC oscillating circuit of claim 1, wherein the output shaping circuit comprises a first inverter and a second inverter connected in series, wherein after the series connection, an input terminal of the first inverter is connected to an oscillating clock signal, and an output terminal of the second inverter outputs a final clock signal.

4. An electronic device comprising a ring RC oscillating circuit as claimed in any one of claims 1-3.