CN116015022A - Drive circuit and related control chip circuit, power adapter and electronic equipment - Google Patents

Abstract

The present application provides a driving circuit, a related control chip circuit, a power adapter and electronic equipment, the driving circuit includes: an operational amplifier circuit, a comparator, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first A PMOS transistor, a second PMOS transistor, a first drive control module, and a second drive control module, wherein the first resistor, the second resistor, and the first NMOS transistor are used to form an LDO negative feedback system. The embodiment of the present application can solve the EMI problem caused by the GaN power tube in the charging application and satisfy the accuracy requirement of the driving voltage of the GaN power tube.

Description

Drive circuit and related control chip circuit, power adapter and electronic equipment

technical field

The present application relates to the field of electronic technology, in particular to a drive circuit and related control chip circuits, power adapters and electronic equipment.

Background technique

With the advancement of technology and the continuous reduction of defect rate, the advantages of gallium nitride (GaN) in electronic power supplies for AC and DC power conversion, changing voltage levels, and ensuring reliable power supply with a certain number of functions are becoming more and more obvious.

Furthermore, in practical applications, GaN will be considered as the material of GaN power tubes. However, during the charging process, because GaN works at a higher frequency, there will be a large di/dt, which will cause serious electromagnetic waves. Electromagnetic interference (EMI), therefore, how to solve the EMI problem caused by the GaN power tube in the charging application needs to be solved urgently.

Contents of the invention

The embodiment of the present application provides a driving circuit, related control chip circuit, power adapter and electronic equipment, which can solve the EMI problem caused by the GaN power tube in the charging application and meet the accuracy requirement of the driving voltage of the GaN power tube.

In the first aspect, the embodiment of the present application provides a driving circuit, the driving circuit includes: an operational amplifier circuit, a comparator, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor tube, the first drive control module, and the second drive control module, wherein,

The non-inverting input end of the operational amplifier circuit is connected to the first power supply, the output end of the operational amplifier circuit is connected to the first end of the first NMOS transistor, and the third end of the first NMOS transistor is connected to the second power supply, so The second end of the first MOS transistor is connected to one end of the first resistor, and the other end of the first resistor is connected to the inverting input end of the operational amplifier circuit and grounded through the second resistor;

The non-inverting input terminal of the comparator is connected to the third power supply, the output terminal of the comparator is connected to the first input terminal of the OR gate circuit, the second input terminal of the OR gate circuit is used to access the driving signal, and the driving The signal is also input into the first end of the first drive control module;

The output end of the OR gate circuit is connected to the first end of the second drive control module, and the second end of the second drive control module is connected to the first end of the second PMOS transistor; the first end of the second PMOS transistor The two ends are connected to the second end of the first PMOS transistor and the second end of the second NMOS end, the third end of the second PMOS transistor is connected to a driving port, and the driving port is used to drive a GaN power transistor; The third end of the second NMOS transistor is also connected to one end of the third resistor, and the other end of the third resistor is connected to one end of the fourth resistor and the inverting input end of the comparator;

The first end of the second NMOS transistor is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to the first end of the first NMOS transistor and grounded through the first capacitor; the second NMOS transistor the third end of which is connected to the second power supply;

The second end of the first drive control module is connected to the first end of the first PMOS transistor, and the third end of the first drive control module is connected to the first end of the third NMOS transistor and the second end of the second NMOS transistor. The third end of the drive control module, the third NMOS transistor is connected to the third end of the second PMOS transistor, and the second end of the third NMOS transistor is grounded.

In a second aspect, an embodiment of the present application provides a control chip circuit, and the control chip circuit includes the driving circuit as described in the first aspect above.

In a third aspect, an embodiment of the present application provides a power adapter, the power adapter includes the drive circuit described in the first aspect, or the control chip circuit described in the second aspect.

In the fourth aspect, the embodiment of the present application provides an electronic device, the electronic device includes the driving circuit as described in the first aspect, or, the control chip circuit as described in the second aspect, or, as described in the third aspect power adapter.

Implementing the embodiment of the present application has the following beneficial effects:

It can be seen that in the driving circuit, chip control circuit, power adapter and electronic equipment described in the embodiments of the present application, the driving circuit includes: an operational amplifier circuit, a comparator, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first drive control module, and a second drive control module, wherein the non-inverting input end of the operational amplifier circuit is connected to the first power supply, and the output end of the operational amplifier circuit is connected to the first NMOS transistor The first end of the first NMOS transistor is connected to the second power supply, the second end of the first MOS transistor is connected to one end of the first resistor, and the other end of the first resistor is connected to the inverting input end of the operational amplifier circuit and through The second resistor is grounded; the non-inverting input terminal of the comparator is connected to the third power supply, the output terminal of the comparator is connected to the first input terminal of the OR gate circuit, and the second input terminal of the OR gate circuit is used to access the drive signal, and the drive signal is also It is input to the first end of the first drive control module, the output end of the OR gate circuit is connected to the first end of the second drive control module, and the second end of the second drive control module is connected to the first end of the second PMOS transistor; the second The second end of the PMOS transistor is connected to the second end of the first PMOS transistor and the second end of the second NMOS end, the third end of the second PMOS transistor is connected to the drive port, and the drive port is used to drive the GaN power transistor; the second NMOS transistor The third end is also connected to one end of the third resistor, the other end of the third resistor is connected to one end of the fourth resistor and the inverting input end of the comparator, the first end of the second NMOS transistor is connected to one end of the fifth resistor, and the fifth resistor The other end of the first NMOS transistor is connected to the first end of the first NMOS transistor and grounded through the first capacitor; the third end of the second NMOS transistor is connected to the second power supply, and the second end of the first drive control module is connected to the first end of the first PMOS transistor. end, the third end of the first drive control module is connected to the first end of the third NMOS transistor and the third end of the second drive control module, the third NMOS transistor is connected to the third end of the second PMOS transistor, the third NMOS transistor The second terminal is grounded. According to the driving requirements of GaN devices, the control method of LDO operational amplifier clamping the upper limit of the output driving voltage can be used to ensure that the upper line of the output driving voltage is strictly clamped at about 6V. At the same time, the EMI effect is improved by using the method of detecting the magnitude of the output driving voltage and driving in two stages.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present application. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of an NMOS transistor provided in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a PMOS transistor provided in an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a driving circuit provided in an embodiment of the present application;

FIG. 4 is another structural schematic diagram of a driving circuit provided by an embodiment of the present application;

FIG. 5 is another structural schematic diagram of a driving circuit provided by an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a drive control circuit provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of another driving control circuit provided by an embodiment of the present application;

FIG. 8 is a schematic waveform diagram of signals based on the driving circuit in FIG. 5 provided by the embodiment of the present application.

Detailed ways

In order for those skilled in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only the present invention. Some, but not all, embodiments of the application. Based on the description of the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative efforts fall within the protection scope of the present application.

The terms "first", "second" and the like in the specification and claims of the present application and the above drawings are used to distinguish different objects, rather than to describe a specific order. Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, software, product, or device that includes a series of steps or units is not limited to the listed steps or units, but also includes steps or units that are not listed, or includes , other steps or units inherent in the product or equipment.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments.

The following describes the embodiments of the present application in conjunction with the accompanying drawings. In the drawings, dots at the intersections of intersecting conductors indicate that the conductors are connected, and no dots at the intersections indicate that the conductors are not connected.

In order to better understand the solutions of the embodiments of the present application, the following first introduces related terms and concepts that may be involved in the embodiments of the present application.

GaN devices: With low on-resistance and high operating frequency, it can meet the requirements of next-generation electronic equipment for higher power, higher frequency, smaller volume and harsher high-temperature operation of power devices. The overall performance of GaN power components is better, and it can be epitaxially grown on a silicon substrate. In terms of area and overall cost, it is also more cost-effective than silicon carbide components, so it is also used in high-power, high-frequency semiconductor components. .

With the advancement of technology and the continuous reduction of defect rate, the advantages of GaN in electronic power supplies for AC and DC power conversion, changing voltage levels, and ensuring reliable power supply with a certain number of functions are becoming more and more obvious. Power designers are rethinking circuit design, trying to find ways to create power systems that can take full advantage of the potential of the new GaN transistors without negative side effects. The usual way of thinking about these kinds of problems is to look for solutions in existing components—GaN switches, Si switch drivers, high-speed switch controllers, and parts in the overall design such as power inductors, transformers, and capacitors. Integrated circuit (IC) manufacturers producing power products can greatly expand power supply design possibilities if they can provide system-level solutions with co-designed devices, or even integrate multiple chips in a module package.

Compared with silicon Si-based power electronic devices, GaN-based power electronic devices have the following three advantages:

1. High efficiency and energy saving: Due to the unique polarization characteristics of GaN materials, there is a strong polarization effect between AlGaN/GaN heterojunctions, forming a high-concentration two-dimensional electron gas (2DEG) with a mobility as high as 2000 and an areal density as high as an order of magnitude. ). The GaN-based power switching device HFET uses AlGaN/GaN heterojunction 2DEG to work. The device has the advantages of small on-resistance and fast switching speed, which greatly reduces the on-state loss and switching of the device.

2. Miniaturization, light weight and low cost of power electronic devices: GaN material has a larger band gap than Si, so that GaN devices can work in a higher temperature environment, so the heat dissipation device can be simplified or even omitted. In addition, because the GaN device has a high switching frequency, the volume of the passive device capacitance and inductance of the system is greatly reduced. All of these make the GaN-based power electronic device more miniaturized and lightweight, greatly reducing the system manufacturing cost.

3. High output power density and strong driving force: Due to the characteristics of wide bandgap and other characteristics, the critical breakdown electric field of GaN material is as high as 3.4MV/cm, which is 10 times that of Si material. Therefore, GaN devices have higher withstand voltage capability. At the same time, GaN-based devices work with 2DEG to obtain low on-resistance and high current density, so that GaN devices can obtain greater power density.

Compared to silicon MOSFETs, Gallium Nitride-based Field Effect Transistors (GaN) operate much faster at lower gate threshold voltages. In addition, for the lower internal gate resistance of GaN FETs, the reverse recovery characteristics of the body diode are much better than those of silicon MOSFETs. GaNFETs have some output capacitance, but it's significantly lower than silicon. In practice, GaN transistors have lower resistance (RDS(ON)) and gate charge QG. What's more, GaN transistors are not subject to strong negative temperature coefficients like MOSFETs. Therefore, the driving requirements for a GaN FET, whether it is normal or off, will be completely different from that of a silicon MOSFET.

Compared with the traditional Si driver, the GaN driver circuit drives the switching frequency higher, requires lower driving voltage, and has higher efficiency. For power supply designers, factors to consider when driving GaN devices:

(1), low threshold voltage

The threshold voltage of GaN FET is generally lower than 1.5V, the minimum value is as low as 0.7V, which is lower than that of many MOSFETs, but it changes almost smoothly with temperature.

(2) The upper limit of the gate-source voltage is strictly required: VGS(MAX)=6V. On the one hand, VGS must be set below 5.5V to reserve a safety margin of 0.5V. On the other hand, it can be seen from the curve of Rds(ON) and VGS that when VGS=4.5-5.5V, RDS(ON) can reach the minimum value, which means that the conduction loss is reduced. All things considered, set VGS at 5V. Problems caused by the gate-source voltage design requirements: the gate-source voltage must be strictly controlled to avoid damage to the gate of the GaN FET power tube, and the common bias suitable for driving MOSFETs cannot be used directly.

(3), EMI problem

Since GaN can work at a higher frequency, there is a larger dV/dt. This will cause serious EMI problems.

In addition, in the embodiment of the present application, as shown in FIG. 1 , for the NMOS transistor, the first end of the NMOS transistor is the gate, the second end is the source, the third end is the drain, the fourth end is the substrate, and the first end is the substrate. The four terminals are grounded; as shown in Figure 2, for the PMOS transistor, the first end of the PMOS transistor is the gate, the second end is the source, the third end is the drain, the fourth end is the substrate, and the fourth end is used for Connect to the power supply, such as VDD; for the drive control module, the first terminal is DR, the second terminal is DU, and the third terminal is DW.

In the related art, as shown in FIG. 3 , FIG. 3 is a drive control circuit of a conventional drive, and its drive modules are driven step by step through an inverter chain. The output voltage drives an external MOS power transistor. The external MOS power transistor has a non-negligible capacitance between the gate and the source. In order to quickly turn on or turn off the drain current, a larger current is required to drive the gate voltage up or down. The drive adopts a one-stage control method. When the Drive signal is 0, the gate voltage of the NMOS transistor N1 is high. At the same time, N1 is turned on to output a large current, and the GATE voltage becomes higher instantly; similarly, when the Drive signal is 1, the NMOS transistors N2 and N3 are turned on, and the GATE voltage is pulled down instantly.

Among them, the disadvantage of the drive circuit shown in Figure 1 is that the drive adopts a one-stage control mode, and the di/dt changes during the switching process are large, resulting in poor EMI effects. At the same time, the output voltage is limited by the VCC voltage, the highest is VCC-VGS, and the output voltage changes with the change of VCC, which is unfavorable for the GaN drive tube. If you want to use this driver, you need to add an additional circuit to control VCC, which increases the cost.

Further, Fig. 4 is the drive circuit of the resonant drive schematic diagram, the core idea is to add an LC resonant circuit to the drive circuit, and use the parasitic capacitance inside the switch tube to resonate with the external inductance to realize the drive of the switch tube, and store in The energy in the resonant inductor is effectively recovered, thereby reducing the driving loss. However, the control circuit is complicated, and an additional circuit needs to be added to control VCC, and the resonant drive can only exert its advantages in ultra-high frequency applications. Not applicable for flyback configurations.

Furthermore, based on the defects of the above-mentioned related technologies, the embodiments of the present application provide a driving circuit, a chip control circuit, a power adapter and an electronic device for solving the above-mentioned defects.

Please refer to FIG. 5. FIG. 5 is a schematic structural diagram of a driving circuit provided by an embodiment of the present application. The driving circuit includes: an operational amplifier circuit OP1, a comparator CMP1, a first NMOS transistor MN1, a second NMOS transistor MN2, a Three NMOS transistors MN3, the first PMOS transistor MP1, the second PMOS transistor MP2, the first drive control module CTRL1, and the second drive control module CTR2, wherein,

The non-inverting input terminal (+) of the operational amplifier circuit OP1 is connected to the first power supply S1, the output terminal of the operational amplifier circuit OP1 is connected to the first end of the first NMOS transistor MN1, and the first terminal of the first NMOS transistor MN2 The three terminals are connected to the second power supply VDD, the second terminal of the first MOS transistor MN1 is connected to one terminal of the first resistor R1, and the other terminal of the first resistor R1 is connected to the inverting input terminal of the operational amplifier circuit OP1 (- ) and grounding through the second resistor R2;

The non-inverting input terminal (+) of the comparator CMP1 is connected to the third power supply S2, the output terminal of the comparator CMP1 is connected to the first input terminal of the OR gate circuit, and the second input terminal of the OR gate circuit is used to access a drive signal Drive_P, the drive signal Drive_P is also input to the first terminal of the first drive control module CTRL1;

The output end of the OR gate circuit is connected to the first end of the second drive control module, and the second end of the second drive control module is connected to the first end of the second PMOS transistor MP2; the second PMOS transistor MP2 The second end of the first PMOS transistor MP1 is connected to the second end of the second NMOS end MN2, the third end of the second PMOS transistor MN2 is connected to the drive port GATE, and the drive port GATE Used to drive a GaN power transistor; the third end of the second NMOS transistor MN2 is also connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to one end of the fourth resistor R4 and the inverting phase of the comparator CMP1 input (-);

The first end of the second NMOS transistor MN2 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the first end of the first NMOS transistor NM1 and grounded through the first capacitor C1; The third end of the second NMOS transistor MN2 is connected to the second power supply VDD;

The second end of the first drive control module CTRL1 is connected to the first end of the first PMOS transistor MP1, the third end of the first drive control module CTR1 is connected to the first end of the third NMOS transistor MN3 and The third end of the second drive control module CTR2 and the third NMOS transistor MN3 are connected to the third end of the second PMOS transistor MP2, and the second end of the third NMOS transistor MN3 is grounded.

Wherein, R1 and R2 can be replaced with a variable resistor, and the ratio between R1 and R2 can be adjusted through the variable resistor. R3 and R4 can also be replaced with a variable resistor, through which the ratio between R3 and R4 can be adjusted.

Optionally, the operational amplifier circuit OP1, the first resistor R1, the second resistor R2, and the first NMOS transistor MN1 are used to form an LDO negative feedback system;

The negative feedback system is used to dynamically adjust the current of the first NMOS transistor MN1 through the ratio between the first resistor R1 and the second resistor R2, and the operational amplifier circuit OP1, so as to obtain the the first output voltage V1 of the second terminal of the first NMOS transistor MN1;

When the first output voltage V1 is less than the first output voltage design value, the output of the operational amplifier circuit OP1 becomes high, the current passing through the first NMOS transistor NM1 increases, and the first output voltage V1 increases;

Conversely, when the first output voltage is greater than the first output voltage design value, the output of the operational amplifier circuit becomes low, the current passing through the first NMOS transistor decreases, and the first output voltage decreases, thereby realizing and dynamically adjusting the first output voltage of the second terminal of the first NMOS transistor.

Wherein, the first design value of the output voltage may be preset or defaulted by the system, for example, the first design value of the output voltage may be a set value, that is, an empirical value.

Optionally, the absolute value of the difference between the second output voltage V2 of the second terminal of the second NMOS transistor MN2 and the first output voltage V1 is smaller than a preset threshold.

Wherein, the preset threshold may be preset or defaulted by the system, and the preset threshold may be close to 0, for example, the preset threshold is 0.01.

Optionally, the first output voltage V1 is determined by the input voltage VREF of the non-inverting input terminal (+) of the operational amplifier circuit OP1, the first resistor R1 and the second resistor R2. The specific calculation formula is as follows:

V1＝VREF*(R1+R2)/R2

Optionally, the second output voltage V2 is determined by the input voltage VREF of the non-inverting input terminal (+) of the operational amplifier circuit OP1, the first resistor R1 and the second resistor R2, and the specific calculation formula is as follows:

V2＝VREF*(R1+R2)/R2

Optionally, the drive signal Drive_P is used to turn on the first PMOS transistor MP1 through the first drive control module CTRL1, and turn off the third NMOS transistor MN3, through the third resistor R3 and the first The four resistors R4 divide the voltage to obtain the third output voltage VO_ADOPT, and use the third output voltage VO_ADOPT as the first input signal of the inverting input terminal (-) of the comparator CMP1, and use the non-inverting input of the comparator CMP1 Compare the second input signal of terminal (+) to obtain a drive control signal; pass the drive control signal and the drive signal Drive_P through an OR gate circuit to obtain an output signal, and turn on the second PMOS transistor through the output signal, Charged simultaneously by the first PMOS transistor MP1 and the second PMOS transistor MP1.

Optionally, the first drive control module CTRL1 includes M inverters, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a third PMOS transistor MP3, and a fourth PMOS transistor MP4, where M is an even number;

The first end of the first drive control module CTRL1 is connected to the second end of the first drive control module CTRL1 and the first end of the fifth NMOS transistor MN5 through the M inverters; The second end of the NMOS transistor MN5 is grounded;

The first end of the first drive control module CTRL1 is connected to the first end of the fourth NMOS transistor MN4, the second end of the fourth NMOS transistor MN4 is grounded, and the third end of the fourth NMOS transistor MN4 is connected to One end of the sixth resistor R6, the other end of the sixth resistor R6 is connected to the third end and the first end of the third PMOS transistor MP3, and the first end of the third PMOS transistor MP3 is connected to the fourth PMOS transistor MP3 The first end of the tube MP4; the third end of the fourth PMOS transistor MP4 is connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is connected to the third end of the first drive control module CTRL1 and the The third end of the fifth NMOS transistor MN5; the second end of the third PMOS transistor MP3 and the second end of the fourth PMOS transistor MP4 are both connected to the second power supply VDD.

Specifically, as shown in FIG. 6 , in FIG. 6 , M=4, that is, four inverters are taken as an example for illustration, and the inverters are represented by triangles in the figure. On the one hand, the inverter can improve the driving ability, on the other hand, it can realize the delay effect.

Optionally, the second drive control module CTRL2 includes N inverters, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6, where N is an even number;

The first end of the second drive control module CTRL2 is connected to the second end of the second drive control module CTRL2 and the first end of the seventh NMOS transistor MN7 through the N inverters; the seventh The second end of the NMOS transistor MN7 is grounded;

The first end of the second drive control module CTRL is connected to the first end of the sixth NMOS transistor MN6, the second end of the sixth NMOS transistor MN6 is grounded, and the third end of the sixth NMOS transistor MN6 is connected to One end of the eighth resistor R8, the other end of the eighth resistor R8 is connected to the third end and the first end of the fifth PMOS transistor MP5, and the first end of the fifth PMOS transistor MP5 is connected to the sixth PMOS transistor MP5 The first end of the transistor MP6; the third end of the sixth PMOS transistor MP6 is connected to one end of the ninth resistor R9, and the other end of the ninth resistor R9 is connected to the third end of the second drive control module CTRL2 and the The third end of the seventh NMOS transistor MN7; the second end of the fifth PMOS transistor MP5 and the second end of the sixth PMOS transistor MP6 are both connected to the second power supply VDD.

Specifically, as shown in FIG. 7 , in FIG. 7 , N=4, that is, four inverters are taken as an example for illustration, and the inverters are represented by triangles in the figure. On the one hand, the inverter can improve the driving ability, on the other hand, it can realize the delay effect.

In the embodiment of the present application, due to the control of the OR gate circuit, the first drive control circuit and the second drive control circuit are respectively controlled to work in different periods, and then two-stage drive control is formed, and the two-stage drive control and LDO operational amplifier are used to clamp The upper limit technology of the output driving voltage not only improves the EMI, but also improves the precise value of the chip driving voltage, avoiding damage to the GaN device due to the fluctuation of the output voltage value. Furthermore, the effect of chip EMI can be improved on the basis of satisfying GaN driving requirements.

In specific implementation, the operational amplifier OP1, the resistors R1 and R2, and the NMOS tube MN1 form an LDO circuit.

For the above drive circuit, its specific working principle: LDO is a negative feedback system, using the ratio of R1 and R2, and the op amp to dynamically adjust the current through MN1, the precise value of the output voltage (V1) can be achieved. When the output voltage V1 is lower than the design value, the output of OP1 becomes high, the current through MN1 increases, and the output voltage V1 increases. When the output voltage V1 is greater than the design value, the output of OP1 becomes low, the current through MN1 decreases, and the output voltage V1 decrease. In this way, the voltage output of V1 is maintained at the design value. Similarly, the first ports of MN2 and MN1 are connected together, and the two are matched as much as possible, so that the output voltage V2 can be maintained at the design value, that is, V1 and V2 are equal or almost equal. The function of the capacitor C1 is to stabilize the voltage of the gate of the MOS transistor, reduce the bandwidth of the LDO, and increase the stability of the LDO system. At the same time, C1 and R5 form a low-pass filter, which can reduce the influence of the gate voltage of MN2 on the gate voltage of MN1.

Wherein, the above set value may be determined according to the driving voltage of the GAN power amplifier of the device to be driven.

In the specific implementation, the working principle of the two-stage drive is: first, the drive signal Drive_P passes through the drive control module CTRL1 (the circuit is shown in Figure 6), turns on MP1, turns off MN3, and increases the output voltage. Then, divide the voltage through resistors R3 and R4 to sample the output voltage. The sampled output voltage is compared with the reference voltage VREF1 by the comparator CMP1 to output 2-stage drive control signals. Then it is ORed with the signal Drive_P, PM2 is turned on through the control module CTRL2, and finally MP1 and MP2 give charging at the same time. In this way, the driving current changes from small to large, and the driving voltage has a slow and gradual process from low to high. Reduced di/dt spike and improved EMI effect.

In the embodiment of this application, according to the driving requirements of the GaN device, the control method of clamping the upper limit of the output driving voltage of the LDO operational amplifier is adopted to ensure that the upper line of the output driving voltage is strictly clamped at about 6V. At the same time, the EMI effect is improved by using the method of detecting the magnitude of the output driving voltage and driving in two stages. That is, it can meet the driving requirements of GaN, so that the output driving voltage can be well maintained at 6V, avoiding damage to GaN caused by output voltage fluctuations, and improving the effect of chip EMI. Compared with the driving circuit shown in Figure 5, the driving circuit shown in Figure 5 has a smaller EMI and lower cost in the embodiment of the present application; the driving circuit shown in Figure 5 is compared with the driving circuit shown in Figure 4, The embodiment of the present application has lower EMI and is applicable to a flyback structure.

Wherein, both the first power supply and the third power supply can be AC/DC power supply, DC/DC power supply, regulated power supply, communication power supply, module power supply, variable frequency power supply, inverter power supply, AC regulated power supply, DC regulated power supply, etc. This embodiment of the present application does not limit it. The first power supply and the second power supply may be the same power supply or different power supplies.

Further, the GaN power tube is used to output to the electric device to charge the electric device. The electric device can be understood as a device that needs to be charged by the user. The user device can include but not limited to: smart phones, tablet computers, Smart robots, smart elevators, in-vehicle devices, wearable devices, smart home devices, computing devices or other processing devices connected to wireless modems, and various forms of user equipment (user equipment, UE), mobile station (mobile station, MS ), terminal device (terminaldevice) and so on.

In the specific implementation, as shown in Figure 8, which shows the waveform diagram of Drive_P, DU1, DU2 and GATE signals, it can be seen that the driving current can be changed from small to large, and the driving voltage has a slow gradient from low to high the process of. Reduced di/dt spike and improved EMI effect.

Further, the above driving circuit can be applied to a control chip circuit, and the control chip circuit can include at least one of the following: AC-DC chip control circuit, DC-DC chip control circuit, which is not limited here, AC-DC chip control circuit It can be a flyback AC-DC chip control circuit or a non-flyback AC-DC chip control circuit.

In this way, in the specific implementation, the two-stage drive control and LDO operational amplifier clamp output drive voltage upper limit technology are used, which not only improves EMI, but also improves the precise value of the chip drive voltage, avoiding damage to GaN devices due to fluctuations in output voltage values . For example, the driver is used in the flyback ACDC control chip circuit to realize the driving of the GaN power tube.

Still further, both the above-mentioned drive circuit and the above-mentioned control chip circuit can be applied to a power adapter.

Certainly, the embodiment of the present application also provides an electronic device, which may include a drive circuit or a chip control circuit or a power adapter as described in FIG. 5 , for example, the electronic device may be a power bank or a charger.

The above is the implementation of the embodiment of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the embodiment of the present application, some improvements and modifications can also be made. These improvements and modifications are also It is regarded as the scope of protection of this application.

Claims (10)

1. A driving circuit, characterized in that the driving circuit comprises: the operational amplifier circuit, the comparator, the first NMOS tube, the second NMOS tube, the third NMOS tube, the first PMOS tube, the second PMOS tube, the first drive control circuit and the second drive control circuit, wherein,

the non-inverting input end of the operational amplifier circuit is connected with a first power supply, the output end of the operational amplifier circuit is connected with the first end of the first NMOS tube, the third end of the first NMOS tube is connected with a second power supply, and the second end of the first MOS tube is connected with the inverting input end of the operational amplifier circuit through a first resistor;

the non-inverting input end of the comparator is connected with a third power supply, the output end of the comparator is connected with the first input end of the OR gate circuit, the second input end of the OR gate circuit is used for being connected with a driving signal, and the driving signal is also input into the first end of the first driving control circuit;

the output end of the OR gate circuit is connected with the first end of the second drive control circuit, and the second end of the second drive control circuit is connected with the first end of the second PMOS tube; the second end of the second PMOS tube is connected with the second end of the first PMOS tube and the second end of the second NMOS tube, the third end of the second PMOS tube is connected with a driving port, and the driving port is used for driving the GaN power tube; the third end of the second NMOS tube is also connected with one end of a fourth resistor and the inverting input end of the comparator through a third resistor;

the first end of the second NMOS tube is connected with the first end of the first NMOS tube through one end of a fifth resistor and grounded through a first capacitor; the third end of the second NMOS tube is connected with the second power supply;

the second end of the first drive control circuit is connected with the first end of the first PMOS tube, the third end of the first drive control circuit is connected with the first end of the third NMOS tube and the third end of the second drive control circuit, the third NMOS tube is connected with the third end of the second PMOS tube, and the second end of the third NMOS tube is grounded.

2. The driving circuit of claim 1, wherein the op-amp circuit, the first resistor, the second resistor, the first NMOS transistor are configured to form an LDO negative feedback system;

the negative feedback system is used for dynamically adjusting the current of the first NMOS tube through the ratio between the first resistor and the second resistor and the operational amplifier circuit so as to obtain a first output voltage of the second end of the first NMOS tube;

when the first output voltage is smaller than a first output voltage design value, the output of the operational amplifier circuit becomes high, the current passing through the first NMOS tube is increased, and the first output voltage is increased;

conversely, when the first output voltage is greater than or equal to the first output voltage design value, the output of the operational amplifier circuit becomes low, the first output voltage is reduced through the current reduction of the first NMOS tube, and the first output voltage of the second end of the first NMOS tube is dynamically adjusted.

3. The drive circuit of claim 2, wherein an absolute value of a difference between a second output voltage of the second end of the second NMOS transistor and the first output voltage is less than a preset threshold.

4. A driving circuit according to claim 3, wherein the first output voltage is determined by an input voltage at a non-inverting input of the op-amp circuit, the first resistor and the second resistor;

and/or the second output voltage is determined by the input voltage of the non-inverting input end of the operational amplifier circuit, the first resistor and the second resistor.

5. The driving circuit according to any one of claims 1 to 4, wherein the driving signal is used for turning on the first PMOS transistor and turning off the third NMOS transistor through the first driving control circuit, dividing the voltage by the third resistor and the fourth resistor to obtain a third output voltage, using the third output voltage as a first input signal of an inverting input terminal of the comparator, and comparing a second input signal of a non-inverting input terminal of the comparator to obtain a driving control signal; and the driving control signal and the driving signal pass through an OR gate circuit to obtain an output signal, the second PMOS tube is started through the output signal, and the first PMOS tube and the second PMOS tube are charged simultaneously.

6. The drive circuit according to any one of claims 1 to 4, wherein the first drive control circuit includes M inverters, a fourth NMOS transistor, a fifth NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, M being an even number;

the first end of the first drive control circuit is connected with the second end of the first drive control circuit and the first end of the fifth NMOS tube through the M inverters; the second end of the fifth NMOS tube is grounded;

the first end of the first drive control circuit is connected with the first end of the fourth NMOS tube, the second end of the fourth NMOS tube is grounded, the third end of the fourth NMOS tube is connected with one end of a sixth resistor, the other end of the sixth resistor is connected with the third end and the first end of the third PMOS tube, and the first end of the third PMOS tube is connected with the first end of the fourth PMOS tube; the third end of the fourth PMOS tube is connected with one end of a seventh resistor, and the other end of the seventh resistor is connected with the third end of the first drive control circuit and the third end of the fifth NMOS tube; and the second end of the third PMOS tube and the second end of the fourth PMOS tube are both connected with the second power supply.

7. The drive circuit according to any one of claims 1 to 5, wherein the second drive control circuit includes N inverters, a sixth NMOS transistor, a seventh NMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor, the N being an even number;

the first end of the second drive control circuit is connected with the second end of the second drive control circuit and the first end of the seventh NMOS tube through the N inverters; the second end of the seventh NMOS tube is grounded;

the first end of the second driving control circuit is connected with the first end of the sixth NMOS tube, the second end of the sixth NMOS tube is grounded, the third end of the sixth NMOS tube is connected with one end of an eighth resistor, the other end of the eighth resistor is connected with the third end and the first end of the fifth PMOS tube, and the first end of the fifth PMOS tube is connected with the first end of the sixth PMOS tube; the third end of the sixth PMOS tube is connected with one end of a ninth resistor, and the other end of the ninth resistor is connected with the third end of the second drive control circuit and the third end of the seventh NMOS tube; and the second end of the fifth PMOS tube and the second end of the sixth PMOS tube are both connected with the second power supply.

8. A control chip circuit, characterized in that the control chip circuit comprises a drive circuit as described in any of claims 1-7.

9. A power adapter comprising a drive circuit as described in any one of claims 1-7 or a control chip circuit as described in claim 8.

10. An electronic device comprising a drive circuit as described in any of claims 1-7, or a control chip circuit as described in claim 8, or a power adapter as described in claim 9.

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