CN115762418B

CN115762418B - Pixel circuit, pixel circuit driving method and display device comprising pixel circuit

Info

Publication number: CN115762418B
Application number: CN202210917193.1A
Authority: CN
Inventors: 金仁准; 尹在熊
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2021-09-03
Filing date: 2022-08-01
Publication date: 2025-09-19
Anticipated expiration: 2042-08-01
Also published as: US11735116B2; CN115762418A; US20230073636A1

Abstract

In an embodiment, a pixel circuit, a method for driving the pixel circuit, and a display device including the pixel circuit are disclosed. According to the embodiment, the pixel circuit includes: a driving element including a first electrode connected to a first power line to which a pixel driving voltage is applied, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switching element including a first electrode connected to a second power line to which a data voltage is applied, a gate electrode to which a first scan pulse is applied, and a second electrode connected to the first node; a second switching element including a first electrode connected to the second power line; a gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node; a light-emitting element including an anode electrode connected to the second node and a cathode electrode connected to a third power line to which a low-potential power voltage is applied; and a capacitor connected between the first node and the second node.

Description

Pixel circuit, pixel circuit driving method and display device comprising pixel circuit

Cross Reference to Related Applications

The present application claims priority and benefit from korean patent application No. 10-2021-0110227 filed on 3 month 9 of 2021 and korean patent application No. 10-2021-0178245 filed on 14 month 12 of 2021, the disclosures of both of which are incorporated herein by reference in their entireties.

Technical Field

The present disclosure relates to a pixel circuit and a display device including the pixel circuit.

Background

Electroluminescent display devices are largely classified into inorganic light emitting display devices and organic light emitting display devices according to materials of light emitting layers. An active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter, referred to as "OLED") that emits light by itself, and has advantages of high response speed, high light emitting efficiency, and large luminance and viewing angle. In the organic light emitting display device, an OLED is formed in each pixel. The organic light emitting display device not only has a fast response speed, excellent light emitting efficiency, brightness, and viewing angle, but also has excellent contrast and color reproducibility since it can express black gray scale in full black.

The pixel circuit of the electroluminescent display device includes an OLED serving as a light emitting element and a driving element for driving the OLED.

The driving frequency applied to the electroluminescent display device is gradually increased. For example, when the driving frequency is increased from 120Hz to 240Hz, one horizontal period (1H) is shortened. When one horizontal period is shortened, the data charge rate in the pixel circuit may be reduced, which may cause a reduction in luminance. Therefore, a scheme capable of improving the data charge capability even in the case of increasing the driving frequency applied to the electroluminescent display device is required.

Disclosure of Invention

The present disclosure is directed to addressing all of the needs and problems set forth above.

The present disclosure provides a pixel circuit capable of improving data charge capability and a display device including the pixel circuit.

It should be noted that the objects of the present disclosure are not limited to the above-described objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

The pixel circuit according to an embodiment of the present disclosure may include a driving element including a first electrode connected to a first power line to which a pixel driving voltage is applied, a gate electrode connected to a first node, and a second electrode connected to a second node, a first switching element including a first electrode connected to a second power line to which a data voltage is applied, a gate electrode to which a first scan pulse is applied, and a second electrode connected to the first node, a second switching element including a first electrode connected to a second power line, a gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node, a light emitting element including an anode electrode connected to the second node, and a cathode electrode connected to a third power line to which a low potential power voltage is applied, and a capacitor connected between the first node and the second node.

According to the present disclosure, two switching elements turned on according to a gate-on voltage of a scan pulse are connected in parallel between a data voltage line and a gate node of a driving element, so that data charge capability can be improved even in the case of an increase in driving frequency.

According to the present disclosure, double data charge control can be achieved by adjusting the falling time of the scan pulse applied to the two switching elements, and thus the data charge rate can be improved.

The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be apparent to those skilled in the art from the following description and appended claims.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

fig. 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

fig. 2 is a view showing a sectional structure of the display panel shown in fig. 1;

fig. 3 is a circuit diagram showing a pixel circuit according to a first embodiment of the present disclosure;

fig. 4 is a circuit diagram showing a pixel circuit according to a second embodiment of the present disclosure;

Fig. 5A and 5B are waveform diagrams showing gate signals applied to the pixel circuit shown in fig. 4;

fig. 6A to 6D are circuit diagrams showing the operation of the pixel circuit shown in fig. 4 in stages;

Fig. 7A to 7G are diagrams describing a falling time of the second scan pulse;

fig. 8A to 8C are waveform diagrams showing gate signals applied to the pixel circuit shown in fig. 4;

Fig. 9 is a circuit diagram showing a pixel circuit according to a third embodiment of the present disclosure;

Fig. 10 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present disclosure, and

Fig. 11A and 11B are waveform diagrams showing a gate signal applied to the pixel circuit shown in fig. 10.

Detailed Description

The advantages and features of the present disclosure, as well as methods for practicing the present disclosure, will be more clearly understood from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but may be implemented in various different forms. Rather, the present embodiments will complete the disclosure of the present disclosure and enable one of ordinary skill in the art to fully understand the scope of the present disclosure. The present disclosure is limited only by the scope of the appended claims.

The shapes, sizes, ratios, angles, numbers, and the like shown in the drawings for describing embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference numerals generally refer to like elements throughout the specification. In addition, in describing the present disclosure, detailed descriptions of known related art may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

As used herein, terms such as "comprising," including, "" having, "and" consisting of "are generally intended to allow for the addition of other components unless the term is used with the term" only. Any reference to the singular may include the plural unless specifically stated otherwise.

The components are to be construed as including ordinary error ranges even if not explicitly stated.

When terms such as "on," above, "" below, "and" beside "are used to describe a positional relationship between two components, one or more components may be positioned between the two components unless these terms are used with the terms" immediately following "or" directly on.

The terms "first," "second," and the like may be used to distinguish one element from another, but the function or structure of the element is not limited by the serial number or element name preceding the element.

Like reference numerals may refer to substantially like elements throughout the present disclosure.

The following embodiments may be partially or fully combined with each other, and may be technically coupled and operated in various ways. Embodiments may be performed independently of each other or in association with each other.

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Each of the pixels is divided into a plurality of sub-pixels having different colors to realize the colors, and each of the sub-pixels includes a transistor serving as a switching element or a driving element. Such a transistor may be implemented as a Thin Film Transistor (TFT).

The driving circuit of the display device writes pixel data of an input image into pixels. The driving circuit of the flat panel display device includes a data driver for supplying a data signal to the data lines, a gate driver for supplying a gate signal to the gate lines, and the like.

In the display device of the present disclosure, the pixel circuit may include a plurality of transistors. The transistor may be implemented as a TFT having a Metal Oxide Semiconductor FET (MOSFET) structure, and may be an oxide TFT including an oxide semiconductor or a Low Temperature Polysilicon (LTPS) TFT including LTPS. Hereinafter, a transistor constituting a pixel circuit will be exemplarily described using an example implemented using an n-channel oxide TFT, but the present disclosure is not limited thereto.

A transistor is a three-electrode device that includes a gate, a source, and a drain. The source is an electrode that provides carriers to the transistor. In a transistor, carriers flow from the source. The drain is the electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flow is from drain to source. In the case of a P-channel transistor, since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a P-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain are not fixed in the transistor. For example, the source and drain may be changed according to the applied voltage. Accordingly, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as a first electrode and a second electrode.

The gate signal may swing between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor. The gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

The transistor is turned on in response to a gate-on voltage and turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be gate high voltages (VGH and VEH), and the gate-off voltage may be gate low voltages (VGL and VEL).

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described focusing on an organic light emitting display device, but the disclosed invention is not limited thereto.

Fig. 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure, and fig. 2 is a diagram illustrating a cross-sectional structure of the display panel illustrated in fig. 1.

Referring to fig. 1 and 2, a display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and a power supply device 140 for generating power required to drive the pixels and the display panel driver.

The display panel 100 may be a display panel having a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 comprises a pixel array AA displaying an input image. The pixel array AA includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines generally connected to the pixels. The power lines may include a power line to which the pixel driving voltage EVDD is applied, a power line to which the initialization voltage Vinit is applied, a power line to which the reference voltage Vref is applied, and a power line to which the low potential power voltage EVSS is applied. These power lines are typically connected to pixels.

The pixel array AA includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes one row of pixels arranged in the pixel array AA of the display panel 100 in the row direction X. The pixels arranged on one pixel row share the gate line 103. The subpixels disposed in the column direction Y along the data line direction share the same data line 102. One horizontal period 1H is a time obtained by dividing one frame period by the total number of pixel rows L1 to Ln.

The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and an actual background can be seen.

The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be made of a plastic OLED panel. An organic thin film may be disposed on the back plate of the plastic OLED panel, and the pixel array AA and the light emitting element may be formed on the organic thin film.

To realize colors, each of the pixels 101 may be divided into a red sub-pixel (hereinafter referred to as an "R sub-pixel"), a green sub-pixel (hereinafter referred to as a "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as a "B sub-pixel"). Each of the pixels may further include a white subpixel. Each of the sub-pixels includes a pixel circuit. The pixel circuit is connected to the data line, the gate line, and the power line.

The pixels may be set as true color pixels and PenTile pixels. The Pentile pixel can realize a higher resolution than a true color pixel by driving two sub-pixels having different colors as one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm may compensate for the lack of color representation in each pixel with the color of light emitted from adjacent pixels.

A touch sensor may be provided on the display panel 100. The touch input may be sensed using a separate touch sensor or may be sensed by a pixel. The touch sensor may be set as an on-cell type (on-cell type) or an add-on type (add-on type) on the screen of the display panel, or may be implemented as an in-cell type (in-cell type) touch sensor embedded in the pixel array AA.

As shown in fig. 2, the display panel 100 may include a circuit layer 12, a light emitting element layer 14, and an encapsulation layer 16 stacked on a substrate 10 when viewed from a cross-sectional structure.

The circuit layer 12 may include pixel circuits connected to wirings such as data lines, gate lines, and power lines, gate drivers (GIPs) connected to the gate lines, and the like. The wiring and circuit elements of the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated by insulating layers therebetween, and an active layer comprising a semiconductor material.

The light emitting element layer 14 may include light emitting elements EL driven by pixel circuits. The light emitting element EL may include a red (R) light emitting element, a green (G) light emitting element, and a blue (B) light emitting element. The light emitting element layer 14 may include a white light emitting element and a color filter. The light emitting element EL of the light emitting element layer 14 may be covered with a protective layer including an organic film and a passivation film.

The encapsulation layer 16 covers the light emitting element layer 14 to seal the circuit layer 12 and the light emitting element layer 14. The encapsulation layer 16 may have a multi-layered insulating structure in which organic films and inorganic films are alternately stacked. The inorganic film blocks permeation of moisture and oxygen. The organic film planarizes the surface of the inorganic film. When the organic film and the inorganic film are stacked in a plurality of layers, the moving path of moisture or oxygen becomes longer as compared with a single layer, so that permeation of moisture and oxygen affecting the light emitting element layer 14 can be effectively blocked.

A touch sensor layer may be disposed on the encapsulation layer 16. The touch sensor layer may include a capacitive type touch sensor that senses a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include a metal wiring pattern and an insulating layer forming a capacitance of the touch sensor. The capacitance of the touch sensor may be formed between the metal wiring patterns. A polarizing plate may be disposed on the touch sensor layer. The polarizing plate may improve visibility and contrast by converting polarization of external light reflected by the metals of the touch sensor layer and the circuit layer 12. The polarizing plate may be implemented as a polarizing plate in which a linear polarizing plate is combined with a phase retardation film, or as a circular polarizing plate. The cover glass may be adhered to the polarizing plate.

The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16. The color filter layer may include red, green, and blue color filters and a black matrix pattern. The color filter layer may replace the polarizing plate and improve color purity by absorbing a part of wavelengths of light reflected from the circuit layer and the touch sensor layer. In the present embodiment, by applying a color filter layer having higher light transmittance than a polarizing plate to a display panel, the light transmittance of the display panel PNL can be improved, and the thickness and flexibility of the display panel PNL can be improved. The cover glass may be adhered to the color filter layer.

The power supply device 140 generates DC power required to drive the pixel array AA of the display panel 100 and the display panel driver by using a DC-to-DC converter. The DC-to-DC converter may include a charge pump, a regulator, a buck converter (buck converter), a boost converter, and the like. The power supply device 140 may adjust a DC input voltage from a host system (not shown) and thereby generate DC voltages such as a gamma reference voltage VGMA, gate-on voltages VGH and VEH, gate-off voltages VGL and VEL, pixel driving voltage EVDD, pixel low-potential power supply voltage EVSS, reference voltage Vref, initial voltage Vinit, anode voltage Vano, and the like. The gamma reference voltage VGMA is supplied to the data driver 110. The gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL are supplied to the gate driver 120. The pixel driving voltage EVDD and the pixel low potential power supply voltage EVSS, the reference voltage Vref, the initial voltage Vinit, the anode voltage Vano, and the like are commonly supplied to the pixels.

The display panel driver writes pixel data (digital data) of an input image to the pixels of the display panel 100 under the control of a Timing Controller (TCON) 130.

The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a data driver 110 and a demultiplexer array 112 disposed between the data lines 102.

The demultiplexer array 112 sequentially supplies the data voltages output from the channels of the data driver 110 to the data lines 102 using a plurality of Demultiplexers (DEMUX). The demultiplexer may include a plurality of switching elements disposed on the display panel 100. When the demultiplexer is disposed between the output terminal of the data driver 110 and the output terminal of the data line 102, the number of channels of the data driver 110 can be reduced. The demultiplexer array 112 may be omitted.

The display panel driver may further include a touch sensor driver for driving the touch sensor. The touch sensor driver is omitted from fig. 1. The touch sensor driver may be integrated into one drive Integrated Circuit (IC). In the mobile device or the wearable device, the timing controller 130, the power supply 140, the data driver 110, the touch sensor driver, and the like may be integrated into one driving Integrated Circuit (IC).

The display panel driver may operate in a low-speed driving mode under the control of a Timing Controller (TCON) 130. The low-speed driving mode may be set to reduce power consumption of the display device in a case where the input image is not changed within a preset number of frames when the input image is analyzed. In the low-speed driving mode, when a still image is input for a predetermined time or more, power consumption of the display panel driver and the display panel 100 can be reduced by reducing a refresh rate of pixels. The low-speed driving mode is not limited to the case of inputting a still image. For example, when the display device is operated in the standby mode or when a user command or an input image is not input to the display panel driver for a predetermined time or more, the display panel driver may be operated in the low-speed driving mode.

The data driver 110 generates a data voltage Vdata by converting pixel data of an input image received from the timing controller 130 with a gamma compensation voltage at each frame period using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided for each gray level by a voltage divider circuit. The gamma compensation voltage divided from the gamma reference voltage VGMA is supplied to the DAC of the data driver 110. The data voltage Vdata is output through an output buffer AMP in each of the channels of the data driver 110.

The gate driver 120 may be implemented as an in-panel Gate (GIP) circuit formed directly on the circuit layer 12 of the display panel 100 together with the TFT array of the pixel array AA. The in-panel Gate (GIP) circuit may be disposed on a bezel area BZ, which is a non-display area of the display panel 100, or dispersed in a pixel array on which an input image is reproduced. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signal may include a scan pulse, an emission control pulse (hereinafter referred to as an "EM pulse"), an initial pulse, and a sensing pulse.

The shift register of the gate driver 120 outputs a pulse of the gate signal in response to the start pulse and the shift clock from the timing controller 130, and shifts the pulse according to the shift clock timing.

The timing controller 130 receives digital video DATA of an input image and a timing signal synchronized with the digital video DATA from a host system (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, a data enable signal DE, and the like. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE has a period of one horizontal period (1H).

The host system may be any one of a Television (TV) system, a tablet computer, a notebook computer, a navigation system, a Personal Computer (PC), a home theater system, a mobile device, and a vehicle system. The host system may scale an image signal from the video source according to the resolution of the display panel 100 and transmit the image signal to the timing controller 130 together with the timing signal.

The timing controller 130 multiplies the input frame frequency by i, and controls the operation timing of the display panel driver at a frame frequency of the input frame frequency x i (i is a positive integer greater than 0) Hz. The input frame frequency is 60Hz in the NTSC (national television standards committee) scheme and 50Hz in the PAL (phase alternating line) scheme. The timing controller 130 may reduce the driving frequency of the display panel driver by reducing the frame frequency to a frequency between 1Hz and 30Hz to reduce the refresh rate of the pixels in the low-speed driving mode.

Based on the timing signals Vsync, hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a control signal for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120. The timing controller 130 controls the operation timing of the display panel driver to synchronize the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

The voltage level of the gate timing control signal output from the timing controller 130 may be converted into gate-on voltages VGH and VEH and gate-off voltages VGL and VEL by a level shifter (not shown), and then supplied to the gate driver 120. That is, the level shifter converts low-level voltages of the gate timing control signal into gate-off voltages VGL and VEL, and converts high-level voltages of the gate timing control signal into gate-on voltages VGH and VEH. The gate timing signal includes a start pulse and a shift clock.

Fig. 3 is a circuit diagram showing a pixel circuit according to the first embodiment of the present disclosure.

Referring to fig. 3, a pixel circuit according to a first embodiment of the present disclosure may include a light emitting element EL, a driving element DT for driving the light emitting element EL, a plurality of switching elements M01 and M02, and a capacitor Cst.

The light emitting element EL may be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an emission layer (EML), an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), etc., but is not limited thereto. An anode electrode of the light emitting element EL is connected to the second node n2, and a cathode electrode is connected to the third power line PL3 to which the low-potential power voltage EVSS is applied. When voltages are applied to the anode electrode and the cathode electrode of the light emitting element EL, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL are moved to the emission layer EML and form excitons, thereby emitting visible light in the emission layer EML.

An organic light emitting diode used as a light emitting element may have a tandem structure in which a plurality of light emitting layers are stacked. The organic light emitting diode having a serial structure may improve brightness and lifetime of the pixel.

The driving element DT generates a current according to the gate-source voltage Vgs, and thereby drives the light emitting element EL. The driving element DT includes a gate electrode connected to the first node n1, a first electrode connected to a first power line PL1 to which a pixel driving voltage EVDD is applied, and a second electrode connected to the second node n 2.

The first switching element M01 is turned on according to the gate-on voltage VEH of the first SCAN pulse SCAN1, and applies the data voltage to the first node n1. The first switching element M01 includes a gate electrode to which the first SCAN pulse SCAN1 is applied, a first electrode connected to the second power line DL to which the data voltage Vdata is applied, and a second electrode connected to the first node n1.

The second switching element M02 is turned on according to the gate-on voltage VEH of the second SCAN pulse SCAN2, and applies the data voltage to the first node n1. The second switching element M02 includes a gate electrode to which the second SCAN pulse SCAN2 is applied, a first electrode connected to the second power line DL to which the data voltage is applied, and a second electrode connected to the first node n1.

In the case where both the first switching element M01 and the second switching element M02 are turned on during a period in which the data voltage is applied, the first switching element M01 and the second switching element M02 are connected in parallel with the second power line. This reduces the total resistance on the equivalent circuit, thereby improving the data charge capability.

The first capacitor Cst is connected between the first node n1 and the second node n2 and stores a threshold voltage. One end of the first capacitor Cst is connected to the first node n1, and the other end is connected to the second node n2.

Fig. 4 is a circuit diagram illustrating a pixel circuit according to a second embodiment of the present disclosure, and fig. 5A and 5B are waveform diagrams illustrating a gate signal applied to the pixel circuit illustrated in fig. 4.

Referring to fig. 4, a pixel circuit according to a second embodiment of the present disclosure may include a light emitting element EL, a driving element DT for driving the light emitting element EL, a plurality of switching elements M01, M02, M03, and M04, and a capacitor Cst. The driving element DT and the switching elements M01, M02, M03, and M04 may be implemented as n-channel oxide TFTs.

The pixel circuit is connected to a first power line PLl to which a pixel driving voltage EVDD is applied, a second power line DL to which a data voltage Vdata is applied, a third power line PL3 to which a low-potential power voltage EVSS is applied, a fourth power line PL4 to which an initialization voltage Vinit is applied, a fifth power line RL to which a reference voltage Vref is applied, and gate lines to which gate signals INIT, SENSE, SCAN1 and SCAN2 are applied.

The first switching element M01 is turned on according to the gate-on voltage VEH of the first SCAN pulse SCAN1, and applies the data voltage to the first node n1. The first switching element M01 includes a gate electrode to which the first SCAN pulse SCAN1 is applied, a first electrode connected to the second power line DL to which the data voltage is applied, and a second electrode connected to the first node n1.

The third switching element M03 is turned on according to the gate-on voltage VGH of the initialization pulse INIT, and applies the initialization voltage Vinit to the first node n1. The third switching element M03 includes a first electrode connected to the fourth power line PL4 to which the initialization voltage Vinit is applied, a gate electrode to which the initialization pulse INIT is applied, and a second electrode connected to the first node n1.

The fourth switching element M04 is turned on according to the gate-on voltage VGH of the sensing pulse SENSE, and supplies the reference voltage Vref to the second node n2. The fourth switching element M04 includes a first electrode connected to the second node n2, a gate electrode to which the sensing pulse SENSE is applied, and a second electrode connected to the fifth power line RL to which the reference voltage is applied.

As shown in fig. 5A and 5B, the pixel circuit may be driven in the order of the initialization step Ti, the sensing step Ts, the data writing step Tw, and the light emission step Tem. In the initializing step Ti, the pixel circuit is initialized. In the sensing step Ts, the threshold voltage Vth of the driving element DT is sensed and stored in the first capacitor Cst. In the data writing step Tw, the data voltage Vdata of the pixel data is applied to the first node n1. After the voltage at the first node n1 and the voltage at the second node n2 are increased in the step-up step Tboost, the light-emitting element EL may emit light at a luminance corresponding to the gray-scale value of the pixel data in the light-emitting step Tem.

The pixel circuit may apply the first scan pulse and the second scan pulse equally as shown in fig. 5A, but may also apply the first scan pulse and the second scan pulse differently and separately as shown in fig. 5B.

Fig. 6A to 6D are circuit diagrams showing the operation of the pixel circuit shown in fig. 4 in stages. Here, an operation according to the driving timing shown in fig. 5B will be described.

As shown in fig. 6A, in the initialization step Ti, the third switching element M03 and the fourth switching element M04 are turned on, and the first switching element M01 and the second switching element M02 are turned off. The initialization voltage Vinit is applied to the first node n1, and the reference voltage Vref is applied to the second node n2. At this time, the driving element DT is turned on, and the light emitting element EL is not turned on.

As shown in fig. 6B, in the sensing step Ts, the fourth switching element M04 maintains the on state, and thus the voltage of the second node n2 increases. When the gate-source voltage Vgs of the driving element DT reaches the threshold voltage Vth, the driving element DT is turned off, and the threshold voltage Vth is stored in the first capacitor Cst. During the sensing step Ts, the sensing pulse SENSE applied to the fourth switching element M04 may be generated within about 1.5 horizontal periods (1.5H).

In the holding period Th, the third switching element M03 is turned off, and the second node n2 and the first node n1 float to maintain the previous voltage. The holding period Th may be generated within about one horizontal period (1H).

As shown in fig. 6C, in the data writing step Tw, the first switching element M01 and the second switching element M02 are turned on. The data voltage Vdata of the pixel data is applied to the first node n1, and thus the voltage at the first node n1 is changed by the data voltage Vdata. At this time, the data voltage Vdata of the pixel data is not applied through one switching element but is applied through the first switching element M01 and the second switching element M02 connected in parallel, thereby improving the charging characteristics. During the data writing step Tw, both the first switching element M01 and the second switching element M02 maintain the on state. The SCAN pulse SCAN applied to the first and second switching elements M01 and M02 during the data writing step Tw may be generated within about 0.7 horizontal periods (0.7H). The first switching element M01 and the second switching element M02 are both turned on at the start of the data writing step Tw, and the first switching element M01 and the second switching element M02 are turned off at different points in time. That is, the first switching element M01 is turned off before the termination of the data writing step Tw, and the second switching element M02 is turned off when the data writing step Tw is terminated. The reason for the off-time point being different as above is to prevent data shuffling (shuffling). In this case, the point in time when the first switching element M01 is turned off may be fixed, and the point in time when the second switching element M02 is turned off may be variable.

In addition, the second scan pulse can reduce not only the falling time point but also the falling time by applying underdrive downward.

Fig. 7A to 7G are diagrams showing the fall time of the second scan pulse.

Referring to fig. 7A and 7B, it can be seen that when the falling time of the second scan pulse is changed, the off time of the second switching element is also changed. As the falling time of the second scan pulse decreases, the off time of the second switching element also decreases.

Due to the reduction of the off time of the second switching element, the second switching element can be turned off before the next row is turned off. This makes it possible to prevent occurrence of data shuffling, thereby ensuring more effective charging time.

The second switching element is an auxiliary TFT for improving the charging rate, and can minimize the falling time by reducing the size and load and applying underactuation downward as compared with the first switching element.

Referring to fig. 7C, the voltage level of the first scan pulse SACN and the voltage level of the second scan pulse SACN may be separated, and the gate low voltage of the second scan pulse SACN may be lower than the gate low voltage of the first scan pulse SACN. That is, the voltage swing of the first scan pulse SACN1 is between the first gate-on voltage VGH1 and the first gate-off voltage VGL1, and the voltage swing of the second scan pulse SACN2 is between the first gate-on voltage VGH1 and the second gate-off voltage VGL2 lower than the first gate-off voltage VGL 1.

When the difference between the gate high voltage VGHl and the gate low voltage VGL2 of the second scan pulse SACN2 increases, the falling period of the second scan pulse SACN2 is shortened, and thus the falling time can be reduced.

Referring to fig. 7D, the voltage level of the first scan pulse SACN and the voltage level of the second scan pulse SACN may be separated, and the gate high voltage of the second scan pulse SACN may be higher than the gate high voltage of the first scan pulse SACN. That is, the voltage swing of the first scan pulse SACN1 is between the first gate-on voltage VGH1 and the first gate-off voltage VGL1, and the voltage swing of the second scan pulse SACN2 is between the second gate-on voltage VGH2 higher than the first gate-on voltage VGH1 and the first gate-off voltage VGL 1.

When the difference between the gate-on voltage VGH2 and the gate-off voltage VGL1 of the second scan pulse SACN2 increases, the falling period of the second scan pulse SACN2 is shortened, and thus the falling time can be reduced.

Referring to fig. 7E, the voltage level of the first scan pulse SACN and the voltage level of the second scan pulse SACN2 may be separated, the gate low voltage of the second scan pulse SACN2 may be lower than the gate low voltage of the first scan pulse SACN1, and the gate high voltage of the second scan pulse SACN2 may be higher than the gate high voltage of the first scan pulse SACN 1. That is, the voltage swing of the first scan pulse SACN1 is between the first gate-on voltage VGH1 and the first gate-off voltage VGL1, and the voltage swing of the second scan pulse SACN2 is between the second gate-on voltage VGH2 higher than the first gate-on voltage VGH1 and the first gate-off voltage VGL 1.

When the difference between the gate high voltage VGH2 and the gate low voltage VGL2 of the second scan pulse SACN2 increases, the falling period of the second scan pulse SACN2 is shortened, and thus the falling time can be reduced.

Referring to fig. 7F, since the falling time of the scan pulse of the (n-1) -th row is shortened and thus the off time point of the switching element is advanced, the effective charging time of the n-th row is increased and thus the data charging rate can be improved.

Referring to fig. 7G, as the gate low voltage VGL of the second scan pulse decreases, a difference from the gate high voltage VGH of the second scan pulse increases. Accordingly, the falling period of the second scan pulse is reduced, and thus the data charge rate can be improved.

For example, as shown, the data charge rate is 12.7% when the gate low voltage VGL of the second scan pulse is-6V, and 53.7% when the gate low voltage VGL is-12V. In addition, the data charge rate is 66.1% when the gate low voltage VGL is-15V, and 74.3% when the gate low voltage VGL is-18V. This example shows that the charging rate is improved.

During the step-up Tboost, the first switching element M01, the second switching element M02, the third switching element M03, and the fourth switching element M04 are turned off. At this time, the voltage at the first node n1 and the voltage at the second node n2 increase.

In the light emission step Tem, as shown in fig. 6D, the first switching element M01, the second switching element M02, the third switching element M03, and the fourth switching element M04 maintain an off state. At this time, a current generated according to the gate-source voltage Vgs of the driving element DT, that is, the voltage between the first node n1 and the second node n2 is supplied to the light emitting element EL, thereby causing the light emitting element EL to emit light.

In the embodiment, the case where the falling time of the scan pulse is equally applied to all pixels is exemplarily described, but the present disclosure is not limited thereto. That is, in the embodiment, the falling time of the scan pulse is differently applied for each gate line or each group of gate lines in consideration of the RC delay in the data lines or the IR drop in the power lines EVDD and EVSS.

Fig. 8A to 8C are waveform diagrams showing gate signals applied to the pixel circuit shown in fig. 4.

Referring to fig. 8A, the falling time of the second scan pulse may be differently applied for each gate line in consideration of the RC delay in the data line or the IR drop in the power lines EVDD and EVSS.

Referring to fig. 8B, the falling time of the second scan pulse may be differently applied for each group of gate lines in consideration of the RC delay in the data lines or the IR drop in the power lines EVDD and EVSS.

Referring to fig. 8C, the rising time of the second scan pulse may be differently applied for each group of gate lines in consideration of the RC delay in the data lines or the IR drop in the power lines EVDD and EVSS, thereby adjusting the overlapping period of the first and second scan pulses.

As shown in fig. 8A to 8C, the falling time of the second scan pulse or the gate low voltage according to the embodiment may vary in proportion to the RC delay or the IR drop.

Although the case of differently applying the gate low voltage of the second scan pulse is described, the present disclosure is not limited thereto. That is, in an embodiment, at least one of the gate high voltage and the gate low voltage of the second scan pulse may be differently applied.

Fig. 9 is a circuit diagram showing a pixel circuit according to a third embodiment of the present disclosure.

Referring to fig. 9, a pixel circuit according to a third embodiment of the present disclosure includes a light emitting element EL, a driving element DT for driving the light emitting element EL, a switching element M01, and a capacitor Cst.

The light emitting element EL may be implemented as an OLED. The OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer may include, but is not limited to, a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an emission layer (EML), an Electron Transport Layer (ETL), an Electron Injection Layer (EIL). An anode electrode of the light emitting element EL is connected to the second node n2, and a cathode electrode is connected to the third power line PL3 to which the low-potential power voltage EVSS is applied. When voltages are applied to the anode electrode and the cathode electrode of the light emitting element EL, holes passing through the Hole Transport Layer (HTL) and electrons passing through the Electron Transport Layer (ETL) are moved to the emission layer EML and form excitons, thereby emitting visible light in the emission layer EML.

The driving element DT generates a current according to the gate-source voltage Vgs, and thereby drives the light emitting element EL. The driving element DT includes a gate electrode connected to the first node n1, a first electrode connected to a first power line to which a pixel driving voltage is applied, and a second electrode connected to the second node n 2.

The first switching element M01 may be formed as a double gate and driven separately by the first SCAN pulse SCAN1 and the second SCAN pulse SCAN 2. In the case of forming as a double gate, applying a gate voltage to the upper and lower surfaces of the active layer may cause an increase in carriers and an increase in mobility, thereby improving current capability. Accordingly, in the case where the first switching element M01 is turned on during the period in which the data voltage is applied, the data charge capacity can be improved due to the current capacity characteristic of the first switching element M01 having the double gate structure.

Fig. 10 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present disclosure, and fig. 11A and 11B are waveform diagrams showing a gate signal applied to the pixel circuit shown in fig. 10.

Referring to fig. 10, a pixel circuit according to a fourth embodiment of the present disclosure includes a light emitting element EL, a driving element DT for driving the light emitting element EL, a plurality of switching elements M01, M02, and M03, and a capacitor Cst. The driving element DT and the switching elements M01, M02, and M03 may be implemented as n-channel oxide TFTs.

The first switching element M01 is turned on according to the gate-on voltage VEH of the first and second SCAN pulses SCAN1 and SCAN2, and applies the data voltage to the first node n1. The first switching element M01 includes a first gate electrode to which the first SCAN pulse SCAN1 is applied, a second gate electrode to which the second SCAN pulse SCAN2 is applied, a first electrode connected to the second power line DL to which the data voltage is applied, and a second electrode connected to the first node n1.

The second switching element M02 is turned on according to the gate-on voltage VGH of the initialization pulse INIT, and applies the initialization voltage Vinit to the first node n1. The second switching element M02 includes a first electrode connected to the fourth power line PL4 to which the initialization voltage Vinit is applied, a gate electrode to which the initialization pulse INIT is applied, and a second electrode connected to the first node n1.

The third switching element M03 is turned on according to the gate-on voltage VGH of the sensing pulse SENSE, and supplies the reference voltage Vref to the second node n2. The third switching element M03 includes a first electrode connected to the second node n2, a gate electrode to which the sensing pulse SENSE is applied, and a second electrode connected to the fifth power line RL to which the reference voltage is applied.

As shown in fig. 11A and 11B, the pixel circuit may be driven in the order of the initialization step Ti, the sensing step Ts, the data writing step Tw, and the light emission step Tem. In the initializing step Ti, the pixel circuit is initialized. In the sensing step Ts, the threshold voltage Vth of the driving element DT is sensed and stored in the first capacitor Cst. In the data writing step Tw, the data voltage Vdata of the pixel data is applied to the first node n1. After the voltage of the first node n1 and the voltage of the second node n2 are increased in the step-up step Tboost, the light emitting element EL may emit light at a luminance corresponding to the gray value of the pixel data in the light emitting step Tem.

The pixel circuit may apply the first scan pulse and the second scan pulse equally as shown in fig. 11A, but may also apply the first scan pulse and the second scan pulse differently and separately as shown in fig. 11B.

As shown in fig. 11A, in the initialization step Ti, the second switching element M02 and the third switching element M03 are turned on, and the first switching element M01 is turned off. The initialization voltage Vinit is applied to the first node n1, and the reference voltage Vref is applied to the second node n2. At this time, the driving element DT is turned on, and the light emitting element EL is not turned on.

In the sensing step Ts, the second switching element M02 maintains the on state, and thus the voltage of the first node n1 increases. When the gate-source voltage Vgs of the driving element DT reaches the threshold voltage Vth, the driving element DT is turned off, and the threshold voltage Vth is stored in the first capacitor Cst.

In the holding period Th, the second switching element M02 is turned off, and the second node n2 and the first node n1 float to maintain the previous voltage.

In the data writing step Tw, the first switching element M01 is turned on. The data voltage Vdata of the pixel data is applied to the first node n1, and thus the voltage at the first node n1 is changed by the data voltage Vdata. The SCAN pulse SCAN applied to the first switching element M01 during the data writing step Tw may be generated within about 0.7 horizontal periods (0.7H). In this case, the data voltage Vdata of the pixel data is not applied through one switching element but is applied through the first switching element M01 having the dual gate structure, so that the charging characteristics can be improved.

During the step-up Tboost, the first, second, and third switching elements M01, M02, M03 are turned off. At this time, the voltage of the first node n1 and the voltage of the second node n2 increase.

In the light emission step Tem, the first, second and third switching elements M01, M02 and M03 maintain an off state. At this time, a current generated according to the gate-source voltage Vgs of the driving element DT, that is, the voltage between the first node n1 and the second node n2 is supplied to the light emitting element EL, thereby causing the light emitting element EL to emit light.

Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure may be implemented in many different forms without departing from the technical concept of the present disclosure. Accordingly, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concepts of the present disclosure. The scope of the technical idea of the present disclosure is not limited thereto. Accordingly, it should be understood that the above-described embodiments are illustrative in all respects, and not limiting upon the present disclosure. The scope of the present disclosure should be construed based on the appended claims, and all technical ideas within the equivalent scope thereof should be construed to fall within the scope of the present disclosure.

Claims

1. A pixel circuit comprising:

a driving element including a first electrode connected to a first power line to which a pixel driving voltage is applied, a gate electrode connected to a first node, and a second electrode connected to a second node;

a first switching element including a first electrode connected to the second power line to which the data voltage is applied, a gate electrode to which the first scan pulse is applied, and a second electrode connected to the first node;

a second switching element including a first electrode connected to the second power line, a gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node;

a light emitting element including an anode electrode connected to the second node and a cathode electrode connected to a third power line to which a low-potential power voltage is applied; and

a capacitor connected between the first node and the second node,

The turn-off time point of the second switch element varies with the RC delay or IR drop of the first power line, the second power line, and the third power line.

2. The pixel circuit according to claim 1, further comprising:

a third switching element including a first electrode connected to a fourth power line to which an initialization voltage is applied, a gate electrode to which an initialization pulse is applied, and a second electrode connected to the first node; and

A fourth switching element includes a first electrode connected to the second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a fifth power line to which a reference voltage is applied.

3 . The pixel circuit according to claim 1 , wherein turn-on time points of the first switching element and the second switching element are the same, and turn-off time points of the first switching element and the second switching element are different from each other.

4. The pixel circuit according to claim 1 , wherein the voltage swing of the first scanning pulse is between a first gate-on voltage and a first gate-off voltage, and

The voltage of the second scan pulse has a swing amplitude between the first gate-on voltage and a second gate-off voltage lower than the first gate-off voltage.

5. The pixel circuit according to claim 1 , wherein the voltage swing of the first scanning pulse is between a first gate-on voltage and a first gate-off voltage, and

The voltage swing of the second scan pulse is between a second gate-on voltage higher than the first gate-on voltage and the first gate-off voltage.

6. The pixel circuit according to claim 1 , wherein the voltage swing of the first scanning pulse is between a first gate-on voltage and a first gate-off voltage, and

The voltage of the second scan pulse has a swing amplitude between a second gate-on voltage higher than the first gate-on voltage and a second gate-off voltage lower than the first gate-off voltage.

7 . The pixel circuit according to claim 1 , wherein during a period in which the data voltage is applied, a turn-on time point of the first switching element and a turn-on time point of the second switching element are different from each other.

8. A pixel circuit comprising:

a first switching element including a first electrode connected to the second power line to which a data voltage is applied, a first gate electrode to which a first scan pulse is applied, a second gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node;

a second switching element including a first electrode connected to a fourth power line to which an initialization voltage is applied, a gate electrode to which an initialization pulse is applied, and a second electrode connected to the first node;

a capacitor connected between the first node and the second node,

9. The pixel circuit according to claim 8, further comprising:

A third switching element includes a first electrode connected to the second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a fifth power line to which a reference voltage is applied.

10 . The pixel circuit according to claim 8 , wherein turn-on time points of the first switching element and the second switching element are the same, and turn-off time points of the first switching element and the second switching element are different from each other.

11. A method for driving the pixel circuit according to any one of claims 1 to 10, comprising:

Initializing the pixel circuit;

sensing a threshold voltage of the driving element and storing the sensed threshold voltage in the capacitor;

applying a data voltage of pixel data to the first node so that a voltage of the first node and a voltage at the second node increase; and

Light is emitted through the light emitting element at a brightness corresponding to the grayscale value of the pixel data.

12. A display device comprising:

a display panel in which a plurality of data lines, a plurality of gate lines intersecting the plurality of data lines, a plurality of power lines to which different constant voltages are applied, and a plurality of sub-pixels are provided;

a data driver that provides data voltages of pixel data to the plurality of data lines; and

a gate driver providing gate signals to the plurality of gate lines;

Each sub-pixel of the plurality of sub-pixels comprises:

a driving element including a first electrode connected to a first power line to which a pixel driving voltage is applied among the plurality of power lines, a gate electrode connected to a first node, and a second electrode connected to a second node;

a first switching element including a first electrode connected to a second power line to which a data voltage is applied among the plurality of power lines, a gate electrode to which a first scan pulse is applied, and a second electrode connected to the first node;

a light emitting element including an anode electrode connected to the second node and a cathode electrode connected to a third power line to which a low-potential power voltage is applied among the plurality of power lines; and

a capacitor connected between the first node and the second node,

13. The display device according to claim 12, wherein each of the plurality of sub-pixels further comprises:

a fourth switching element including a first electrode connected to the second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a fifth power line to which a reference voltage is applied among the plurality of power lines.

14 . The display device according to claim 12 , wherein turn-on time points of the first switching element and the second switching element are the same, and turn-off time points of the first switching element and the second switching element are different from each other.

15. The display device according to claim 12, wherein the swing amplitude of the voltage of the first scan pulse is between a first gate-on voltage and a first gate-off voltage, and

16. The display device according to claim 12, wherein the voltage swing of the first scan pulse is between a first gate-on voltage and a first gate-off voltage, and

A voltage of the second scan pulse is between a second gate-on voltage higher than the first gate-on voltage and the first gate-off voltage.

17. The display device according to claim 12, wherein the swing amplitude of the voltage of the first scan pulse is between a first gate-on voltage and a first gate-off voltage, and

18 . The display device of claim 12 , wherein during a period in which the data voltage is applied, a turn-on time point of the first switching element and a turn-on time point of the second switching element are different from each other.

19 . The display device according to claim 12 , wherein the data driver, the gate driver, and all transistors in the sub-pixels are implemented using oxide thin film transistors including an n-channel oxide semiconductor.

20. A display device comprising:

a gate driver providing gate signals to the plurality of gate lines;

Each sub-pixel of the plurality of sub-pixels comprises:

a first switching element including a first electrode connected to a second power line to which a data voltage is applied, a first gate electrode to which a first scan pulse is applied, a second gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node;

a capacitor connected between the first node and the second node,

21. The display device according to claim 20, wherein each of the plurality of sub-pixels further comprises:

a third switching element including a first electrode connected to the second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a fifth power line to which a reference voltage is applied among the plurality of power lines.

22 . The display device according to claim 20 , wherein the data driver, the gate driver, and all transistors in the sub-pixels are implemented using oxide thin film transistors including an n-channel oxide semiconductor.

23 . The display device according to claim 20 , wherein turn-on time points of the first switching element and the second switching element are the same, and turn-off time points of the first switching element and the second switching element are different from each other.