CN115357525A - Snooping filter, processing unit, computing device and related methods - Google Patents

Abstract

The embodiment of the present application provides a snooping filter, a processing unit, a computing device, and a related method. A variety of chips, such as IoT chips, audio/video chips, etc. The snooping filter includes: a receiving unit, configured to receive the coordinate information sent by the private cache after the first cache line is filled into the private cache; a snooping unit, configured to store in the mapping entry corresponding to the target filling position determined according to the coordinate information When the identification information of the second cache line is available, the identification information of the second cache line is transferred from the mapping entry corresponding to the target filling position to the victim entry, and the first cache line is stored in the mapping entry corresponding to the target filling position. Identification information. This solution can reduce the occupancy of snooping and filtering on the communication bandwidth inside and outside the processor core.

Description

Snooping filter, processing unit, computing device and related methods

technical field

The embodiments of the present application relate to the field of chip technology, and in particular, to a snoop filter, a processing unit, a computing device, and a related method.

Background technique

In a processing unit including multiple processor cores, the cache includes a private cache and a shared cache, the private cache belongs to a specific processor core, and the shared cache belongs to multiple processor cores. When the processor core queries data from the cache, it first queries the required data from its private cache, and if it cannot find it, it then queries the lower-level cache in turn. If the required data is stored in the private caches of other processor cores, the required data needs to be queried in the private caches of other processor cores. This processing method is called snooping. Snooping on the private caches of other processor cores will reduce the operating efficiency of other processor cores.

At present, a snoop filter for storing relevant information of data stored in the private cache is set. By querying the snoop filter, the private cache that does not store the required data can be determined, so as to avoid snooping the private cache that does not store the required data.

However, in order to ensure that the snooping filter can accurately reflect the data stored in the private cache, whenever the private cache actively deletes a cache line, it needs to send a deletion request to the snooping filter, and the relevant information of the deleted cache line in the snooping filter For deletion, even if the deleted cache line is the same as the data in the memory, a deletion request needs to be sent to the snoop filter, which will occupy the communication bandwidth between the processor core and the processor core, and affect the performance of the processing unit.

Contents of the invention

In view of this, embodiments of the present application provide a snoop filter, a processing unit, a computing device, and a related method, so as to at least solve or alleviate the above-mentioned problems.

According to the first aspect of the embodiments of the present application, there is provided a snooping filter, including: a receiving unit, configured to receive coordinate information sent by the private cache after the first cache line is filled in the private cache, wherein the The coordinate information is used to indicate the target filling position of the first cache line in the private cache; the snooping unit is configured to store the second cache in the mapping entry corresponding to the target filling position determined according to the coordinate information When the identification information of the line is selected, the identification information of the second cache line is transferred from the mapping entry corresponding to the target filling position to the victim entry, and the second cache line is stored in the mapping entry corresponding to the target filling position. Identification information of a cache line, where different cache lines correspond to different identification information.

According to the second aspect of the embodiment of the present application, there is provided a processing unit, including: the snooping filter according to the first aspect above; at least two processor cores, used to query the snooping filter and determine the required The private cache where the data resides.

According to a third aspect of the embodiments of the present application, there is provided a computing device, including: the processing unit described in the second aspect above; and a memory, coupled to the processing unit, and storing data required by the processing unit.

According to a fourth aspect of the embodiments of the present application, there is provided a method for snooping and filtering, including: receiving coordinate information sent by the private cache after the first cache line is filled in the private cache, wherein the coordinate information is used to indicate The target filling position of the first cache line in the private cache; when it is determined according to the coordinate information that the mapping entry corresponding to the target filling position stores the identification information of the second cache line, the first The identification information of the second cache line is transferred from the mapping entry corresponding to the target filling position to the victim entry, and the identification information of the first cache line is stored in the mapping entry corresponding to the target filling position, where different The cache lines correspond to different identification information.

According to the snooping and filtering scheme provided by the embodiment of the present application, the filling position in the private cache corresponds to the mapping entry in the snooping filter. After the first cache line is filled to the target filling position, if the mapping corresponding to the target filling position The entry stores the identification information of the second cache line, and the snooping unit transfers the identification information of the second cache line to the victim entry, and stores the identification information of the first cache line in the mapping entry corresponding to the target filling position. Since the filling position corresponds to the mapping table item one by one, when the second cache line does not need to write back data, the private cache only needs to send the coordinate information of the target filling position to the snoop filter, and the snoop filter will send the coordinate information of the first cache line The identification information is stored in the mapping entry corresponding to the target filling position, and the identification information of the second cache line is transferred to the victim entry. Therefore, for the cache line that does not need data write-back, the private cache does not need to send a delete request to the snoop filter. It can be guaranteed to determine which private caches cannot store the required data according to the snooping filter, thereby reducing the number of snoops on the private caches of other processor cores, thereby reducing the impact of sending delete requests on the processor core and the processor core. Occupation of external communication bandwidth, thereby ensuring the performance of the processing unit.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments described in the embodiments of the present application, and those skilled in the art can also obtain other drawings based on these drawings.

FIG. 1 is a schematic diagram of a computing device used in an embodiment of the present application;

Fig. 2 is a schematic diagram of a processing unit of an embodiment of the present application;

FIG. 3 is a schematic diagram of a snoop filter according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a private cache and a snooping filter according to an embodiment of the present application;

Fig. 5 is a flowchart of a snooping filtering method according to an embodiment of the present application.

Detailed ways

The present application is described below based on examples, but the present application is not limited only to these examples. In the following detailed description of the application, some specific details are set forth in detail. The present application can be fully understood by those skilled in the art without the description of these detailed parts. In order to avoid obscuring the essence of the present application, well-known methods, procedures, and procedures are not described in detail. Additionally, the drawings are not necessarily drawn to scale.

First of all, some nouns or terms appearing in the process of describing the embodiments of the present application are applicable to the following explanations.

Snooping: In a processing unit including multiple processor cores, if the data required by one processor core is stored in the private cache of other processor cores, the processor core needs to query in the private cache of other processor cores The required data, the process is called snooping (snoop).

Snooping filter: Since snooping on the private caches of other processor cores will reduce the operating efficiency of other processor cores, in order to reduce the number of snooping times, a lookup table of the upper-level cache is stored near the next-level cache, and the lookup table is stored. Regarding information about the data stored in the corresponding private cache, it can be determined whether the required data is stored in the corresponding private cache through a lookup table, and the lookup table is called a snoop filter.

Cache line: When the processor core reads data from the main memory into the buffer memory, it needs to read in the required data and a part of the nearby data. The set of data read each time is called a cache line (CacheLine). Many cache lines can be stored in the level cache, and each level cache stores data in units of cache lines.

computing device

FIG. 1 shows a schematic block diagram of a computing device 10 . The computing device 10 can be constructed based on various types of processing units and driven by any operating system such as WINDOWS operating system, UNIX operating system, and Linux operating system. In addition, computing device 10 may be implemented in hardware and/or software such as PCs, desktops, notebooks, servers, and mobile communication devices.

As shown in FIG. 1 , computing device 10 may include one or more processing units 12 , and memory 14 . The memory 14 in the computing device 10 can be used as a main memory (referred to as main memory or internal memory) for storing instruction information and/or data information represented by data signals, for example, the memory 14 can store data provided by the processing unit 12 (such as For budgetary results), it can also be used to implement data exchange between the processing unit 12 and the external storage device 16 (or become an auxiliary storage or an external storage).

In some cases, the processing unit 12 needs to access the memory 14 through the bus 11 to acquire data in the memory 14 or modify the data in the memory 14 . Since the access speed of the memory 14 is relatively slow, in order to alleviate the speed gap between the processing unit 12 and the memory 14, the computing device 10 further includes a cache memory 18 communicatively connected with the bus 11, and the cache memory 18 is used to store the data stored in the memory 14. Some program data or message data that may be called repeatedly are cached. The cache memory 18 may be implemented by a storage device such as a static random access memory (Static Random Access Memory, SRAM). The high-speed cache memory 18 can be a multi-level structure, such as a three-level cache structure with a first-level cache (L1Cache), a second-level cache (L2Cache) and a third-level cache (L3Cache), and the high-speed cache memory 18 can also be a cache with more than three levels structure or other type of cache structure. In some embodiments, a portion of cache memory 18 (eg, L1 cache, or both L1 and L2 cache) may be integrated within processing unit 12 or integrated with processing unit 12 in the same system-on-chip.

Based on this, the processing unit 12 may include an instruction execution unit 121 , a memory management unit 122 and other parts. The instruction execution unit 121 initiates a write access request when executing some instructions that need to modify the memory, and the write access request specifies the write data to be written into the memory and the corresponding physical address. The memory management unit 122 is configured to translate the virtual address specified by these instructions into the physical address mapped by the virtual address, and the physical address specified by the write access request may be consistent with the physical address specified by the corresponding instruction.

The exchange of information between memory 14 and cache memory 18 may be organized in blocks of data. In some embodiments, the cache memory 18 and the memory 14 can be divided into data blocks according to the same space size, and the data block can be used as the minimum unit of data exchange between the cache memory 18 and the memory 14 (including a preset length one or more data). For simplicity and clarity, each data block in the cache memory 18 is referred to as a cache block (or cacheline or cache line) for short below, and different cache blocks have different cache block addresses. Each data block in the memory 14 is referred to as a memory block for short, and different memory blocks have different memory block addresses. Cache block addresses and/or memory block addresses may include physical address tags for locating data blocks.

Due to the limitation of space and resources, the cache memory 18 cannot cache all the contents in the memory 14, that is, the storage capacity of the cache memory 18 is usually smaller than that of the memory 14, and the addresses of each cache block provided by the cache memory 18 cannot correspond to the memory 14. All memory block addresses provided. When the processing unit 12 needs to access the memory, it first accesses the cache memory 18 via the bus 11 to determine whether the content to be accessed has been stored in the cache memory 18 . If the content to be accessed has been stored in the cache memory 18 , the cache memory 18 hits, and the processing unit 12 directly recalls the content to be accessed from the cache memory 18 . If the content to be accessed is not stored in the cache memory 18 , the cache memory 18 and the processing unit 12 need to access the memory 14 via the bus 11 to find corresponding information in the memory 14 . Since the access rate of the cache memory 18 is very fast, when the cache memory 18 hits, the efficiency of the processing unit 12 can be significantly improved, thereby improving the performance and efficiency of the entire computing device 10 .

In addition, the computing device 10 may also include a storage device 16, a display device, an audio device, a mouse/keyboard, and other input/output devices. The storage device 16 may be a hard disk, an optical disk, and a flash memory, which are coupled to the bus 11 through a corresponding interface, and are used for information access. The display device can be coupled to the bus 11 via a corresponding graphics card for displaying according to the display signal provided by the bus 11 .

The computing device 10 may also include a communication device 17, so that the computing device 10 may communicate with a network or other devices in various ways. The communication device 17 may include one or more communication modules, and the communication device 17 may include a wireless communication module suitable for a specific wireless communication protocol. For example, the communication device 17 may include a WLAN module for implementing WiFi communication conforming to the 802.11 standard formulated by the Institute of Electrical and Electronics Engineers (IEEE). The communication device 17 may include a WWAN module for implementing wireless wide area communication conforming to cellular or other wireless wide area protocols. The communication device 17 may also include communication modules using other protocols, such as a Bluetooth module, or other self-defined communication modules. The communication device 17 may also be a port for serial transmission of data.

It should be noted that, different computing devices 10 may have different structures of computing devices 10 according to different motherboards, operating systems and instruction set architectures. For example, many current computing devices are provided with an I/O control center connected between the bus 11 and various I/O devices, and the I/O control center can be integrated in the processing unit 12 or independent of the processing unit 12 .

processing unit

FIG. 2 is a schematic block diagram of the processing unit 12 according to one embodiment of the present application. As shown in FIG. 2 , each processing unit 12 may include a plurality of processor cores 120 for processing instructions, and the processing and execution of instructions may be controlled by a user (for example, through an application program) and/or a system platform. Each processor core 120 can be used to process a specific instruction set, and the instruction set can support Complex Instruction Set Computing (Complex Instruction Set Computing, CISC), Reduced Instruction Set Computing (Reduced Instruction Set Computing, RISC) or based on very long instruction word (Very Long Instruction Word, VLIW) calculation, it should be noted that the processor core 120 is suitable for processing the RISC-V instruction set. Different processor cores 120 may each process different or the same instruction set. The processor core 120 may also include other processing modules, such as a digital signal processor (Digital Signal Processor, DSP) and the like. As an example, FIG. 2 shows processor core 1 to processor core m, where m is a positive integer.

The cache memory 18 shown in FIG. 1 may be fully or partially integrated in the processing unit 12 . Depending on the architecture, the cache memory 18 may be a single or multi-level internal cache memory located inside and/or outside each processor core 120 (such as three levels of cache memories L1 to L3 shown in FIG. 2 , In FIG. 2, it is collectively identified as 18), and may also include instruction-oriented and instruction caches and data-oriented data caches. The processor cores 120 in the processing unit 12 may share at least a part of the cache memory, for example, the processor cores 1 to m may share the third-level cache memory L3. Each processor core 120 in the processing unit 12 has its own private cache, for example, each processor core 120 has a first-level cache memory L1 and a second-level cache memory L2. The processing unit 12 may also include an external cache (not shown), and other cache structures may also serve as the external cache of the processing unit 12 .

As shown in FIG. 2, the processing unit 12 may include a register file (Register File) 126, and the register file 126 may include a plurality of registers for storing different types of data and/or instructions, and these registers may be of different types, such as a register file 126 may include integer registers, floating point registers, status registers, instruction registers and pointer registers, among others. The registers in the register file 126 can be implemented by selecting general-purpose registers, or can adopt a specific design according to the actual requirements of the processing unit 12 .

The processing unit 12 may include a memory management unit (Memory Management Unit, MMU) 122, configured to translate virtual addresses into physical addresses. Some entries in the page table are cached in the memory management unit 122 , and the memory management unit 122 may also acquire non-cached entries from the memory. One or more memory management units 122 can be set in each processor core 120, and the memory management units 122 in different processor cores 120 can be synchronized with the memory management units 122 in other processing units or processor cores, so that each Each processing unit or processor core can share a unified virtual storage system.

The processing unit 12 is used to execute instruction sequences (ie, programs). The process of the processing unit 12 executing each instruction includes: fetching the instruction from the memory storing the instruction, decoding the fetched instruction, executing the decoded instruction, and maintaining the execution result of the instruction, etc., and so on until the instruction is executed All commands in the sequence or a shutdown command is encountered.

In order to realize the above process, the processing unit 12 may include an instruction fetching unit 124, an instruction decoding unit 125, an instruction issuing unit (not shown), an instruction executing unit 121, a retirement unit 123, and the like.

The instruction fetching unit 124 is used as the startup engine of the processing unit 12, and is used to transfer instructions from the memory 14 to the instruction register (which may be a register for storing instructions in the register file 126 shown in FIG. 2 ), and receives the following An instruction fetch address or the next instruction fetch address can be calculated according to the instruction fetch algorithm. The instruction fetch algorithm can increase or decrease the address according to the instruction length.

After the instruction is fetched, the processing unit 12 enters the instruction decoding stage, and the instruction decoding unit 125 decodes the fetched instruction according to a predetermined instruction format, so as to obtain operand acquisition information required by the fetched instruction, so as to provide instructions for execution. Unit 121 is ready for operation. Operand fetch information can include pointers to immediates, registers, or other software/hardware that can provide source operands.

The instruction issuing unit usually exists in the high-performance processing unit 12, between the instruction decoding unit 125 and the instruction execution unit 121, and is used for instruction scheduling and control, so as to efficiently distribute each instruction to different instruction execution units 121 , making parallel operation of multiple instructions possible. After the instruction is fetched, decoded, and dispatched to the corresponding instruction execution unit 121, the corresponding instruction execution unit 121 starts to execute the instruction, that is, executes the operation indicated by the instruction and performs the corresponding function.

Retirement unit 123 (or called instruction retirement unit or instruction write-back unit) is mainly used to write back the execution result generated by the instruction execution unit 121 to the corresponding storage location (for example, a register inside the processing unit 12), so that subsequent instructions The corresponding execution result can be quickly obtained from the storage location.

For different types of instructions, different instruction execution units 121 may be set in the processing unit 12 accordingly. The instruction execution unit 121 may be an operation unit (for example, including an arithmetic logic unit, a shaping processing unit, a vector operation unit, etc., for performing operations according to operands and outputting operation results), a memory execution unit (for example, for accessing memory according to instructions to read fetch data in memory or write specified data to memory, etc.) and coprocessors, etc. In the processing unit 12, each instruction execution unit 121 may run in parallel and output a corresponding execution result.

When the instruction execution unit 121 executes a certain type of instruction (such as a memory access instruction), it needs to access the memory 14 to obtain information stored in the memory 14 or provide data that needs to be written into the memory 14 . It should be noted that the instruction execution unit 121 for executing memory access instructions may also be referred to as a memory execution unit for short, and the memory execution unit may be a load store unit (Load Store Unit, LSU) and/or other units for memory access .

After the memory access instruction is acquired by the instruction fetching unit 124, the instruction decoding unit 125 may decode the memory access instruction, so that the source operand of the memory access instruction can be acquired. The decoded memory access instruction is provided to the corresponding instruction execution unit 121, and the instruction execution unit 121 can perform corresponding operations on the source operand of the memory access instruction (for example, the source operand stored in the register is operated by the arithmetic logic unit number) to obtain the address information corresponding to the memory access instruction, and initiate corresponding requests based on the address information, such as address translation requests, write access requests, and the like.

The source operand of the memory access instruction generally includes an address operand, and the instruction execution unit 121 performs operations on the address operand to obtain a virtual address or a physical address corresponding to the memory access instruction. When the memory management unit 122 is disabled, the instruction execution unit 121 can directly obtain the physical address of the memory access instruction through logical operations. When the memory management unit 121 is enabled, the corresponding instruction execution unit 121 initiates an address translation request according to the virtual address corresponding to the memory access instruction, and the address translation request includes the virtual address corresponding to the address operand of the memory access instruction; the memory management unit 122 Respond to the address translation request, and convert the virtual address in the address translation request into a physical address according to the entry matching the virtual address, so that the instruction execution unit 121 can access the cache memory 18 and/or memory 14 according to the translated physical address .

Depending on the function, memory access instructions may include load instructions and store instructions. The execution process of the load instruction generally does not need to modify the information in the memory 14 or the cache memory 18, and the instruction execution unit 121 only needs to read the address operand stored in the memory 14, the cache memory 18 or the external memory according to the load instruction. data in the device. Different from the load instruction, the source operand of the store instruction includes not only the address operand, but also data information. The execution of the store instruction usually needs to modify the information in the memory 14 and/or the cache memory 18 . The data information of the storage instruction can point to the write data, and the source of the write data can be the execution result of instructions such as operation instructions and load instructions, or it can be the data provided by the registers in the processing unit 12 or other storage units, or it can be immediate value.

As shown in Figure 2, the processing unit 12 includes a snoop filter 15, which is arranged near the shared cache L3, and the number of snoop filters 15 can be one or more, for example, different processor cores 120 can correspond to different The same snoop filter 15 can also be corresponded to by multiple processor cores 120 . The snooping filter 15 stores the relevant information of the data stored in the private cache (L1 and L2) of the corresponding processor core 120, and other processor cores 120 can determine the corresponding snooping filter 15 by querying the snooping filter 15. Whether the required data is stored in the private cache of the processor core 120, for example, the processor core 2 can determine whether there is a processor in the private cache corresponding to the processor core 1 by querying the snooping filter 15 corresponding to the processor core 1. Data required for core 2.

The snooping filter 15 stores the relevant information of the data stored in the private cache corresponding to the processor core 120. When the data stored in the private cache changes, the snooping filter 15 needs to update the stored related information, so that the stored related information is consistent with Corresponding to the data stored in the private cache, so that other processor cores 120 can determine whether the required data is stored in the corresponding private cache by querying the snooping filter 15 .

The embodiment of the present application mainly focuses on the process of updating the stored relevant information by the snooping filter 15, and the process of updating the stored relevant information by the snooping filter 15 will be described in detail later.

snoop filter

A multi-core processing unit usually includes a multi-level cache, the top cache has a small capacity but a fast access speed, and the bottom cache has a large capacity but a slow access speed. The top-level cache is private to a certain processor core, and the bottom-level cache is shared by multiple processor cores. For example, the first-level cache (L1cache) is private to a certain processor core and is only used to cache the data of the processor core. The cache (L2 cache) is jointly occupied by multiple processor cores, and is used to cache data of multiple processor cores that share the L2 cache. When the processor core needs to query specific data, it first queries the required data from its private cache, and if the required data cannot be queried, it then queries the next-level cache in turn. If the required data is stored in the private caches of other processor cores, it is necessary to query the required data in the private caches of other processor cores.

Currently, the snoop filter stores information about the data stored in the private cache. In order to ensure that the relevant information stored in the snoop filter can accurately reflect the data stored in the private cache, whenever a private cache proactively deletes a cache line, it needs to send the snoop The filter sends a delete request to delete the relevant information about the deleted cache line from the snoop filter. When the deleted cache line is the same as the data in the memory, there is no need to write back the data at this time, but it is still necessary to send a delete request to the snoop filter to delete the relevant information of the deleted cache line from the snoop filter to ensure snoop The relevant information stored in the filter is in one-to-one correspondence with the cache lines in the private cache. Since the processor core needs to frequently send delete requests to the snoop filter, this will occupy the communication bandwidth between the processor core and outside the processor core, and affect the performance of the processing unit.

The embodiment of the present application is to deal with the problem that deletion of entries by the snoop filter occupies a large communication bandwidth between the core and the outside of the core, and it is mainly realized through the snoop filter 15 . The internal structure of the snoop filter 15 and the implementation process of the embodiment of the present application will be discussed in detail below.

Fig. 3 is a schematic diagram of an internal structure of a snoop filter according to an embodiment of the present application. As shown in FIG. 3 , the snoop filter 15 includes a receiving unit 151 and a snoop unit 152 . After the first cache line is filled into the private cache, the private cache will send coordinate information to the receiving unit 151 , where the coordinate information can indicate the target filling position of the first cache line in the private cache. After the receiving unit 151 receives the coordinate information, the snooping unit 152 can judge whether the identification information of the second cache line is stored in the mapping entry corresponding to the target filling position according to the coordinate information. For the identification information of the second cache line, the identification information of the second cache line is transferred from the mapping entry corresponding to the target filling position to the victim entry, and the identification information of the first cache line is stored in the mapping entry corresponding to the target filling position. , where different cache lines correspond to different identification information.

The snooping filter 15 is used to store the identification information of the filled buffer lines in the private cache, and there may be one or more private caches. Different cache lines correspond to different identification information, and different cache lines can be distinguished according to the identification information, for example, the identification information may be an address of the cache line in memory.

The private cache includes a plurality of filling positions for filling cache lines, and the snooping filter 15 includes a plurality of mapping entries, and the mapping entries in the snooping filter 15 correspond to the filling positions in the private cache one by one, and the mapping entries are used for The identification information of the filled cache line in the corresponding filled position is stored. For example, the private cache includes N filling positions, where N is a positive integer greater than or equal to 2, then the snoop filter 15 includes N mapping entries, and different filling positions correspond to different mapping entries. In addition to including multiple mapping entries, the snooping filter 15 also includes a victim table entry, which is also used to store the identification information of the cache line, but the victim table entry does not belong to a certain filling position, but consists of multiple filling positions. location sharing.

The target filling position in the private cache is filled with a second cache line before. When the first cache line is filled to the target filling position, the private cache sends the coordinate information of the target filling position to the receiving unit 151, and the snooping unit 152 sends the coordinate information of the target filling position to the receiving unit 151. For the received coordinate information, transfer the identification information of the second cache line stored in the mapping entry corresponding to the target filling position to the victim entry, and store the identification information of the first cache line in the mapping entry corresponding to the target filling position . If the second cache line does not need to perform data write-back, after the first cache line is filled to the target filling position, the second cache line is squeezed out from the private cache, and the identification information of the second cache line is stored in the victim entry, It is also ensured that the identification information of the cache lines stored in the private cache is all stored in the snooping filter 15 .

In the embodiment of the present application, the filling position in the private cache corresponds to the mapping entry in the snoop filter 15. After the first cache line is filled to the target filling position, if the mapping entry corresponding to the target filling position The identification information of the second cache line is stored, and the snooping unit 152 transfers the identification information of the second cache line to the victim entry, and stores the identification information of the first cache line into the mapping entry corresponding to the target filling position. Since the filling position corresponds to the mapping entry one by one, when the second cache line does not need to perform data write-back, the private cache only needs to send the coordinate information of the target filling position to the snooping filter 15, and the snooping filter 15 will first cache The identification information of the line is stored in the mapping entry corresponding to the target filling position, and the identification information of the second cache line is transferred to the victim entry, so for the cache line that does not need data write-back, the private cache does not need to send to the snoop filter 15 The delete request can ensure that which private caches cannot store the required data according to the snoop filter, thereby reducing the number of snoops on the private caches of other processor cores, thereby reducing the impact of sending delete requests on the processor core and The occupancy of the communication bandwidth outside the processor core to ensure the performance of the processing unit.

In a possible implementation manner, when the snooping unit 152 determines that the mapping entry corresponding to the target filling position is empty according to the coordinate information, it stores the identification information of the first cache line in the mapping entry corresponding to the target filling position.

Since the filling position in the private cache is in one-to-one correspondence with the mapping entry in the snoop filter 15, if the mapping entry corresponding to the target filling position is empty, it means that the target filling position has not been filled before the first cache line is filled. The cache line, or the cache line filled in the target fill location before the first cache line was filled has been excluded from the private cache. When it is determined according to the coordinate information that the mapping table corresponding to the target filling position is empty, the snooping unit 152 stores the identification information of the first cache line in the mapping entry corresponding to the target filling position, and indicates the private cache through the identification information of the first cache line. Store the first cache line.

In this embodiment of the present application, when the mapping entry corresponding to the target filling position is empty, snooping unit 152 does not need to perform the step of transferring the identification information to the victim entry, and directly transfers the first cache line filled to the target filling position The identification information is stored in the mapping entry corresponding to the target filling position, and then when other processor cores query the snooping filter 15, the private key corresponding to the snooping filter 15 can be determined according to the identification information stored in the mapping entry corresponding to the target filling position. The first cache line is stored in the cache to ensure that the processor core can quickly query the required data.

In a possible implementation manner, the snooping filter 15 includes at least one snooping entry set, each snooping entry set includes a victim entry and at least one mapping entry, and each snooping entry set is related to the Corresponding to a set of filling positions, each set of filling positions includes at least one filling position, the number of mapping entries in each set of snooping entries is equal to the number of filling positions in the corresponding set of filling positions, and in the corresponding snooping In the entry set and the filling position set, different mapping entries correspond to different filling positions. After determining that the identification information of the second cache line is stored in the mapping entry corresponding to the target filling position according to the coordinate information, the snooping unit 152 determines the set of snooping entries to which the mapping entry corresponding to the target filling position belongs, and then stores the second cache line The identification information of is transferred from the mapping entry corresponding to the target filling position to the victim entry included in the snooping entry set.

For example, the private cache includes y filling position sets, and each filling position set includes x filling positions, where both x and y are positive integers greater than or equal to 1. The snoop filter 15 includes y snoop entry sets, and each snoop entry set includes x mapping entries and 1 victim entry. The set of filling positions corresponds to the set of snooping entries. For example, the set of filling positions 0 corresponds to the set of snooping entries 0, the set of filling positions 1 corresponds to the set of snooping entries 1, and the set of filling positions y-1 corresponds to the set of snooping entries The set y-1 corresponds. In the corresponding filling position set and snooping entry set, the filling position corresponds to the mapping table item one by one, for example, the filling position 0 corresponds to the mapping table item 0, the filling position 1 corresponds to the mapping table item 1, and the filling position x-1 corresponds to mapping table entry x-1.

After filling the first cache line into the filling position x-1 in the filling position set 0, the snooping unit 152 will transfer the identification information of the second cache line stored in the mapping entry x-1 in the snooping entry set 0 to snoop the victim entry in entry set 0, and store the identification information of the first cache line in the mapping entry x-1 in snoop entry set 0.

For the same cache line, each time the cache line is stored in the private cache, the cache line needs to be filled into the same fill position set, but the cache line can be filled into different fill positions in the fill position set . For example, each time the cache line L is stored in the private cache, the cache line L is filled into the filling position set 1. The last time the cache line L was filled into the filling position 1 included in the filling position set 1, the next time the cache line L can be filled The cache line L is filled to fill position 0 included in fill position set 1 .

In the embodiment of the present application, the filling positions included in the private cache are divided into a plurality of filling position sets, and the entries included in the snooping filter 15 are respectively divided into a plurality of snooping entry sets, so that the filling position set and the snooping entry set One-to-one correspondence, and the corresponding filling position set and the filling position in the snooping entry set are in one-to-one correspondence with the mapping table item, which is convenient for determining the mapping table item corresponding to the filling position according to the coordinate information, and improving the snooping filter 15 to update the identification information s efficiency. In addition, each snooping entry set also includes a victim entry, and the mapping entries included in the same snooping entry set share a victim entry, which is used to store the transferred identification information, and the same cache line is saved every time. Fill in the same filling location set, so that when other processor cores are querying the snooping filter 15, they only need to query the snooping entry set corresponding to the filling location set used to store the required data, and then it can be determined whether the private cache is The data required by other processor cores is stored without traversing all the identification information stored in the snooping filter 15, thereby improving the efficiency of the processor cores in obtaining required data from the private caches of other processor cores.

In a possible implementation manner, the number of cache line filling requests to be completed corresponding to each filling position set is less than or equal to 1, wherein the buffer line filling request is used to request to fill positions included in the corresponding filling position set Fill the cache line.

Each set of fill locations may include multiple fill locations. For each filling location set, the cache line filling request corresponding to the filling location set is used to request to fill the cache lines in the filling locations included in the filling location set, and the filling location set responds to the cache line filling request after receiving the cache line filling request. A fill request fills a cache line to the corresponding fill location. After a cache line is filled into a filling position, the cache line stored before the filling position will be squeezed out of the private cache. If the cache line that is squeezed out of the private cache needs to be written back, after the cache line is written back During the process, the identification information of the cache line will be stored in the victim entry in the corresponding snoop entry set.

For example, on the basis of the corresponding relationship between the filling location set and the snooping entry set and the corresponding relationship between the filling location and the mapping entry in the foregoing embodiments, the second cache line is stored in the filling location 1 in the filling location set 1. When the private cache receives When a cache line fill request is received, when the first cache line is filled to fill position 1 in fill position set 1, the second cache line will be squeezed out of the private cache, and the identification information of the second cache line will be retrieved from snooping entry set 1. Mapping entry 1 is transferred to the victim entry in snooping entry set 1. If the second cache line is different from the data in the memory, the second cache line needs to be written back. During the process of the second cache line being written back, the identification information of the second cache line is stored in snooping entry set 1 The sacrificial entry in the snoop filter 15 ensures the correspondence between the identification information stored in the snoop filter 15 and the cache line in the private cache.

In the embodiment of the present application, since the set of filling positions corresponds to the set of snooping entries one-to-one, and each set of snooping entries includes a victim entry, if a cache line needs to be written back, the cache line is written back During the process, the identification information of the cache line needs to be stored in the corresponding victim table entry to ensure that the cache line stored in the private cache has corresponding identification information in the snooping filter 15. In order to prevent a cache line from being written back before completion, The identification information of other cache lines is transferred to the victim table entry to overwrite the identification information of the cache line, thus causing the cache line stored in the private cache to have no corresponding identification information in the snoop filter 15, for each filling position set, only allowing less than or equal to one cache line filling request to be completed, so as to ensure that each cache line stored in the private cache has corresponding identification information stored in the snooping filter 15, thereby ensuring that the processor core passes the query The snoop filter 15 looks for the correctness of the required data.

In a possible implementation manner, when the snooping unit 152 transfers the identification information of the second cache line to the victim entry, if the identification information of the third cache line is stored in the victim entry, the The identification information overwrites the identification information of the third cache line in the victim entry.

For example, when transferring the identification information of the second cache line from the mapping entry 1 in the snooping entry set 1 to the victim entry in the snooping entry set 1, if the victim entry in the snooping entry set 1 is empty , then directly store the identification information of the second cache line in the victim entry in the snooping entry set 1, if the victim entry in the snooping entry set 1 stores the identification information of the third cache line, then pass the second cache The identification information of the row overwrites the identification information of the third cache line in the victim entry in the snoop entry set 1, so as to store the identification information of the second cache line in the victim entry in the snoop entry set 1.

In the embodiment of this application, since each set of snooping entries includes a victim entry, when the replaced cache line is different from the data in the memory, it is allowed to initiate a data filling request first, and then initiate a data write-back request without An entry deletion operation is first initiated to the snoop filter 15, and then an entry addition operation is initiated to the snoop filter 15, thereby increasing the speed of filling data into the cache. Since each set of snooping entries includes a victim entry, when the identification information of a cache line is transferred from the mapping entry to the victim entry in the same snooping entry set, even if there are other cache lines stored before the victim Identification information. The cache line corresponding to the identification information no longer exists in the private cache, so it can be overwritten.

In a possible implementation manner, each processor core corresponds to one snoop filter 15, and one processor core may include multiple private caches, and each private cache includes at least one filling location set. The snooping filter 15 includes a plurality of snooping entry sets, and at least two filling position sets corresponding to each snooping entry set are located in at least two private caches, and different snooping entry sets correspond to different filling position sets, Each private cache is located in the same processor core.

Each private cache includes at least one filling location set, and the number of filling location sets included in different private caches may be the same or different. The total number of filling position sets in each private cache is equal to the number of snooping entry sets in the snooping filter 15, each snooping entry set corresponds to a filling position set, and different snooping entry sets correspond to different filling position sets.

For example, the processor core includes a first-level cache and a second-level cache, and both the first-level cache and the second-level cache include y filling position sets. The snooping filter includes 2y sets of snooping entries, wherein y sets of snooping entries correspond to y sets of filling positions in the first-level cache, and another set of y snooping entries corresponds to y sets of filling positions in the second-level cache Correspondingly, and different sets of snooping entries correspond to different sets of filling positions.

In the embodiment of the present application, each set of snooping entries included in the snooping filter 15 may correspond to multiple filling position sets in the same private cache, or may correspond to multiple filling position sets in different private caches, so that the snooping filter 15 is applicable to a processor core including one private buffer, and is also applicable to a processor core including multiple private buffers, which ensures that the snoop filter 15 has strong applicability.

In a possible implementation manner, each filling position included in the same filling position set corresponds to the same index information, and the index information may identify the address segment of the cache line that can be filled by the filling position in the private cache.

In the private cache, index information is assigned to different filling position sets according to the order of adding 1 from 0, that is, the index information of each filling position set is 0, 1, 2..., and the address intervals that can be cached are divided into at least one address segment such that the number of address segments is equal to the number of fill location sets. Similarly, index information is assigned to different address segments according to sequentially increasing from 0 to 1, so that each address segment corresponds to a set of filling positions having the same index information. The address segment where any cache line is located can only be cached in the filling position of the corresponding index information.

Corresponding to the filling position in the private cache, index information and way information can be assigned to the mapping entry in the snoop filter 15, so that the corresponding filling position and mapping entry have the same index information and way information, so that the Multiple mapping entries with the same index information are divided into the same set of snooping entries. In addition, index information is assigned to the victim entry, so that different victim entries correspond to different index information, so that each set of snooping entries includes a victim entry, and the mapping entries and victim entries in the same set of snooping entries have the same index information.

Fig. 4 is a schematic diagram of a private cache and a snooping filter provided by an embodiment of the present application. As shown in FIG. 4 , the private cache includes y filling location sets, and each filling location set includes x filling locations. Different filling position sets correspond to different index information, and the index information corresponding to each filling position set is respectively index0, index1...index(y-1). Each filling position included in the same filling position set has the same index information, and each filling position included in the same filling position set corresponds to different way information, and the way information corresponding to each filling position is way0, way1...way(x-1) .

Corresponding to each filling position included in the private cache, the snoop filter 15 includes y snoop entry sets, and each snoop entry set includes x mapping entries and 1 victim entry. Different snooping entry sets correspond to different index information, and the index information corresponding to each snooping entry set is index0, index1...index(y-1) respectively. Each mapping entry included in the same snooping entry set corresponds to the same index information, and each mapping entry included in the same snooping entry set corresponds to different way information, and the way information corresponding to each mapping entry is way0, way1...way (x-1).

The filling position in the private cache is in one-to-one correspondence with the mapping entry in the snooping filter 15 . The filling position in the private cache is filled with the cache line and the identification information of the cache line, and the mapping entry in the snoop filter 15 stores the identification information of the filled cache line corresponding to the filling position.

In the embodiment of the present application, the address segment of the filling position in the private cache is used as the index information, and the filling position in the private cache is divided into multiple filling position sets according to the index information, so that each filling position included in the same filling position set has The same index information, and each filling position included in the same filling position set corresponds to different road information, each mapping entry included in snooping filter 15 has different index information and road information, so that the same index information and road information The filling position corresponds to the mapping table item, so as to realize the one-to-one correspondence between the filling position and the mapping table item.

In a possible implementation manner, the identification information may be address information of the cache line in the memory.

In the embodiment of the present application, since different cache lines have different addresses in the memory, the address information of the cache line in the memory can be used as the identification information of the cache line, so that different cache lines can be distinguished according to the identification information, which is convenient The processor core searches the required data from the private caches of other processor cores according to the identification information of the cache line to ensure the efficiency of the processor core to search for the required data, thereby ensuring the performance of the processing unit.

snoop filter method

Fig. 5 is a flow chart of a snoop filtering method according to an embodiment of the present application, and the snoop filtering method may be executed by the snoop filter 15 in the above embodiment. As shown in Figure 5, the snooping and filtering method includes the following steps:

Step 501: Receive the coordinate information sent by the private cache after the first cache line is filled into the private cache, where the coordinate information is used to indicate the target filling position of the first cache line in the private cache;

Step 502: When it is determined according to the coordinate information that the identification information of the second cache line is stored in the mapping entry corresponding to the target filling position, transfer the identification information of the second cache line from the mapping entry corresponding to the target filling position to the victim entry , and store the identification information of the first cache line in the mapping entry corresponding to the target fill position, where different cache lines correspond to different identification information.

In the embodiment of the present application, the filling position in the private cache corresponds to the mapping table item one by one. After the first cache line is filled to the target filling position, if the mapping table item corresponding to the target filling position stores the second cache line The identification information of the second cache line is transferred to the victim entry, and the identification information of the first cache line is stored in the mapping entry corresponding to the target filling position. Since the filling position corresponds to the mapping table item one by one, when the second cache line does not need to perform data write-back, the identification information of the first cache line is stored in the mapping table item corresponding to the target filling position, and the second cache line’s The identification information is transferred to the victim table entry. Therefore, for the cache line that does not need data write-back, the private cache does not need to send a delete request to the snoop filter, and it can ensure that the private cache cannot store the required data according to the snoop filter. The number of times of snooping on the private caches of other processor cores is reduced, thereby reducing the occupancy of the communication bandwidth between the processor core and outside the processor core by sending delete requests, thereby ensuring the performance of the processing unit.

In a possible implementation manner, when it is determined according to the coordinate information that the mapping entry corresponding to the target filling position is empty, the identification information of the first cache line is stored in the mapping entry corresponding to the target filling position.

In a possible implementation manner, transferring the identification information of the second cache line from the mapping entry corresponding to the target filling position to the victim entry includes: determining the set of snooping entries to which the mapping entry corresponding to the target filling position belongs, And transfer the identification information of the second cache line from the mapping entry corresponding to the target filling position to the victim entry included in the snooping entry set, wherein the snooping filter includes at least one snooping entry set, and each snooping entry set Including the victim table entry and at least one mapping table entry, each snooping table entry set corresponds to a filling position set in the private cache, each filling position set includes at least one filling position, and each snooping table entry set has a mapping table entry The number of is equal to the number of filling positions in the corresponding filling position set, and different mapping entries in the corresponding snooping entry set and filling position set correspond to different filling positions.

In a possible implementation manner, transferring the identification information of the second cache line from the mapping entry corresponding to the target filling position to the victim entry includes: if the victim entry stores the identification information of the third cache line, by The identification information of the second cache line overwrites the identification information of the third cache line in the victim entry, where the number of cache line filling requests to be completed corresponding to each filling position set is less than or equal to 1, and the cache line filling request is used for the request The cache line is filled to the fill locations included in the corresponding fill location set.

It should be noted that, since the details of the snoop filter method have been described in detail in the snoop filter part of the above embodiment in conjunction with the structural schematic diagram, the specific process can refer to the description in the aforementioned snoop filter embodiment, and will not be repeated here. .

computer storage media

The present application also provides a computer-readable storage medium storing instructions for causing a machine to execute the snooping filtering method as described herein. Specifically, a system or device equipped with a storage medium may be provided, on which a software program code for realizing the functions of any of the above embodiments is stored, and the computer (or CPU or MPU of the system or device) ) to read and execute the program code stored in the storage medium.

In this case, the program code itself read from the storage medium can realize the function of any one of the above-mentioned embodiments, so the program code and the storage medium storing the program code constitute a part of the present application.

Examples of storage media for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), Tape, non-volatile memory card, and ROM. Alternatively, the program code can be downloaded from a server computer via a communication network.

computer program product

An embodiment of the present application further provides a computer program product, including computer instructions, where the computer instruction instructs a computing device to perform any corresponding operation in the foregoing multiple method embodiments.

The commercial value of the embodiment of this application

In the embodiment of the present application, when solving the problem that the snoop filter occupies a large communication bandwidth between the processor core and the outside of the processor core, by setting a sacrificial entry, the private cache notifies the coordinate information corresponding to the snoop filter when the cache line is filled, and snoop The filter stores the identification information of the filled cache line in the corresponding mapping table item. If there is other identification information in the mapping table item, but the cache line corresponding to the identification information does not need to be written back, it only needs to inform the listener of the filter coordinates information, the snooping filter will store the identification information of the original cache line in the victim entry, so that the private cache does not need to send a delete request to the snooping filter, reducing the communication bandwidth usage between the processor core and outside the processor core. Thus, the performance of the processing unit is guaranteed. Due to the addition of sacrifice entries and the restriction that only one filling request is allowed in the same filling location set, when the replaced cache line is different from the data in memory, it is allowed to initiate a data filling request first, and then initiate a data write-back request, which guarantees the speed at which data fills the cache.

It should be understood that each embodiment in this specification is described in a progressive manner, the same or similar parts of each embodiment can be referred to each other, and each embodiment focuses on the difference from other embodiments . In particular, for the method embodiments, since they are basically similar to the methods described in the device and system embodiments, the description is relatively simple, and for relevant parts, please refer to some descriptions of other embodiments.

It should be understood that the foregoing describes specific embodiments of the present specification. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. Multitasking and parallel processing are also possible or may be advantageous in certain embodiments.

It should be understood that describing an element herein in the singular or showing only one in a drawing does not mean limiting the number of that element to one. Furthermore, modules or elements described or illustrated herein as separate may be combined into a single module or element, and modules or elements described or illustrated herein as a single may be split into a plurality of modules or elements.

It should also be understood that the terms and expressions used herein are for description only, and one or more embodiments of this specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features shown and described (or parts thereof), and it should be recognized that various modifications may also be included within the scope of the claims. Other modifications, changes and substitutions may also exist. Accordingly, the claims should be read to cover all such equivalents.

Claims (14)

1. A snoop filter comprising:

the device comprises a receiving unit and a processing unit, wherein the receiving unit is used for receiving coordinate information sent by a private cache after a first cache line is filled into the private cache, and the coordinate information is used for indicating a target filling position of the first cache line in the private cache;

and the snooping unit is configured to, when it is determined that the mapping table entry corresponding to the target filling position stores identification information of a second cache line according to the coordinate information, transfer the identification information of the second cache line from the mapping table entry corresponding to the target filling position to a victim table entry, and store the identification information of the first cache line in the mapping table entry corresponding to the target filling position, where different cache lines correspond to different identification information.

2. The snoop filter as claimed in claim 1, wherein,

and the snooping unit is configured to store the identification information of the first cache line in the mapping table entry corresponding to the target filling position when it is determined that the mapping table entry corresponding to the target filling position is empty according to the coordinate information.

3. The snoop filter of claim 1, wherein said snoop filter comprises at least one set of snoop entries, each set of snoop entries comprising a victim entry and at least one mapping entry, each set of snoop entries corresponding to a set of fill locations in said private cache, each set of fill locations comprising at least one fill location, a number of mapping entries in each set of snoop entries being equal to a number of fill locations in a corresponding set of fill locations, different mapping entries in a corresponding set of snoop entries and a set of fill locations corresponding to different fill locations;

and the snoop unit is configured to determine a snoop table entry set to which a mapping table entry corresponding to the target filling position belongs when it is determined according to the coordinate information that identification information of a second cache line is stored in the mapping table entry corresponding to the target filling position, and transfer the identification information of the second cache line from a mapping table entry corresponding to the target filling position to a victim table entry included in the snoop table entry set.

4. The snoop filter as claimed in claim 3, wherein the number of cache line fill requests to be completed for each set of fill locations is less than or equal to 1, a cache line fill request requesting a cache line to be filled to a fill location included in the corresponding set of fill locations.

5. The snoop filter of claim 4 wherein,

the snooping unit is configured to, when transferring the identifier information of the second cache line to a victim entry, if the identifier information of a third cache line is stored in the victim entry, overwrite the identifier information of the third cache line in the victim entry with the identifier information of the second cache line.

6. The snoop filter of claim 3 wherein the snoop filter comprises at least two sets of snoop entries, at least two sets of fill locations corresponding to the at least two sets of snoop entries being located in at least two private caches, different sets of snoop entries corresponding to different sets of fill locations, the at least two private caches being located within the same processor core.

7. The snoop filter of claim 3 wherein each fill location in a same set of fill locations corresponds to the same index information identifying the address segment of the cache line that the fill location in the private cache can fill.

8. A snoop filter as claimed in any one of claims 1 to 7 wherein the identification information comprises address information in memory for the corresponding cache line.

9. A processing unit, comprising:

the snoop filter as claimed in any one of claims 1-8;

and the at least two processor cores are used for inquiring the snoop filter and determining the private cache where the required data is located.

10. A computing device, comprising:

the processing unit of claim 9;

and the memory is coupled with the processing unit and used for storing the data required by the processing unit.

11. A snoop filtering method comprising:

receiving coordinate information sent by a private cache after a first cache line is filled into the private cache, wherein the coordinate information is used for indicating a target filling position of the first cache line in the private cache;

and when determining that the mapping table entry corresponding to the target filling position stores the identification information of a second cache line according to the coordinate information, transferring the identification information of the second cache line from the mapping table entry corresponding to the target filling position to a sacrifice table entry, and storing the identification information of the first cache line in the mapping table entry corresponding to the target filling position, wherein different cache lines correspond to different identification information.

12. The snoop filtering method as claimed in claim 11, wherein the method further comprises:

and when the mapping table entry corresponding to the target filling position is determined to be empty according to the coordinate information, storing the identification information of the first cache line into the mapping table entry corresponding to the target filling position.

13. The snoop filtering method of claim 11, wherein the transferring identification information of the second cache line from a mapping table entry corresponding to the target fill location to a victim entry comprises:

determining a snoop entry set to which a mapping entry corresponding to the target filling position belongs, and transferring identification information of the second cache line from a mapping table entry corresponding to the target filling position to a victim entry included in the snoop entry set, wherein the snoop filter includes at least one snoop entry set, each snoop entry set includes a victim entry and at least one mapping entry, each snoop entry set corresponds to one filling position set in the private cache, each filling position set includes at least one filling position, the number of mapping entries in each snoop entry set is equal to the number of filling positions in the corresponding filling position set, and different mapping entries in the corresponding snoop entry set and the filling position set correspond to different filling positions.

14. The snoop filtering method of claim 13, wherein the transferring identification information of the second cache line from a mapping table entry corresponding to the target fill location to a victim entry comprises:

and if the sacrifice table entry stores identification information of a third cache line, covering the identification information of the third cache line in the sacrifice table entry by the identification information of the second cache line, wherein the number of cache line filling requests to be completed, which correspond to each filling position set, is less than or equal to 1, and the cache line filling requests are used for requesting to fill the cache line to the filling positions included in the corresponding filling position set.

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