CN115273948B

CN115273948B - Memory operation method, memory and memory system

Info

Publication number: CN115273948B
Application number: CN202210889977.8A
Authority: CN
Inventors: 杨名; 向莉; 魏镜; 张扬; 栗山正男; 梁轲
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-07-27
Filing date: 2022-07-27
Publication date: 2025-07-18
Anticipated expiration: 2042-07-27
Also published as: CN115273948A; CN120808847A

Abstract

The disclosed embodiment provides a memory operation method, a memory and a memory system. The memory includes a memory cell array composed of a plurality of memory blocks, each of which includes at least a plurality of memory strings and a plurality of word lines coupled to the memory strings; the operation method includes: applying an erase voltage to a memory block to be erased in a first time period; turning on the top selection tube and the bottom selection tube of each memory string in the memory block to be erased in a second time period after the first time period, so that the charge in the channel of each memory string after erasure is released from both ends of the memory string; performing an erase verification operation on the memory block.

Description

Memory operation method, memory and memory system

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a memory operation method, a memory, and a memory system.

Background

Flash memory is a low cost, high density, non-volatile solid state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. The gate of the flash memory cell has a structure including a tunnel insulating layer, a floating gate electrode, a dielectric layer, and a control gate. Because the nonvolatile solid-state memory can still store data after power is turned off, special erase operations are needed to be implemented if the data needs to be deleted. The erasing operation is to apply a voltage between the gate electrode and the substrate of the flash memory cell to release the charges stored in the floating gate electrode, thereby changing the threshold voltage of the memory cell and further achieving the purpose of data erasing.

However, after the erasing operation is performed on the memory cell, the charges remaining in the channel often interfere with the reading and writing of the subsequent data, and therefore, how to clean up the charges remaining after the erasing is an important operation for memory control.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a memory operation method, a memory, and a memory system.

In a first aspect, embodiments of the present disclosure provide a method of operating a memory including a memory cell array composed of a plurality of memory blocks, each of the memory blocks including at least a plurality of memory strings and a plurality of word lines coupled to the memory strings, the method comprising:

Applying an erase voltage to a memory block to be erased for a first period of time;

In a second period after the first period, switching on a top selection tube and a bottom selection tube of each storage string in the storage block to be erased so as to release charges in channels of each storage string after being erased from two ends of the storage string;

and executing an erasure verification operation on the storage block.

In some embodiments, the switching on the top selection tube and the bottom selection tube of each memory string in the memory block to be erased in the second period after the first period includes:

applying a first turn-on voltage to a top select gate line in the memory block, wherein the top select gate line is connected to a control electrode of the top select transistor;

Applying a second turn-on voltage to a bottom select gate line in the memory block, wherein the bottom select gate line is connected to a control electrode of the bottom select transistor

And in the second period, applying a first gating voltage to a first gating switch connected to the top selection gate line and a second gating switch connected to the bottom selection gate line synchronously, so that the first switching-on voltage is applied to the top selection tube and the second switching-on voltage is applied to the bottom selection tube.

In some embodiments, the first turn-on voltage is equal to the second turn-on voltage.

In some embodiments, the method further comprises:

And applying a second gating voltage to the first gating switch and the second gating switch in a first period, wherein the second gating voltage is smaller than the first gating voltage.

In some embodiments, the method further comprises:

and in the second period, conducting a discharge path in a page buffer to which a bit line corresponding to the memory string is coupled.

In some embodiments, the turning on the discharge path in the page buffer to which the bit line corresponding to the memory string is coupled includes:

a third turn-on voltage is applied to a control switch in a discharge path in a page buffer to which the bit line is coupled.

In some embodiments, the method further comprises:

during the second period, a turn-off voltage is applied to a control switch between the bit line and a sense node in the page buffer to disconnect a precharge path in the page buffer and a path between latches.

In some embodiments, the applying an erase voltage to the memory block to be erased for a first period of time includes:

applying a ground voltage to each word line of the memory block to be erased in the first period;

the erase voltages are applied simultaneously to the respective bit lines or source lines of the memory block to be erased.

In some embodiments, the method further comprises:

the erase voltages applied to the respective bit lines or source lines are switched to a ground voltage during the second period.

In some embodiments, the performing an erase verify operation on the memory block includes:

applying an erase verify voltage to a selected word line on the memory block, wherein the selected word line is any word line on the memory block;

applying a turn-on voltage to unselected word lines on the memory block, wherein the turn-on voltage is greater than or equal to a maximum threshold voltage of a memory cell;

and reading the memory cell corresponding to the selected word line to obtain a verification result of the erase verification operation.

In a second aspect, embodiments of the present disclosure provide a memory comprising:

Peripheral circuits and memory cell arrays composed of a plurality of memory blocks;

wherein the peripheral circuitry is configured to perform at least the method of operation of any of the embodiments described above.

In a third aspect, embodiments of the present disclosure provide a memory system comprising:

A memory and a controller;

The memory comprises at least peripheral circuitry and a memory cell array comprising a plurality of memory blocks, the peripheral circuitry being configured at least to perform the method of operation of any of the embodiments described above.

According to the operation method of the memory, the method that the top selection tube and the bottom selection tube are simultaneously opened is adopted for solving the problem of channel charge residues in the memory block erasing process, so that channel charges can be released from two ends of a channel, the channel charge residues after erasing are reduced, and the problem that channel potential is raised by the channel charges to generate subsequent reading errors is further reduced.

Drawings

FIG. 1 is a schematic diagram of an exemplary system provided in an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a memory card according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of a Solid State Drive (SSD) according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a memory including a memory cell array and peripheral circuits according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a memory according to an embodiment of the disclosure;

FIG. 6 is a schematic diagram of a page buffer in a peripheral circuit of a memory according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a memory string in a memory according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of word lines and common word lines in a memory according to an embodiment of the disclosure;

FIG. 9 is a schematic diagram of a top select transistor and a bottom select transistor of a memory string for controlling discharge of channel charges in a memory according to an embodiment of the present disclosure;

FIG. 10 is a schematic waveform diagram of a memory erase operation provided by an embodiment of the present disclosure;

FIG. 11 is a flowchart of a method of operating a memory according to an embodiment of the present disclosure;

FIG. 12 is a schematic waveform diagram of an erase operation in a method of operating a memory according to an embodiment of the present disclosure;

FIG. 13 is a schematic diagram illustrating a control switch state of a page buffer in a method for operating a memory according to an embodiment of the disclosure;

FIG. 14 is a schematic diagram of a memory cell state distribution in a memory according to an embodiment of the disclosure;

FIG. 15 is a schematic diagram of a memory according to an embodiment of the disclosure;

fig. 16 is a schematic structural diagram of a memory system according to an embodiment of the disclosure.

Detailed Description

In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1, an exemplary system 10 is shown in an embodiment of the present disclosure, the exemplary system 10 may include a host 20 and a storage system 30. Among other things, exemplary system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having memory 34 therein, host 20 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on a chip (SoC) (e.g., an Application Processor (AP)) of an electronic device.

In embodiments of the present disclosure, host 20 may be configured to send data to storage system 30 or receive data from storage system 30. Here, the storage system 30 may include a controller 32 and one or more memories 34. The Memory 34 may include, but is not limited to, NAND Flash Memory (NAND FLASH Memory), vertical NAND Flash Memory (VERTICAL NAND FLASH Memory), NOR Flash Memory (NOR Flash Memory), dynamic random access Memory (Dynamic Random Access Memory, DRAM), ferroelectric random access Memory (Ferroelectric Random Access Memory, FRAM), magnetic random access Memory (Magnetoresistive Random Access Memory, MRAM), phase change random access Memory (PHASE CHANGE Random Access Memory, PCRAM), resistive random access Memory (RESISTIVE RANDOM ACCESS MEMORY, RRAM), nano random access Memory (Nano Random Access Memory, NRAM), and the like.

On the other hand, the controller 32 may be coupled to the memory 34 and the host 20 and used to control the memory 34. By way of example, the controller may be designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) flash drive, or other medium for use in an electronic device such as a personal computer, digital camera, mobile phone, or the like. In some embodiments, the controller may also be designed to operate in a high duty cycle environment, SSD, or embedded multimedia card (eMMC), which serves as a data storage and enterprise storage array for mobile devices such as smartphones, tablet computers, laptop computers, and the like. Further, the controller may manage data in the memory and communicate with the host. The controller may be configured to control memory read, erase, and program operations, and the like, may also be configured to manage various functions with respect to data stored or to be stored in memory, including but not limited to bad block management, garbage collection, logical-to-physical address conversion, wear leveling, and the like, and may also be configured to process Error Correction Codes (ECCs) with respect to data read from or written to memory. In addition, the controller may perform any other suitable function, such as formatting the memory, or communicating with an external device (e.g., host 20 in FIG. 1) according to a particular communication protocol. Illustratively, the controller may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

In the disclosed embodiments, the controller and the one or more memories may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system may be implemented and packaged into different types of terminal electronics. As shown in fig. 2, the controller 32 and the single memory 34 may be integrated into a memory card 40. Memory card 40 may include a PC card (PCMCIA, personal computer memory card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, or the like. The memory card 40 may also include a memory card connector 42 that couples the memory card 40 with a host (e.g., the host 20 in fig. 1). In another embodiment as shown in fig. 3, the controller 32 and the plurality of memories 34 may be integrated into the SSD 50. The SSD 50 may also include an SSD connector 52 that couples the SSD 50 with a host (e.g., host 20 in FIG. 1). In some embodiments, the storage capacity and/or operating speed of SSD 50 is greater than the storage capacity and/or operating speed of memory card 40.

It should be noted that, the memory according to the embodiments of the present disclosure may be a semiconductor memory, which is a solid-state electronic device that is manufactured by using a semiconductor integrated circuit process and stores data information. Illustratively, FIG. 4 is a schematic diagram of an alternative memory 60 in an embodiment of the present disclosure. Wherein the memory 60 may be the memory 34 of fig. 1-3. As shown in fig. 4, the memory 60 may be composed of a memory cell array 62, a peripheral circuit 64 coupled to the memory cell array 62, and the like. Here, the memory cell array may be a NAND flash memory cell array in which memory cells are provided in the form of an array of NAND memory strings 66, each NAND memory string 66 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 66 can include multiple memory cells coupled in series and stacked vertically. Wherein each memory cell is held at a continuous analog value, e.g., voltage or charge, depending on the number of electrons trapped in the memory cell region. In addition, each memory cell in the above-described memory cell array 62 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

In embodiments of the present disclosure, the memory cell described above may be a single layer memory cell (SINGLE LEVEL CELL, SLC) that has two possible memory states and thus can store one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In other embodiments, each memory cell is a Multi-layer memory cell (Multi LEVEL CELL, MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-layer memory cell (TRIPLE LEVEL CELL, TLC)), or four bits per cell (also known as a four-layer memory cell (Quad LEVEL CELL, QLC)). Each MLC may be programmed to take a range of possible nominal stored values. For example, if each MLC stores two bits of data, the MLC may be programmed to take one of three possible program levels from the erased state by writing one of three possible nominal storage values to the memory cell. Wherein the fourth nominal stored value may be used for the erased state.

In the embodiments of the present disclosure, the peripheral circuits described above may be coupled to the memory cell array through Bit lines (Bit lines, BL), word lines (Word lines, WL), source lines (Source lines), source select gates (Source SELECT GATE, SSG), and drain select gates (DRAIN SELECT GATE, DSG). Here, the peripheral circuitry may include any suitable analog, digital, and mixed signal circuitry for facilitating operation of the memory cell array by applying and sensing voltage signals and/or current signals to and from each target memory cell via the bit lines, word lines, sources, SSGs, and DSGs. Furthermore, it is possible to provide a device for the treatment of a disease. The peripheral circuits may also include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. As illustrated by way of example in fig. 5. The peripheral circuit 70 includes a Page Buffer/sense amplifier 71, a column decoder/bit line driver 72, a row decoder/word line driver 73, a voltage generator 74, a control logic unit 75, a register 76, an interface 77, and a data bus 78. It should be appreciated that the peripheral circuitry 70 described above may be identical to the peripheral circuitry 64 of fig. 4, and in other embodiments, the peripheral circuitry 70 may also include additional peripheral circuitry not shown in fig. 5.

As shown in FIG. 6, a page buffer 90 is shown in one embodiment of the present disclosure. The page buffer 90 may be coupled with the memory cell array 80 via bit lines BL. Each page buffer includes a register set 91 connected through a bit line bias switch VBL _BIAS and a discharge path connected to ground through a discharge switch VBL _DISCH. In addition, the page buffer may further include at least one sensing node located between the register set and the word line. As shown in fig. 6, the page buffer 90 includes a sensing node SO and a sensing node SO2, and a select pipe VSO _BLK is further included between the two sensing nodes. In addition, the page buffer may further include a bit line switch V _PASS between the bit lines for controlling whether or not the entire page buffer communicates with the bit lines.

In the disclosed embodiment, the memory cell array may be composed of memory strings 700 as shown in fig. 7, each of which is formed by stacking a plurality of memory cells connected by a channel 720 perpendicular to a substrate 710. Word line 730 is perpendicular to the channel and may surround the channel for use as a gate electrode of a memory cell. The memory structure 740 between the gate electrode and the channel of the memory cell includes at least a tunneling layer 741, a memory layer 742 (charge trapping layer), a blocking layer 743, and the like. The memory structure may typically be a tunneling layer comprising silicon oxide, a memory layer comprising silicon nitride and a blocking layer comprising silicon oxide, so-called ONO structure.

Each memory cell may be in an erased state or a programmed state, and there may be a plurality of programmed states. The erased state is used to represent the original state of the memory cell that has not been programmed, or the state that has not been stored with data, and can be understood as the "0" state of the stored data, and the programmed state is used to represent the state that has different data stored. For example, for the above-described SLC memory cell, it is capable of holding 1 bit (bit) data, so only one erased state is required to represent data "0" and one programmed state represents data "1". For the memory cell of the MLC described above, which is capable of holding 2 bits of data, one erased state is required to represent data "00", and 3 programmed states represent data "01", "10", and "11".

The erase state and the program state are substantially represented by the threshold voltages of the memory cells. Since the memory cell having the ONO structure can achieve charge trapping, by applying a voltage between the gate electrode and the channel, charge can be made to pass through the tunneling layer to the memory layer, that is, the charge trapping layer, by utilizing the tunneling effect, so that the charge is trapped in the memory layer. The change in the amount of charge in the memory layer results in a change in the threshold voltage of the memory cell. Thus, if data is to be stored in the memory cell, it is possible to inject a corresponding charge into the memory layer. The process of injecting charge may be referred to herein as "programming," i.e., adjusting the state of a memory cell from an erased state to a different programmed state by programming.

Accordingly, if the data in the memory cell is to be erased, that is, the memory cell is to be recovered from the programmed state to the erased state, a reverse process is required to be applied between the gate electrode and the channel, and the charges bound in the memory layer are returned to the channel through the tunneling layer by using the tunneling effect, so that the charges in the memory layer are released, and the threshold voltage of the memory cell is returned to the range where the erased state is located.

In an embodiment of the present disclosure, the memory cell array of the above memory may be formed of a plurality of memory blocks (blocks), each memory block has a source, a channel bottom of each memory string in the memory block may be connected to a SL of the source through a doped region in the substrate, and a top of the memory string is connected to the BL. The memory block is the minimum unit of erase operation, and when erasing, a high voltage may be applied to SL or BL while maintaining the channel of the memory string in a non-conductive state, for example, 0V voltage is applied to the word line of each memory cell on the memory string. At this time, a high voltage of BL or SL is coupled to the channel, raising the voltage of the channel, so that charges stored in the memory layer tunnel into the channel, thereby achieving erasure.

In some embodiments, after the application of the erase voltage, it may be confirmed whether the erase was successful by a verification process. The verification process is similar to the principle of a read operation, for example, a verification voltage using an erased state is applied to a WL (which may be referred to as a select word line, sel Blk WL) corresponding to a memory cell to be verified, and a pass voltage Vpass is applied to other WLs (unselected word lines), and then a read is performed through BL. If a voltage is read, i.e., the memory cell is turned on, it indicates that the threshold voltage of the memory cell is less than the verify voltage, i.e., the memory cell has been successfully erased. If the voltage is not read, i.e., the memory cell is not turned on, it indicates that the threshold voltage of the memory cell is greater than the verify voltage, i.e., the memory cell has not been successfully erased.

However, it will be appreciated that since the charges in the memory layer return to the channel after erase, and the channel is substantially non-conductive, these charges can affect subsequent reading or other operations. Therefore, it is also necessary to release the charge in the channel after erasing to ensure that the subsequent operation is not affected.

For the verification process described above, the channel discharges at the start of verification due to the charge remaining in the channel. At this time, the current generated by the discharge will generate coupling effect to the selected word line, resulting in the voltage of the selected word line being pulled down, even reaching negative voltage. And since the individual Word lines of the memory block are also coupled to a common Word Line (LWL), as shown in fig. 8. Such that the pull-down of the selected word line sel_wl causes the voltage leakage of the unselected word line unsel_wl, which in turn causes the threshold voltage to shift after the verification is completed, and the subsequent read operation is erroneous.

In some embodiments, the channel portion may be made conductive by opening a Bottom select tube (Bottom SELECT GATE, BSG) of the memory string. As shown in fig. 9, the BSG voltage is raised after erasure by raising the voltage of SD Vg (STRING DRIVER GATE). Here, SD Vg is a switch for controlling whether or not a voltage is applied to a string selection line of each memory string in the memory block. When the SD Vg is turned on, the voltage signals applied to the BSG line and the TSG line are applied to the BSG gate and the TSG gate. As shown in fig. 10, the SD Vg is maintained at 6V in the preparation phase and the erase phase, and the erase voltage Vers is applied to the BL or SL in the erase phase, so that the voltages of the BSG and TSG are coupled from the low voltage vss to the higher high voltage. When the application of the erase voltage is completed, the recovery phase is entered, and the voltages of the BSG and TSG fall back, for example, about 3V. At this time, the voltage of the SD Vg is raised to 15V, so that the TSG and the BSG are gated, and since the voltage of 6V is applied to the BSG and the voltage of 0V is applied to the TSG, the BSG is turned on again to achieve the discharging purpose, and the TSG is kept in the off state, as shown in fig. 9.

Since the BSG is located at the bottom of the memory string, the channel discharge is performed by opening one end of the BSG, so that charges can rapidly flow to the substrate for subsequent erase verification operation.

However, with the increase of the number of memory layers, it may be difficult to meet the discharge demand after the erase by only turning on the BSG, a longer discharge period is required, and the above-described abnormality after the erase verification is still easily caused by the charge residue.

Accordingly, as shown in fig. 11, the embodiment of the present disclosure provides a method of operating a memory including a memory cell array composed of a plurality of memory blocks, each memory block including at least a plurality of memory strings and a plurality of word lines coupled to the memory strings, including:

step S101, applying an erasing voltage to a memory block to be erased in a first period;

Step S102, in a second period after the first period, switching on a top selection tube and a bottom selection tube of each storage string in the storage block to be erased so as to release charges in channels of each storage string after being erased from two ends of the storage string;

step S103, executing an erasure verification operation on the storage block.

In the embodiment of the disclosure, after the erasing voltage is applied to the memory block, the top selection tube and the bottom selection tube are simultaneously turned on, so that charges in the channel are released from two ends of the channel, the discharging speed is further increased, residual charges can be further reduced, and the discharging is more sufficient.

In some embodiments, in the step S101, applying the erase voltage to the memory block to be erased includes:

Applying an erase voltage to the source of the memory block to be erased while floating the bit lines to which the corresponding memory strings are connected, or applying an erase voltage to the bit lines of the memory block to be erased while floating the source, or applying an erase voltage to the source of the memory block and the bit lines.

In the erasing process, an erasing voltage is applied to the source electrode, that is, a high level voltage is applied to the SL, and the BL is floated, so that the channel of the entire memory string is not turned on, but is coupled to a high level by the high level voltage of the SL, thereby generating a voltage difference with the gate (word line) of each memory cell. Similarly, erasing of the memory block can be achieved by applying an erase voltage to the bit lines, i.e., applying a high voltage to the BL, while floating the source SL so that the channel is coupled to a high level. In addition, an erase voltage can be applied to both BL and SL to raise the potential of the channel to a high level as a whole, thereby realizing the erase of the memory block.

It will be appreciated that the application of the erase voltage to the memory block to be erased may be a high voltage applied to either BL or SL during which the floating channel is coupled to a high level, while TSG and BSG may be coupled from a low state to a high state. The other WL may be grounded or provide a low voltage. Holes in P+ (P type heavily doped) polysilicon enter a channel under the action of an electric field, then enter a storage layer under the action of the electric field generated by the voltage difference between WL and the channel, and are neutralized with electrons in the storage layer, so that the erasing effect is realized.

After this process is finished, the application of the erase voltage is stopped, so that holes stop continuing into the memory layer. At this time, a large amount of residual holes exist in the channel.

Therefore, through the above step S102, the top select tube and the bottom select tube of the memory string are opened, so that the remaining charges are discharged.

In some embodiments, in the step S102, in a second period after the first period, a top selection pipe and a bottom selection pipe of each storage string in the storage block are turned on, including:

Applying a first turn-on voltage to a top select gate line in the memory block, wherein the top select gate line is connected to a control electrode of a top select pipe;

Applying a second start voltage to a bottom select gate line in the memory block, wherein the bottom select gate line is connected to a control electrode of a bottom select tube;

And applying a gate voltage to the first gate switch connected to the top selection gate line and the second gate switch connected to the bottom selection gate line in synchronization during a second period, so that the first turn-on voltage is applied to the top selection tube and the second turn-on voltage is applied to the bottom selection tube.

The memory block is composed of a multi-layered stacked structure in which alternately stacked conductive layers and insulating layers are arranged in a plane perpendicular to the direction of the memory string channel, each conductive layer being used as a word line of a memory cell to control the memory cell of the ONO structure at the channel side wall. The conductive layer at the top of the stack, i.e., top select gate line TSG, and the conductive layer at the bottom of the stack, i.e., bottom select gate line BSG, are shown in fig. 9.

In some embodiments, the first and second turn-on voltages V1 and V2 may be applied to the top and bottom select gate lines TSG and BSG, respectively, during the second period, so that the select transistors at both ends of the channel are turned on.

In addition, the TSG and the BSG may be connected to a gate switch, respectively. I.e. the first gating switch sd_vg1 is connected to the TSG for gating the TSG. The second gating switch sd_vg2 is connected to the BSG for gating the BSG.

Therefore, the time of the TSG and the BSG applied to the transistors at the two ends of the channel can be controlled by gating the switch without changing the voltage applied to the TSG and the BSG, so that the purpose of controlling the on-off of the channel is achieved.

In some embodiments, the first turn-on voltage is equal to the second turn-on voltage. The top selection grid line and the bottom selection grid line are provided with equal starting voltages, so that the top selection tube and the bottom selection tube have the same starting degree, and charges are conveniently released from a channel. Also, the TSG and the BSG may be connected to the same gating switch SD. After the end of the above-described application of the erase voltage, the second turn-on voltage may be applied to the bottom select gate line by turning on the gate switch SD while applying the first turn-on voltage to the top select gate line. Because the top select gate line is connected to the control electrode of the TSG and the bottom select gate line is connected to the control electrode of the BSG, the first and second turn-on voltages can be applied to the TSG and the BSG synchronously, so that the TSG and the BSG are turned on and channel charges are released.

It should be noted that, the first period may be in the erasing stage shown in fig. 12, and the second period may be in the recovery stage after the erasing stage.

In some embodiments, the method further comprises:

the first gate switch and the second gate switch are applied with a second gate voltage during a first period, and the second gate voltage is smaller than the first gate voltage.

Illustratively, as shown in fig. 12, the gate switch SD connected to the TSG and BSG during the erase phase may provide a lower second gate voltage, such as ground, or a voltage of 6V, or the like. The TSG and BSG are actually in an off state due to the higher channel potential during the erase phase.

And switching to the second period, such as the recovery stage in fig. 12, the gate voltage of the gate switch SD may be raised to the first gate voltage, for example, 15V. At this time, the BSG and the TSG are turned on synchronously, so that two ends of the channel are in a conductive state, and thus the channel charges are conveniently released from the two ends.

In some embodiments, the method further comprises:

And in a second period, turning on a discharge passage in a page buffer to which a bit line corresponding to the memory string is coupled.

In some embodiments, the turning on a discharge path in a page buffer to which a bit line corresponding to the memory string is coupled includes:

In some embodiments, the method further comprises:

It will be appreciated that the memory string is connected to the bit line BL, which is connected to other blocks of the peripheral circuit through the page buffer as shown in FIG. 6. Since the bit line is not directly grounded, it is also necessary to provide a path from the bit line BL to ground Gnd when channel charge is discharged by turning on the TSG.

Illustratively, as shown in fig. 13, in the embodiment of the present disclosure, the control switch between BL and the sensing nodes SO and SO2 of the page buffer 90 may be turned off, and the discharge switch of the discharge path may be turned on. Specifically, applying the off-voltage to the bit line bias switch VBL _BIAS and switch VSO _BLK turns off the path while the bit line switch V _PASS, and applying the on-voltage (i.e., the third on-voltage described above) to the discharge switch VBL _DISCH and bit line switch V _PASS turns on the discharge path. Thus, the residual charges in the channel can be released to the discharge path through the bit line, so as to achieve the purpose of rapidly releasing charges.

In addition, it should be noted that the step of applying the erase voltage to the memory block to be erased in the first period of time may specifically include:

In some embodiments, in step S103, performing the erase verify operation on the memory block includes:

The above-described verification process may be sequentially performed for different word lines, and similar to the read process, an erase verification voltage is applied to a selected word line of a memory block and an on voltage is applied to other word lines. The process of reading the memory cell corresponding to the selected word line specifically includes applying a voltage to the bit line, and detecting whether the channel is turned on or not through a sensing node connected to the bit line. If the channel is on, it indicates that the erase verify voltage is greater than the threshold voltage of the memory cell to which the selected word line is coupled, i.e., the memory cell is erased successfully. If the channel is not conductive, it indicates that the erase verify voltage is less than the threshold voltage of the memory cell, i.e., the erase of the memory cell fails.

It is to be understood that, as shown in fig. 14, the above-described erase verification voltage V _vf0 is defined based on the target threshold voltage Vth after erasing. That is, the threshold voltage Vth of a successfully erased memory cell should be less than the erase verification voltage V _vf0, so that, during verification, the threshold voltage Vth is greater than the erase verification voltage V _vf0 as long as the memory cell is still in the P1 state, P2 state, P3 state, and other states that are not successfully erased, thereby rendering the memory cell non-conductive, and the threshold voltage Vth of the memory cell is less than the erase verification voltage V _vf0 only after successful erase. That is, if the erase is successful, the maximum threshold voltage of the memory cell is V1, and the set erase verify voltage V _vf0 should be greater than or equal to V1.

As shown in fig. 15, the embodiment of the present disclosure further provides a memory 100, including:

a peripheral circuit 110 and a memory cell array 120 composed of a plurality of memory blocks;

Wherein the peripheral circuit 110 is at least configured to perform the method of operation of any of the embodiments described above. That is, the operation method provided in any of the above embodiments can be applied to the memory 100.

As shown in fig. 16, the presently disclosed embodiments also provide a memory system 200 comprising:

a memory 210 and a controller 220;

The memory 210 includes at least peripheral circuitry and a memory cell array comprised of a plurality of memory blocks, the peripheral circuitry being configured at least to perform the method of operation as described in any of the embodiments above. The memory 210 may also be the memory 100 shown in fig. 12 in the above embodiment.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method for operating a memory, characterized in that the memory comprises a memory cell array composed of a plurality of memory blocks, each of the memory blocks comprises at least a plurality of memory strings and a plurality of word lines coupled to the memory strings; the method comprises:

Applying an erase voltage to a memory block to be erased during a first period of time;

In a second period after the first period, turning on the top selection tube and the bottom selection tube of each storage string in the storage block to be erased, so that the charges in the channel of each storage string after erasure are released from both ends of the storage string;

An erase verification operation is performed on the memory block.

2. The operating method according to claim 1, characterized in that, in the second time period after the first time period, turning on the top selection tube and the bottom selection tube of each storage string in the storage block to be erased comprises:

Applying a first start-up voltage to a top selection gate line in the storage block; wherein the top selection gate line is connected to a control electrode of the top selection tube;

Applying a second start-up voltage to a bottom selection gate line in the storage block; wherein the bottom selection gate line is connected to a control electrode of the bottom selection tube;

During the second period, a first selection voltage is synchronously applied to a first selection switch connected to the top selection gate line and a second selection switch connected to the bottom selection gate line, so that the first start-up voltage is applied to the top selection tube and the second start-up voltage is applied to the bottom selection tube.

3 . The operating method according to claim 2 , wherein the first turn-on voltage is equal to the second turn-on voltage.

4. The operating method according to claim 2, characterized in that the method further comprises:

In a first time period, a second gate voltage is applied to the first gate switch and the second gate switch; the second gate voltage is less than the first gate voltage.

5. The operating method according to claim 1, characterized in that the method further comprises:

In the second period, a discharge path in the page buffer coupled to the bit line corresponding to the memory string is turned on.

6. The operating method according to claim 5, wherein turning on the discharge path in the page buffer coupled to the bit line corresponding to the memory string comprises:

A third turn-on voltage is applied to a control switch in a discharge path in a page buffer coupled to the bit line.

7. The operating method according to claim 5, characterized in that the method further comprises:

In the second period, a cut-off voltage is applied to a control switch between the bit line and a sensing node in the page buffer to disconnect a precharge path in the page buffer and a path between latches.

8. The operating method according to claim 1, wherein applying an erase voltage to the memory block to be erased during the first period comprises:

In the first time period, a ground voltage is applied to each word line of the memory block to be erased;

At the same time, the erasing voltage is applied to each bit line or source line of the memory block to be erased.

9. The operating method according to claim 8, characterized in that the method further comprises:

In the second period, the erase voltage applied to each of the bit lines or source lines is switched to a ground voltage.

10. The operating method according to any one of claims 1 to 9, characterized in that the performing an erase verification operation on the storage block comprises:

Applying an erase verification voltage to a selected word line on the storage block; wherein the selected word line is any word line on the storage block;

Applying a turn-on voltage to an unselected word line on the memory block; wherein the turn-on voltage is greater than or equal to a maximum threshold voltage of a memory cell; and the erase verification voltage is less than the turn-on voltage;

The storage unit corresponding to the selected word line is read to obtain a verification result of the erase verification operation.

11. A memory, characterized in that the memory comprises:

Peripheral circuits and a memory cell array consisting of a plurality of memory blocks;

Wherein, the peripheral circuit is at least configured to execute the operating method according to any one of claims 1 to 10.

12. A memory system, characterized in that the memory system comprises:

Memory and controller;

The memory comprises at least a peripheral circuit and a memory cell array consisting of a plurality of memory blocks; the peripheral circuit is at least configured to execute the operating method according to any one of claims 1 to 10.