CN115221077A - Data re-reading method, memory storage device and memory control circuit unit - Google Patents

Abstract

The invention provides a data rereading method, a memory storage device and a memory control circuit unit. The method includes: detecting a notification signal from a volatile memory module; instructing the volatile memory module to execute N instruction sequences in a cache in response to the notification signal; and executing the N instruction sequences in the volatile memory module After the instruction sequences, at least one read instruction sequence is sent according to the M physical addresses involved in the N instruction sequences to instruct the volatile memory module to read the first data from the M physical addresses. Therefore, the operational stability and data access performance of the volatile memory module can be improved.

Description

Data re-reading method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a memory management technology, and more particularly, to a data re-reading method, a memory storage device and a memory control circuit unit.

Background

A volatile memory module (volatile memory module) has the characteristics of fast data access and small volume. Therefore, the volatile memory module is suitable for being arranged in various electronic devices to be used as a storage medium of temporary data.

Generally, when an access error occurs in the volatile memory module (e.g., an instruction from the memory controller cannot be recognized), the memory controller instructs the volatile memory module to re-execute a portion of the operation instructions that have been previously executed, so as to attempt to complete the work that cannot be previously completed. However, if the re-executed instruction includes a read instruction, the read data may have mixed old and new data.

Disclosure of Invention

The invention provides a data re-reading method, a memory storage device and a memory control circuit unit, which can improve the operation stability and the data access efficiency of a volatile memory module.

An exemplary embodiment of the present invention provides a data re-reading method for a volatile memory module, the data re-reading method including: detecting a notification signal from the volatile memory module; instructing the volatile memory module to execute the N instruction sequences in the cache in response to the notification signal; and after the volatile memory module executes the N instruction sequences, sending at least one reading instruction sequence according to the M entity addresses related to the N instruction sequences to instruct the volatile memory module to read first data from the M entity addresses.

In an exemplary embodiment of the invention, the data re-reading method further includes: marking second data read from the M physical addresses by execution of the N sequences of instructions in the cache as invalid data and not decoding the second data.

In an exemplary embodiment of the invention, the data re-reading method further includes: in response to the notification signal, ceasing to add any instruction sequences to a buffer circuit, wherein the buffer circuit is to provide instruction sequences to be executed to the volatile memory module; and after the volatile memory module finishes executing the N instruction sequences, instructing the volatile memory module to execute the instruction sequences remained in the buffer circuit.

In an exemplary embodiment of the invention, the notification signal reflects an access error of the volatile memory module.

In an exemplary embodiment of the invention, the cache area is used for storing the instruction sequence which is transmitted to the volatile memory module.

In an exemplary embodiment of the invention, the data re-reading method further includes: before detecting the notification signal from the volatile memory module, feeding at least one sequence of instructions into a buffer circuit; instructing the volatile memory module to execute a sequence of instructions in the buffer circuit; and storing the instruction sequence which is transmitted to the volatile memory module in the buffer circuit in the buffer area.

In an exemplary embodiment of the invention, the step of instructing the volatile memory module to execute the sequence of instructions in the buffer circuit includes: temporarily storing the at least one instruction sequence to at least one instruction register in the buffer circuit via a first multiplexer in the buffer circuit; and outputting one of the at least one instruction sequence via a second multiplexer in the buffer circuit for execution by the volatile memory module.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a volatile memory module, and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The memory control circuit unit is connected to the connection interface unit and the volatile memory module. The memory control circuit unit is used for: detecting a notification signal from the volatile memory module; instructing the volatile memory module to execute the N instruction sequences in the cache in response to the notification signal; and after the volatile memory module executes the N instruction sequences, sending at least one reading instruction sequence according to M physical addresses related to the N instruction sequences to instruct the volatile memory module to read first data from the M physical addresses.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: marking second data read from the M physical addresses by executing the N instruction sequences in the cache as invalid data and not decoding the second data.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: in response to the notification signal, ceasing to add any instruction sequences to a buffer circuit, wherein the buffer circuit is to provide instruction sequences to be executed to the volatile memory module; and after the volatile memory module finishes executing the N instruction sequences, instructing the volatile memory module to execute the instruction sequences remained in the buffer circuit.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: before detecting the notification signal from the volatile memory module, feeding at least one sequence of instructions into a buffer circuit; instructing the volatile memory module to execute a sequence of instructions in the buffer circuit; and storing the instruction sequence which is transmitted to the volatile memory module in the buffer circuit in the buffer area.

In an exemplary embodiment of the present invention, the buffer circuit includes a first multiplexer, a plurality of instruction registers, and a second multiplexer. The plurality of instruction registers are connected to the first multiplexer. The second multiplexer is connected to the plurality of instruction registers. The first multiplexer is used for temporarily storing the at least one instruction sequence to at least one of the plurality of instruction registers. The second multiplexer is used for outputting one of the at least one instruction sequence for the volatile memory module to execute.

An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a volatile memory module. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is to connect to a volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuitry to: detecting a notification signal from the volatile memory module; instructing the volatile memory module to execute the N instruction sequences in the cache in response to the notification signal; and after the volatile memory module executes the N instruction sequences, sending at least one reading instruction sequence according to the M entity addresses related to the N instruction sequences to instruct the volatile memory module to read first data from the M entity addresses.

In an exemplary embodiment of the invention, the memory management circuit is further configured to: marking second data read from the M physical addresses by executing the N instruction sequences in the cache as invalid data and not decoding the second data.

In an exemplary embodiment of the invention, the memory management circuit is further configured to: in response to the notification signal, ceasing to add any instruction sequences to a buffer circuit, wherein the buffer circuit is to provide instruction sequences to be executed to the volatile memory module; and after the volatile memory module finishes executing the N instruction sequences, instructing the volatile memory module to execute the instruction sequences remained in the buffer circuit.

In an exemplary embodiment of the invention, the memory management circuit is further configured to: feeding at least one sequence of instructions to a buffer circuit prior to detecting the notification signal from the volatile memory module; instructing the volatile memory module to execute a sequence of instructions in the buffer circuit; and storing the instruction sequence which is transmitted to the volatile memory module in the buffer circuit in the buffer area.

Based on the above, after detecting the notification signal from the volatile memory module, the volatile memory module may execute the N instruction sequences in the buffer in response to the notification signal. In particular, after the volatile memory module executes the N instruction sequences, at least one read instruction sequence may be sent according to the M physical addresses involved in the N instruction sequences to instruct the volatile memory module to read the first data from the M physical addresses. Therefore, the data read by data rereading (namely the first data) can be ensured to be the newest data, and the mixed occurrence of the new data and the old data can be reduced.

Drawings

FIG. 1 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating data access to a volatile memory module according to an exemplary embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating the generation of notification signals when a data access is performed to a volatile memory module in accordance with an exemplary embodiment of the present invention;

FIG. 4 is a diagram illustrating re-execution of N instruction sequences in a cache according to a notification signal in accordance with an exemplary embodiment of the present invention;

FIG. 5 is a diagram illustrating a re-issue of a fetch instruction sequence after execution of N instruction sequences in a cache, according to an exemplary embodiment of the present invention;

FIG. 6 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention;

FIG. 7 is a diagram illustrating a host system, memory storage devices, and I/O devices according to an example embodiment of the invention;

FIG. 8 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;

FIG. 9 is a schematic diagram of a memory storage device according to an example embodiment of the invention;

fig. 10 is a flowchart illustrating a data re-reading method according to an exemplary embodiment of the present invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to fig. 1, a memory storage device 10 includes a connection interface unit 11, a memory control circuit unit 12, and a volatile memory module 13.

The connection interface unit 11 is used to connect the memory storage device 10 to a host system. The memory storage device 10 can communicate with a host system via a connection interface unit 11. In an exemplary embodiment, the connection interface unit 11 is compatible with the Peripheral Component Interconnect local bus (PCI Express) standard. In an exemplary embodiment, the connection interface unit 11 may also be compliant with Serial Advanced Technology Attachment (SATA) standard, parallel Advanced Technology Attachment (PATA) standard, institute of Electrical and Electronic Engineers (IEEE) 1394 standard, universal Serial Bus (USB) standard, SD interface standard, ultra High Speed-I (UHS-I) interface standard, second generation (Ultra High Speed-II, UHS-II) interface standard, memory Stick (Memory Stick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, flash Memory (UFS) interface standard, cp interface standard, CF interface standard, device Interface (IDE) standard, or other suitable Electronic standard. The connection interface unit 11 may be packaged with the memory control circuit unit 12 in a chip, or the connection interface unit 11 is disposed outside a chip including the memory control circuit unit 12.

The memory control circuit unit 12 is connected to the connection interface unit 11 and the volatile memory module 13. The memory control circuit unit 12 is used for executing a plurality of logic gates or control instructions implemented in hardware or firmware. The memory control circuit unit 12 may be used to control the volatile memory module 13. For example, the memory control circuit unit 12 may include a memory controller to instruct the volatile memory module 13 to perform data writing, reading, and deleting operations. In addition, the memory control circuit Unit 12 may include a Central Processing Unit (CPU) or other Programmable general purpose or special purpose microprocessor, a Digital Signal Processor (DSP), a Programmable controller, an Application Specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), or other similar devices or combinations thereof.

The volatile memory module 13 may be used to store data in a volatile manner. For example, the volatile Memory module 13 may include various Random Access Memories (RAMs). For example, the volatile memory module 13 may include a dual channel synchronous dynamic random access memory (DDR) SDRAM, such as a DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, DDR4SDRAM, DDR5 SDRAM, etc., or other types of nonvolatile memory.

Memory control circuitry unit 12 may include a host interface 121, memory management circuitry 122, a memory interface 123, buffer circuitry 124, buffer memory 125, and decode circuitry 126. The host interface 121 is used to connect the memory control circuit unit 12 to a host system. The memory control circuit unit 12 can communicate with a host system via a host interface 121. For example, the host interface 121 may be compatible with the PCI Express standard, SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transfer standard.

Memory management circuit 122 is connected to host interface 121, memory interface 123, buffer circuit 124, buffer memory 125, and decode circuit 126. The memory management circuit 122 is responsible for the whole or part of the operation of the memory control circuit unit 12. In addition, the memory management circuit 122 may be used to control the volatile memory module 13. For example, according to a read command, a write command or a delete command from the host system, the memory management circuit 122 may send a corresponding command sequence to the volatile memory module 13 to instruct the volatile memory module 13 to perform an operation such as writing, reading or erasing data. In the following exemplary embodiments, the description of the memory management circuit 122 may be identical to the description of the memory control circuit unit 12.

The memory interface 123 is used to access the volatile memory module 13. For example, the memory management circuit 122 may access the volatile memory module 13 through the memory interface 123. For example, the memory management circuit 122 may transmit various instructions to the volatile memory module 13 through the memory interface 123 in the form of instruction sequences to instruct the volatile memory module 13 to perform operations such as writing, reading, and erasing of data. For example, the instruction sequence may include information such as the identification code of the instruction and the physical address (i.e., memory address) to be accessed. In an example embodiment, the instruction sequence is also referred to as an instruction code.

Buffer circuit 124 may be connected between memory management circuit 122 and memory interface 123. Alternatively, the buffer circuit 124 may be disposed in the memory management circuit 122 or the memory interface 123. The buffer circuit 124 is used to temporarily store the instruction sequence issued by the memory management circuit 122 and intended to be transmitted to the volatile memory module 13. For example, when the memory management circuit 122 continuously issues a plurality of instruction sequences, the buffer circuit 124 may receive and temporarily store the instruction sequences, and then transmit the instruction sequences to the volatile memory module 13 one by one for execution by the volatile memory module 13. According to the instruction sequence from the buffer circuit 124, the volatile memory module 13 can perform data access activities such as data writing, data reading and data erasing on specific physical addresses (i.e. memory addresses) in the volatile memory module 13.

Buffer memory 125 may include a buffer 14. The cache 14 may be used to store a plurality of instruction sequences. In particular, the buffer 14 may be dedicated to storing sequences of instructions that have been transferred to the volatile memory module 13 and/or sequences of instructions that have been executed by the volatile memory module 13. In addition, the depth (depth) of the cache 14 may affect the total number of instruction sequences stored in the cache 14.

The decoding circuit 126 is also referred to as an error checking and correcting circuit. The decoding circuit 126 may be used to perform error checking and correction operations to ensure the correctness of the data. For example, when data is read from the volatile memory module 13, the decoding circuit 126 can perform error checking and correcting operations on the read data to correct errors in the data. For example, the decoding circuit 126 may employ various encoding/decoding algorithms such as Low-density parity-check (LDPC) code or BCH code to perform data encoding and decoding, which is not limited by the invention. Since the decoding circuit 126 belongs to a common circuit module in a memory storage device, the operation principle thereof will not be described herein.

In an example embodiment, the memory management circuit 122 may send at least one instruction sequence into the buffer circuit 124. The memory management circuit 122 may instruct the volatile memory module 13 to execute the sequence of instructions in the buffer circuit 124. Meanwhile, the memory management circuit 122 may store the instruction sequence in the buffer circuit 124, which has been transmitted to the volatile memory module 13 or executed by the volatile memory module 13, in the buffer 14. For example, sequences of instructions transferred to volatile memory module 13 via buffer circuit 124 for execution may be copied or backed up in cache memory 14.

In an example embodiment, during the course of the volatile memory module 13 performing the data access according to the instruction sequence from the buffer circuit 124, the volatile memory module 13 may transmit a notification signal to the memory management circuit 122. The notification signal may reflect an access error of the volatile memory module 13. For example, the volatile memory module 13 may send the notification signal to the memory management circuit 122 when the volatile memory module 13 fails to recognize a particular sequence of instructions from the buffer circuit 124 or when the volatile memory module 13 fails to access a particular physical address. In an example embodiment, the notification signal may include an alarm signal to reflect an access error of the volatile memory module 13.

In response to the notification signal, the memory management circuit 122 may instruct the volatile memory module 13 to re-execute the N instruction sequences in the cache region 14. N can be any integer greater than 1. In particular, the value of N may be less than the depth of the cache 14 or the total number of all instruction sequences currently stored in the cache 14.

In an exemplary embodiment, in response to the notification signal, the volatile memory module 13 may automatically perform the data access action that has been previously performed according to the N instruction sequences in the cache region 14. For example, the volatile memory module 13 may read data (also referred to as second data) from M physical addresses in the volatile memory module 13 according to at least one read instruction sequence of the N instruction sequences. M may be any positive integer, and M may be the same or different from N. Alternatively, the volatile memory module 13 may store specific data to a specific physical address in the volatile memory module 13 according to at least one write command sequence of the N command sequences.

After the volatile memory module 13 executes the N instruction sequences (including reading the second data from the M physical addresses) in the cache region 14, the memory management circuit 122 may resend at least one read instruction sequence according to the M physical addresses involved in the N instruction sequences. The read instruction sequence may be used to instruct the volatile memory module 13 to re-read data (also referred to as first data) from the M physical addresses. It should be noted that the first data and the second data are read from the same M physical addresses in the volatile memory module 13, but the data content of the first data may be the same or different from the data content of the second data.

In an example embodiment, the memory management circuit 122 may mark the read second data as invalid data, and the decoding circuit 126 may not decode the second data. For example, second data that is marked as invalid data may be discarded and not analyzed. However, after reading the first data, the decoding circuit 126 may decode the first data to attempt to correct errors in the first data. The decoded first data may then be communicated to a host system or other processing performed.

In an example embodiment, upon detecting the notification signal, memory management circuit 122 may stop (or suspend) adding a new sequence of instructions to buffer circuit 124 in response to the notification signal. At the same time, the memory management circuit 122 may instruct the volatile memory module 13 to execute the instruction sequence still buffered in the buffer circuit 124. After the volatile memory module 13 completes all instruction sequences in the buffer circuit 124, the instruction sequences in the buffer circuit 124 may be cleared, and the memory management circuit 122 may instruct the volatile memory module 13 to execute the N instruction sequences (including reading the second data from the M physical addresses) in the cache region 14.

In an example embodiment, in response to the notification signal, the memory management circuit 122 may stop (or suspend) adding a new instruction sequence to the buffer circuit 124. At the same time, the memory management circuit 122 may instruct the volatile memory module 13 to execute the N instruction sequences (including reading the second data from the M physical addresses) in the cache region 14. After the volatile memory module 13 re-executes the N instruction sequences in the cache memory 14, the memory management circuit 122 may instruct the volatile memory module 13 to execute the instruction sequences still buffered in the buffer circuit 124. After the volatile memory module 13 completes all the instruction sequences in the buffer circuit 124, the instruction sequences in the buffer circuit 124 may be cleared.

In an exemplary embodiment, after the volatile memory module 13 completes all the instruction sequences in the buffer circuit 124 (i.e. the instruction sequences in the buffer circuit 124 are cleared) and the N instruction sequences in the buffer 14 are also re-executed, the memory management circuit 122 may re-send the at least one read instruction sequence according to the M physical addresses involved in the N instruction sequences to instruct the volatile memory module 13 to re-read the first data from the M physical addresses.

FIG. 2 is a diagram illustrating data access to a volatile memory module according to an exemplary embodiment of the present invention. Referring to fig. 2, in an exemplary embodiment, the buffer circuit 124 may include an address mapping and instruction parsing circuit 21, a multiplexer (also referred to as a first multiplexer) 22, instruction registers 23 (1) -23 (P), and a multiplexer (also referred to as a second multiplexer) 24. Multiplexer 22 is connected between the output of address mapping and instruction parsing circuit 21 and the input of instruction registers 23 (1) -23 (P). The multiplexer 24 is connected to the output terminals of the instruction registers 23 (1) to 23 (P).

When the instruction 201 is received, the address mapping and instruction resolution circuit 21 may perform address mapping and instruction resolution on the instruction 201. For example, the address mapping and instruction resolution circuit 21 may perform address mapping on the logical address indicated by the instruction 201 to obtain the physical address mapped by the logical address. For example, the address mapping and instruction parsing circuit 21 may parse the instruction 201 to determine the type of the instruction 201 (e.g., a read instruction or a write instruction). Then, the address mapping and instruction parsing circuit 21 may send the instruction sequence corresponding to the instruction 201 to one of the instruction registers 23 (1) -23 (P) through the multiplexer 22. The multiplexer 24 can sequentially output the instruction sequences in the instruction registers 23 (1) -23 (P) according to a predetermined rule. For example, when the instruction sequence corresponding to the instruction 201 is output in turn, one of the instruction registers 23 (1) -23 (P) may transmit the instruction sequence corresponding to the instruction 201 to the volatile memory module 13 via the multiplexer 24, so that the volatile memory module 13 performs a corresponding access operation.

On the other hand, the instruction sequences transmitted to the volatile memory module 13 via the multiplexer 24 are also backed up in the buffer memory 14 one by one. For example, the instruction sequences 202 (1) -202 (K) currently backed up in the cache 14 may include the instruction sequence corresponding to the instruction 201 newly added to the cache 14. In addition, the instruction sequences 202 (1) -202 (K) may be ordered In the buffer 14 according to a First-In-First-Out (FIFO) mode.

After the volatile memory module 13 receives and executes the instruction sequence corresponding to the instruction 201, assuming that the instruction 201 is a read instruction, the volatile memory module 13 may transmit the data read from the specific physical address in the volatile memory module 13 corresponding to the instruction 201 to the decoding circuit 126 for decoding. Alternatively, if the instruction 201 is a write instruction, the volatile memory module 13 may store the data indicated by the instruction 201 to a specific physical address in the volatile memory module 13.

FIG. 3 is a schematic diagram illustrating the generation of a notification signal when a data access is performed to a volatile memory module according to an exemplary embodiment of the invention. Referring to FIG. 3, during the course of the volatile memory module 13 performing data access according to the instruction sequence from the buffer circuit 124, the volatile memory module 13 may transmit a notification signal 301 to the memory management circuit 122. The notification signal 301 may reflect an access error of the volatile memory module 13. For example, the volatile memory module 13 may generate the notification signal 301 when the volatile memory module 13 fails to recognize a particular sequence of instructions from the buffer circuit 124.

FIG. 4 is a diagram illustrating re-execution of N instruction sequences in a cache according to a notification signal according to an exemplary embodiment of the invention. Referring to fig. 4, following the example embodiment of fig. 3, in response to the notification signal 301, the memory management circuit 122 may define N instruction sequences 301 (1) -301 (N) from the buffer 14 as instruction sequences to be re-executed. For example, instruction sequences 301 (1) -301 (N) may be sequences of instructions in cache 14 that are added to cache 14 relatively late. The volatile memory module 13 may then automatically resume execution of the instruction sequences 301 (1) -301 (N). For example, instruction sequence 301 (i) of instruction sequences 301 (1) -301 (N) may be transferred directly from cache 14 to volatile memory module 13 for execution. After the volatile memory module 13 has re-executed the instruction sequences 301 (1) -301 (N), the buffer 14 may be emptied.

On the other hand, in response to the notification signal 301, the memory management circuit 122 may stop adding a new instruction sequence to the buffer circuit 124. After the buffer 14 is emptied (i.e., after the instruction sequence 301 (1) -301 (N) is re-executed), the memory management circuit 122 may instruct the volatile memory module 13 to execute the remaining instruction sequence stored in the instruction register 23 (1) -23 (P) as soon as possible. After the volatile memory module 13 finishes executing the remaining instruction sequences in the instruction registers 23 (1) to 23 (P), the instruction sequences in the instruction registers 23 (1) to 23 (P) (or the buffer circuit 124) may also be cleared.

In an exemplary embodiment, it is assumed that the instruction sequences 301 (1) -301 (N) include read instruction sequences for M physical addresses in the volatile memory module 13. During the re-execution of the instruction sequences 301 (1) -301 (N), the data (i.e., the second data) read from the M physical addresses are marked as invalid data by the memory management circuit 122, and the M physical addresses can be recorded by the memory management circuit 122. Second data marked as invalid data may be discarded and not analyzed. For example, the decoding circuit 126 may not decode the second data. After the buffer circuit 124 and the buffer 14 are cleared, the memory management circuit 122 may read data (i.e., the first data) from the M physical addresses in the volatile memory module 13 again according to the M physical addresses recorded.

FIG. 5 is a diagram illustrating a reissue of a fetch instruction sequence after execution of N instruction sequences in a cache, according to an illustrative embodiment of the present invention. Referring to fig. 5, continuing with the example embodiment of fig. 4, after the buffer circuit 124 and the buffer 14 are cleared, the memory management circuit 122 may resend at least one read command sequence to the volatile memory module 13 through the buffer circuit 124 according to the M physical addresses involved in the command sequences 301 (1) to 301 (N) to instruct the volatile memory module 13 to read data (i.e., first data) from the M physical addresses again. For example, the memory management circuit 122 may resend the instruction sequence 401 to the volatile memory module 13 via the buffer circuit 124 according to one of the M physical addresses. The sequence of instructions 401 may instruct the volatile memory module 13 to read data from one of the M physical addresses and transmit the read data (i.e., the first data) back to the decoding circuit 126 for decoding, so as to attempt to correct errors in the first data. The decoded first data may then be communicated to a host system or other processing performed.

In an exemplary embodiment, the reading of the first data is performed after the volatile memory module 13 completes all the instruction sequences in the buffer circuit 124 and the N instruction sequences in the buffer 14 are re-executed, compared to the reading of the second data, which may be read to be overwritten later, so as to ensure that the first data read later is the latest data and reduce the occurrence of the mixed new and old data in the read data. On the other hand, by using the first data instead of the second data, the correctness of the data read by performing data re-reading on the volatile memory module 13 after the notification signal is detected can be improved, thereby improving the operation stability of the system.

It should be noted that the structure of the buffer circuit 124 in the exemplary embodiments of fig. 3 to 5 is only an example and is not intended to limit the present invention. In another exemplary embodiment, the internal structure of the buffer circuit 124 can also be adjusted, and the invention is not limited thereto. For example, in an exemplary embodiment, the address mapping and instruction parsing circuit 21 may also be considered as a part of the memory management circuit 122.

In an exemplary embodiment, the memory storage device 10 of FIG. 1 may also include a non-volatile memory module and a controller thereof. The memory storage device 10 may be used with a host system such that the host system may write data to the memory storage device 10 or read data from the memory storage device 10.

FIG. 6 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 7 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 6 and 7, the host system 61 may include a processor 611, a Random Access Memory (RAM) 612, a Read Only Memory (ROM) 613, and a data transmission interface 614. The processor 611, the random access memory 612, the read only memory 613, and the data transmission interface 614 may be connected to a system bus (system bus) 610.

In an example embodiment, host system 61 may be coupled to memory storage device 60 via data transfer interface 614. For example, host system 61 may store data to memory storage device 60 or read data from memory storage device 60 via data transfer interface 614. Further, the host system 61 may be connected to the I/O device 62 through a system bus 610. For example, the host system 61 may transmit output signals to the I/O device 62 or receive input signals from the I/O device 62 via the system bus 610.

In an exemplary embodiment, the processor 611, the ram 612, the rom 613 and the data transmission interface 614 are disposed on the motherboard 70 of the host system 61. The number of data transmission interfaces 614 may be one or more. The motherboard 70 can be connected to the memory storage device 60 via a wired or wireless connection via the data transmission interface 614.

In an example embodiment, the memory storage device 60 may be, for example, a usb disk 701, a memory card 702, a Solid State Drive (SSD) 703 or a wireless memory storage device 704. The wireless memory storage 704 may be, for example, near Field Communication (NFC) memory storage, wireless facsimile (WiFi) memory storage, bluetooth (Bluetooth) memory storage, or low power Bluetooth memory storage (e.g., iBeacon) based memory storage based on various wireless Communication technologies. In addition, the motherboard 70 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 705, a network interface card 706, a wireless transmission device 707, a keyboard 708, a screen 709, and a speaker 710 via a System bus 610. For example, in an exemplary embodiment, the motherboard 70 may access the wireless memory storage device 704 via the wireless transmission device 707.

In an example embodiment, the host system 61 is a computer system. In an example embodiment, host system 61 may be any system that may substantially cooperate with memory storage device 60 to store data. In an example embodiment, the memory storage device 60 and the host system 61 may include the memory storage device 80 and the host system 81 of fig. 8, respectively.

FIG. 8 is a diagram illustrating a host system and a memory storage device according to an example embodiment of the invention.

Referring to FIG. 8, a memory storage device 80 may be used with a host system 81 to store data. For example, the host system 81 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 80 may be a Secure Digital (SD) card 82, a Compact Flash (CF) card 83, or an embedded storage device 84 used by the host system 81. The embedded memory devices 84 include embedded Multi Media Card (eMMC) 841 and/or embedded Multi Chip Package (eMCP) memory devices 842 of various types that directly connect the memory modules to the host system's substrate.

FIG. 9 is a schematic diagram of a memory storage device according to an example embodiment of the invention.

Referring to fig. 9, the memory storage device 60 includes a connection interface unit 91, a memory control circuit unit 92, a rewritable nonvolatile memory module 93, and a nonvolatile memory module 94.

The connection interface unit 91 is used to connect the memory storage device 60 to the host system 61. The memory storage device 60 can communicate with the host system 61 via the connection interface unit 91. For example, the connection interface unit 91 is compatible with the PCI Express standard, SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transfer standard. The connection interface unit 91 may be packaged with the memory control circuit unit 92 in a chip, or the connection interface unit 91 may be disposed outside a chip including the memory control circuit unit 92.

The memory control circuit unit 92 is connected to the connection interface unit 91, the rewritable nonvolatile memory module 93, and the volatile memory module 94. The memory control circuit unit 92 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 93 according to commands of the host system 61. In addition, the memory control circuit unit 92 may include the memory control circuit unit 12 of fig. 1 to control the volatile memory module 94. The details of the related operations are described above, and are not repeated herein.

The rewritable nonvolatile memory module 93 is used for storing data written by the host system 61. The rewritable nonvolatile memory module 93 may include a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a two-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a three-Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a four-Level Cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 93 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. Each memory cell in the rewritable non-volatile memory module 43 has a plurality of memory states as the threshold voltage changes. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 93 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same word line may constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In an exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area stores system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, a physical erase unit is a physical block (block).

Fig. 10 is a flowchart illustrating a data re-reading method according to an exemplary embodiment of the present invention. Referring to fig. 10, in step 1001, a notification signal from a volatile memory module is detected. In step 1002, in response to the notification signal, the volatile memory module is instructed to execute the N instruction sequences in the cache area. After the volatile memory module executes the N instruction sequences, in step 1003, at least one read instruction sequence is sent according to the M physical addresses related to the N instruction sequences, so as to instruct the volatile memory module to read first data from the M physical addresses.

However, the steps in fig. 10 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 10 can be implemented as a plurality of program codes or circuits, which is not limited in this case. In addition, the method of fig. 10 may be used with the above exemplary embodiments, or may be used alone, which is not limited in this disclosure.

In summary, the exemplary embodiments of the present invention can ensure that the data (i.e., the first data) read by the data re-reading is the newest data after receiving the notification signal from the volatile memory module, thereby reducing the occurrence of mixed new and old data and further improving the operation stability of the system.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the spirit of the corresponding technical solutions of the embodiments of the present invention.

Claims (21)

1. A data re-reading method for a volatile memory module, the data re-reading method comprising: detecting a notification signal from the volatile memory module; instructing the volatile memory module to execute the N instruction sequences in the cache in response to the notification signal; and After the volatile memory module executes the N instruction sequences, according to the M physical addresses involved in the N instruction sequences, at least one read instruction sequence is sent to instruct the volatile memory module from The M physical addresses read the first data. 2. The data rereading method according to claim 1, further comprising: Second data read from the M physical addresses by executing the N instruction sequences in the cache area is marked as invalid data, and the second data is not decoded. 3. The data rereading method according to claim 1, further comprising: In response to the notification signal, stop adding any sequence of instructions to a buffer circuit, wherein the buffer circuit is used to provide the sequence of instructions to be executed to the volatile memory module; and After the volatile memory module executes the N instruction sequences, the volatile memory module is instructed to execute the remaining instruction sequences in the buffer circuit. 4. The data rereading method of claim 1, wherein the notification signal reflects that an access error occurs in the volatile memory module. 5. The data rereading method according to claim 1, wherein the buffer area is used to store the instruction sequence that has been transmitted to the volatile memory module. 6. The data rereading method according to claim 1, further comprising: sending at least one sequence of instructions to a buffer circuit before detecting the notification signal from the volatile memory module; instructing the volatile memory module to execute the sequence of instructions in the buffer circuit; and The instruction sequence that has been transmitted to the volatile memory module in the buffer circuit is stored in the buffer area. 7. The data rereading method of claim 6, wherein the step of instructing the volatile memory module to execute the sequence of instructions in the buffer circuit comprises: temporarily storing the at least one instruction sequence in at least one instruction register in the buffer circuit via a first multiplexer in the buffer circuit; and One of the at least one instruction sequence is output via a second multiplexer in the buffer circuit for execution by the volatile memory module. 8. A memory storage device comprising: a connection interface unit for connecting to a host system; volatile memory modules; and a memory control circuit unit connected to the connection interface unit and the volatile memory module, Wherein the memory control circuit unit is used for: detecting a notification signal from the volatile memory module; instructing the volatile memory module to execute the N instruction sequences in the cache in response to the notification signal; and After the volatile memory module executes the N instruction sequences, according to the M physical addresses involved in the N instruction sequences, at least one read instruction sequence is sent to instruct the volatile memory module from The M physical addresses read the first data. 9. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to: Second data read from the M physical addresses by executing the N instruction sequences in the cache area is marked as invalid data, and the second data is not decoded. 10. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to: In response to the notification signal, stop adding any sequence of instructions to a buffer circuit, wherein the buffer circuit is used to provide the sequence of instructions to be executed to the volatile memory module; and After the volatile memory module has executed the N instruction sequences, the volatile memory module is instructed to execute the remaining instruction sequences in the buffer circuit. 11. The memory storage device of claim 8, wherein the notification signal reflects that an access error occurred to the volatile memory module. 12. The memory storage device of claim 8, wherein the cache area is used to store instruction sequences that have been transferred to the volatile memory module. 13. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to: sending at least one sequence of instructions to a buffer circuit before detecting the notification signal from the volatile memory module; instructing the volatile memory module to execute the sequence of instructions in the buffer circuit; and The instruction sequence that has been transmitted to the volatile memory module in the buffer circuit is stored in the buffer area. 14. The memory storage device of claim 13, wherein the buffer circuit comprises: the first multiplexer; a plurality of instruction registers connected to the first multiplexer; and a second multiplexer connected to the plurality of instruction registers, wherein the first multiplexer is used to temporarily store the at least one instruction sequence in at least one of the plurality of instruction registers, and The second multiplexer is used for outputting one of the at least one instruction sequence for execution by the volatile memory module. 15. A memory control circuit unit for controlling a volatile memory module, the memory control circuit unit comprising: a host interface for connecting to a host system; a memory interface for connecting to a volatile memory module; and memory management circuitry connected to the host interface and the memory interface, Wherein the memory management circuit is used to: detecting a notification signal from the volatile memory module; instructing the volatile memory module to execute the N instruction sequences in the cache in response to the notification signal; and After the volatile memory module executes the N instruction sequences, according to the M physical addresses involved in the N instruction sequences, at least one read instruction sequence is sent to instruct the volatile memory module from The M physical addresses read the first data. 16. The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to: Second data read from the M physical addresses by executing the N instruction sequences in the cache area is marked as invalid data, and the second data is not decoded. 17. The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to: In response to the notification signal, stop adding any sequence of instructions to a buffer circuit, wherein the buffer circuit is used to provide the sequence of instructions to be executed to the volatile memory module; and After the volatile memory module has executed the N instruction sequences, the volatile memory module is instructed to execute the remaining instruction sequences in the buffer circuit. 18. The memory control circuit unit of claim 15, wherein the notification signal reflects that an access error occurred to the volatile memory module. 19. The memory control circuit unit of claim 15, wherein the cache area is used to store instruction sequences that have been transferred to the volatile memory module. 20. The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to: sending at least one instruction sequence to a buffer circuit before detecting the notification signal from the volatile memory module; instructing the volatile memory module to execute the sequence of instructions in the buffer circuit; and The instruction sequence that has been transmitted to the volatile memory module in the buffer circuit is stored in the buffer area. 21. The memory control circuit unit of claim 20, wherein the buffer circuit comprises: the first multiplexer; a plurality of instruction registers connected to the first multiplexer; and a second multiplexer connected to the plurality of instruction registers, wherein the first multiplexer is used to temporarily store the at least one instruction sequence in at least one of the plurality of instruction registers, and The second multiplexer is used for outputting one of the at least one instruction sequence for execution by the volatile memory module.

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