CN114613681B - Preparation method of memory based on II-VI semiconductor one-dimensional nanostructure - Google Patents
Preparation method of memory based on II-VI semiconductor one-dimensional nanostructure Download PDFInfo
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Abstract
本发明提供了基于II‑VI族半导体一维纳米结构的存储器的制备方法。该制备方法包括如下步骤：提供一基底；在所述基底上形成基于II‑VI族半导体的一维纳米结构；在所述一维纳米结构的两端形成第一金属电极层和第二金属电极层，以获得存储器坯料；对所述存储器坯料进行电子辐照处理，以获得存储器。本发明的方案获得了具有大存储窗口、高开关比等特性的基于II‑VI族半导体一维纳米结构的存储器，并且该制备方法省去了制备浮栅层、氧化物阻挡层以及隧穿层的工序，且该制备方法工艺简单。
The present invention provides a method for preparing a memory based on a one-dimensional nanostructure of a II-VI semiconductor. The preparation method comprises the following steps: providing a substrate; forming a one-dimensional nanostructure based on a II-VI semiconductor on the substrate; forming a first metal electrode layer and a second metal electrode layer at both ends of the one-dimensional nanostructure to obtain a memory blank; and subjecting the memory blank to electron irradiation treatment to obtain a memory. The scheme of the present invention obtains a memory based on a one-dimensional nanostructure of a II-VI semiconductor having characteristics such as a large storage window and a high switching ratio, and the preparation method omits the steps of preparing a floating gate layer, an oxide barrier layer, and a tunneling layer, and the preparation method has a simple process.
Description
Technical Field
The invention relates to the field of one-dimensional nano-structure memories, in particular to a preparation method of a memory based on II-VI semiconductor one-dimensional nano-structure and a memory prepared by the preparation method.
Background
Semiconductor memory devices are widely used in the fields of personal computers, mass storage servers, medical instruments, portable electronic devices, and the like. Among various memory types, a floating gate type memory based on a field effect transistor has advantages of a large memory window, a fast write/erase speed, stable memory performance, and the like. Furthermore, field effect transistors are also the main electronics unit of the modern silicon electronics industry. Therefore, the floating gate type memory based on the field effect transistor can be perfectly compatible with modern electronic devices, and device integration is facilitated.
The one-dimensional semiconductor nano structure has excellent electronic performance and is an ideal candidate for constructing a floating gate type memory based on a field effect transistor. For example, silicon nanowires, carbon nanotubes, zinc oxide nanowires have all been used to construct floating gate memories. In general, a floating gate type memory based on one-dimensional semiconductor nano-structures is composed of five parts, a semiconductor channel (one-dimensional semiconductor nano-structure), a three-terminal electrode layer, a blocking layer, a floating gate layer (storage medium), and a tunneling layer. The semiconductor channel, the three terminal electrode layers and the blocking layer are components of the field effect transistor, and the floating gate layer and the tunneling layer are used for realizing the storage function. Therefore, the preparation process of the floating gate type memory based on the one-dimensional semiconductor nano structure generally comprises three steps of (1) preparing a field effect crystal, (2) depositing a dielectric material on a semiconductor channel to prepare a tunneling layer, and (3) depositing or internally injecting a storage medium on the upper part of the tunneling layer to prepare a floating gate layer. In order to reduce the cost and improve the reliability of the device, it is necessary to further simplify the manufacturing process and optimize the manufacturing strategy.
Disclosure of Invention
The inventors of the present invention have found that field effect transistors based on group II-VI semiconductor one-dimensional nanostructures exhibit weak memory performance. The surface states introduced by the hollow defects in the one-dimensional nanostructures of group II-VI semiconductors are the main cause of the memory effect. To improve the storage capacity, it is a viable strategy to further introduce a floating gate storage layer and a tunneling layer. However, this strategy clearly adds two manufacturing steps and has limited effectiveness in improving the storage capacity. For memories based on one-dimensional nanostructures of group II-VI semiconductors, no strategies have been reported to simplify the manufacturing process and greatly increase the storage capacity.
An object of the present invention is to provide a method for a memory with large memory window and high switching ratio characteristics based on a group II-VI semiconductor one-dimensional nanostructure.
It is a further object of the invention to further improve the storage window and the high switching ratio characteristics of the memory.
In particular, the invention provides a preparation method of a memory based on II-VI semiconductor one-dimensional nano structure, which comprises the following steps:
providing a substrate;
Forming a one-dimensional nanostructure based on a group II-VI semiconductor on the substrate;
Forming a first metal electrode layer and a second metal electrode layer at two ends of the one-dimensional nano structure to obtain a memory blank;
And carrying out electron irradiation treatment on the memory blank to obtain the memory.
Optionally, the electron irradiation treatment is performed by bombarding the memory blank with a high-energy electron beam generated by an electron gun.
Optionally, the working environment of the electron gun is a vacuum environment, and the pressure is any value in the range of 10 -2-10-6 Pa;
The working voltage of the electron gun is any value in the range of 0.5-30kV, the current of the high-energy electron beam is any value in the range of 50-300pA, and the irradiation time is any value in the range of 1-3600 s.
Alternatively, the group II-VI semiconductor is selected from cadmium selenide, cadmium sulfide, zinc selenide, zinc sulfide, or zinc oxide.
Optionally, the one-dimensional nanostructure is in the form of a combination of one or more of nanowires, nanobelts, nanorods, and nanotubes.
Optionally, the first metal electrode layer and the second metal electrode layer are selected from the same material;
Optionally, the materials of the first metal electrode layer and the second metal electrode layer are both selected from low work function metals;
optionally, the thickness of the first metal electrode layer and the second metal electrode layer is any value in the range of 50-200 nm.
Optionally, the first metal electrode layer and the second metal electrode layer are selected from different materials.
Optionally, the material of the first metal electrode layer is selected from one of low work function metals;
The material of the second metal electrode layer is selected from one of noble metals.
Optionally, the thickness of the first metal electrode layer is any value in the range of 10-30 nm;
the thickness of the second metal electrode layer is any value ranging from 20 nm to 200 nm.
In particular, the invention provides a memory based on II-VI semiconductor one-dimensional nano structure, which is prepared by the preparation method.
According to the scheme of the application, the memory based on the II-VI semiconductor one-dimensional nano structure with the characteristics of large memory window, high on-off ratio and the like is obtained by forming the II-VI semiconductor one-dimensional nano structure on the substrate, forming the first metal electrode layer and the second metal electrode layer at two ends of the one-dimensional nano structure, and treating for a preset time by utilizing electron irradiation. Before the application, the technical personnel in the art do not propose or realize that the characteristics of a storage window, a switching ratio and the like of the II-VI semiconductor one-dimensional nano-structure memory can be greatly improved by utilizing electron irradiation, the preparation method omits the procedures of preparing a floating gate layer, an oxide barrier layer and a tunneling layer, and the preparation method has simple process.
Further, by limiting the parameters of electron irradiation, working conditions of an electron gun, a II-VI semiconductor, a first metal electrode layer, a second metal electrode layer and the like in the range of the application, the storage window, the switching ratio and the like of the II-VI semiconductor one-dimensional nano-structure memory can be further improved, and meanwhile, the reliability of the preparation method is also improved.
The above, as well as additional objectives, advantages, and features of the present invention will become apparent to those skilled in the art from the following detailed description of a specific embodiment of the present invention when read in conjunction with the accompanying drawings.
Drawings
Some specific embodiments of the invention will be described in detail hereinafter by way of example and not by way of limitation with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts or portions. It will be appreciated by those skilled in the art that the drawings are not necessarily drawn to scale. In the accompanying drawings:
FIG. 1 shows a schematic flow chart of a method for fabricating a memory based on II-VI semiconductor one-dimensional nanostructures, in accordance with one embodiment of the invention;
FIG. 2 shows a schematic flow chart of a method for fabricating a memory based on II-VI semiconductor one-dimensional nanostructures in accordance with the first embodiment of the invention;
FIG. 3 shows a scanning electron microscope image of a CdS nanowire-based memory, according to an embodiment of the invention;
FIG. 4 shows an I-V graph of a large window memory according to an embodiment of the invention;
FIG. 5 shows a schematic flow chart of a method for fabricating a memory based on II-VI semiconductor one-dimensional nanostructures in accordance with the second embodiment of the invention;
fig. 6 shows a schematic flow chart of a method for manufacturing a memory based on II-VI semiconductor one-dimensional nanostructures according to embodiment three of the invention.
Detailed Description
Fig. 1 shows a schematic flow chart of a method for manufacturing a memory based on one-dimensional nanostructures of group II-VI semiconductors, according to one embodiment of the invention. As shown, the preparation method comprises:
Step S110, providing a substrate;
step S120, forming a one-dimensional nano structure based on a II-VI semiconductor on a substrate;
Step S130, forming a first metal electrode layer and a second metal electrode layer at two ends of the one-dimensional nano structure to obtain a memory blank;
step S140, performing electron irradiation treatment on the memory blank to obtain a memory.
In step S110, the substrate may be, for example, a silicon oxide substrate, and the silicon oxide substrate serves as a barrier layer.
In step S120, the group II-VI semiconductor one-dimensional nanostructure obtained by the prior art preparation may be transferred onto the substrate. Wherein the group II-VI semiconductor can be cadmium sulfide, cadmium selenide, zinc sulfide, or zinc oxide. The transfer may be performed by various methods, such as a sliding method (contact printing method), a solution dispersing method, or a displacement table.
In step S130, the materials of the first metal electrode layer and the second metal electrode layer may be the same or different.
In one embodiment, when the materials of the first metal electrode layer and the second metal electrode layer are selected to be the same material, the materials are selected to be metals that match the one-dimensional nanostructure energy levels of group II-VI semiconductors. For n-type group II-VI semiconductors, low work function metals such as indium, chromium or titanium are used. For example, indium metal is preferably used for cadmium sulfide and cadmium selenide of n type, chromium metal is preferably used for zinc sulfide and zinc selenide of n type, and titanium metal is preferably used for zinc oxide of n type. The thickness of the metal material may be, for example, 50nm, 80nm, 100nm, 150nm, 180nm or 200nm, or any other value from 50 to 200 nm.
When the materials of the first metal electrode layer and the second metal electrode layer are the same, the preparation method of the first metal electrode layer and the second metal electrode layer comprises the following steps:
1) Defining corresponding electrode patterns at two ends of the II-VI semiconductor one-dimensional nano structure through one-time photoetching;
2) And preparing and obtaining a first metal electrode layer and a second metal electrode layer at electrode patterns at two ends of the II-VI semiconductor one-dimensional nano structure in a physical deposition mode.
When the materials of the first metal electrode layer and the second metal electrode layer are different materials, the material of the first metal electrode layer is selected to be metal matched with the energy level of the II-VI semiconductor one-dimensional nano structure, and the material of the first metal electrode layer is selected to be noble metal with good stability. For example, the material of the first metal electrode layer is selected from low work function metals such as indium, chromium or titanium in ohmic contact with the n-type semiconductor. For example, indium metal is preferably used for cadmium sulfide and cadmium selenide of n type, chromium metal is preferably used for zinc sulfide and zinc selenide of n type, and titanium metal is preferably used for zinc oxide of n type. The material thickness of the first metal electrode layer may be, for example, 10nm, 15nm, 20nm, 25nm, or 30nm, or any other value from 10 to 30 nm. The material of the second metal electrode layer is noble metal such as gold, platinum, etc., and the thickness of the material of the second metal electrode layer can be 20nm, 50nm, 80nm, 100nm, 150nm or 200nm, or any other value of 20-200 nm.
When the materials of the first metal electrode layer and the second metal electrode layer are selected to be different materials, the preparation method of the first metal electrode layer and the second metal electrode layer comprises the following steps:
1') defining corresponding electrode patterns at two ends of the II-VI semiconductor one-dimensional nano structure through one-time photoetching;
2') respectively evaporating the material of the first metal electrode layer and the material of the second metal electrode layer at the electrode patterns at the two ends of the II-VI semiconductor one-dimensional nano structure in a physical deposition mode to respectively obtain the first metal electrode layer and the second metal electrode layer.
The photolithography method in step 1) and step 1') may use a method in the prior art, as long as the corresponding electrode pattern can be prepared. The physical deposition in step 2) and step 2') may be, for example, evaporation. The vapor deposition method may be thin film vapor deposition by thermal evaporation, electron beam evaporation, or magnetron sputtering evaporation.
In step S140, the electron irradiation method may use a method in the related art as long as irradiation of the memory blank with high-energy electrons can be achieved. The operating voltage of the electron gun may be 0.5kV, 1kV, 2kV, 5kV, 10kV, 20kV or 30kV, or any other value from 0.5 to 30 kV. The beam current of the electron gun may be 50pA, 100pA, 200pA, or 300pA, or may be any other value from 50pA to 300 pA. The working environment of the electron gun is vacuum environment, the pressure range is 10 -2Pa、10-3Pa、10- 4Pa、10-5 Pa or 10 -6 Pa, and the working environment can be any other value of 10 -2-10-6 Pa. The electron irradiation preset time is 1s, 5s, 10s, 30s, 60s, 360s, 1200s, 2400s or 3600s, and can be any other value from 1 to 3600 s.
According to the scheme of the application, the memory based on the II-VI semiconductor one-dimensional nano structure with the characteristics of large memory window, high on-off ratio and the like is obtained by forming the II-VI semiconductor one-dimensional nano structure on the substrate, forming the first metal electrode layer and the second metal electrode layer at two ends of the one-dimensional nano structure, and treating for a preset time by utilizing electron irradiation. Before the application, the technical personnel in the art do not propose or realize that the characteristics of a storage window, a switching ratio and the like of the II-VI semiconductor one-dimensional nano-structure memory can be greatly improved by utilizing electron irradiation, the preparation method omits the procedures of preparing a floating gate layer, an oxide barrier layer and a tunneling layer, and the preparation method has simple process.
By limiting the parameters of electron irradiation, working conditions of an electron gun, a II-VI semiconductor, a first metal electrode layer, a second metal electrode layer and the like in the range of the application, the storage window, the switching ratio and the like of the II-VI semiconductor one-dimensional nano-structure memory can be further improved, and meanwhile, the reliability of the preparation method is also improved.
The following description is made with reference to specific embodiments:
Embodiment one:
The preparation method of the memory is shown in fig. 2, and comprises the following steps:
step S111, transferring CdS nanowires onto a silicon oxide substrate by utilizing a sliding method;
step S112, defining electrode patterns at two ends of the nanowire through photoetching, and evaporating 200nm indium electrodes successively to obtain a memory blank;
And S113, bombarding the memory blank under electron irradiation, wherein the acceleration voltage of an electron gun is 20kV, the current of a high-energy electron beam is 200pA, the working environment pressure is 10 -3 Pa, and the irradiation time is 60S. Wherein the irradiation time may be any one of 1 to 3600 s.
FIG. 3 shows a scanning electron microscope image of a CdS nanowire-based memory according to an embodiment of the application. FIG. 4 shows an I-V graph of a large window memory according to an embodiment of the application, wherein the memory is tested in a voltage linear scan mode, the scan range of the gate voltage is-60V to-60V, the scan speed is 1V/step, the source-drain voltage is fixed to 1V, and the I-V graph of the memory is tested after the irradiation time is 0, 30s and 60 s. As can be seen from fig. 4, the storage window of the unirradiated CdS device is less than 10V. After the irradiation treatment, the storage window increases. The memory window increases to 40V and 80V after 30 seconds and 60 seconds of electron irradiation of the device, respectively. After irradiation, the memory switching ratio is slightly reduced, but still as high as 10 5. In the prior art, the way to increase the switching ratio is to introduce a floating gate storage medium into the device. In the preparation process, two procedures of evaporating a floating gate layer and an oxide barrier layer are needed. In addition, the floating gate storage medium is introduced, and the storage window can be increased to 40-60V. In the application, the electron irradiation treatment omits the procedures of evaporating the floating gate layer and the oxide barrier layer, simplifies the preparation process, greatly improves the storage window and improves the storage capacity of the memory.
Embodiment two:
The preparation method of the memory is shown in fig. 5, and comprises the following steps:
Step S211, transferring the zinc oxide nanoribbon onto a silicon oxide substrate by utilizing a sliding method;
Step S212, defining electrode patterns at two ends of the nano-belt through photoetching, and evaporating a 10nm titanium electrode and a 40nm gold electrode in sequence to obtain a memory blank;
And S213, bombarding the memory blank under electron irradiation, wherein the acceleration voltage of an electron gun is 30kV, the beam current is 230pA, the working environment pressure is 10 -3 Pa, and the irradiation time is 360S.
Embodiment III:
the preparation method of the large window memory is shown in fig. 6, and comprises the following steps:
Step S311, transferring the zinc selenide nanoribbon onto a silicon oxide substrate by utilizing a sliding method;
Step S312, defining electrode patterns at two ends of the nano belt through photoetching, and evaporating a 20nm chromium electrode and an 80 nm gold electrode in sequence to obtain a memory blank;
And step 313, bombarding the memory blank under electron irradiation, wherein the acceleration voltage of an electron gun is 10kV, the beam current is 50pA, the working environment pressure is 10 -3 Pa, and the irradiation time is 2400S.
In the above embodiments, not limited to the values defined in embodiments 1 to 3, for example, the group II-VI semiconductor further includes cadmium selenide, zinc sulfide, etc., and the one-dimensional nanostructure may be a nanowire, a nanoribbon, or a nanotube. The method for transferring the one-dimensional nano structure can be a sliding method, a solution dispersion method or a displacement table for transferring. The thickness of the evaporated single-layer electrode and double-layer electrode can be any value in the range of 50-200 nm. The evaporation mode of the electrode material can be thermal evaporation, electron beam evaporation or magnetron sputtering evaporation. The working voltage of the electron gun can be any value in the range of 0.5-30kV, the current of the high-energy electron beam can be any value in the range of 50-300pA, the vacuum pressure can be any value in the range of 10 -2-10-6 Pa, and the preset irradiation time can be any value in the range of 1-3600 s.
By now it should be appreciated by those skilled in the art that while a number of exemplary embodiments of the invention have been shown and described herein in detail, many other variations or modifications of the invention consistent with the principles of the invention may be directly ascertained or inferred from the present disclosure without departing from the spirit and scope of the invention. Accordingly, the scope of the present invention should be understood and deemed to cover all such other variations or modifications.
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| NL7402013A (en) * | 1974-02-14 | 1975-08-18 | Philips Nv | SEMI-CONDUCTOR DEVICE FOR STORING AND NON-DESTRUCTIVE READING OF IMAGE INFORMATION, AND A MEMORY SYSTEM CONTAINING SUCH DEVICE. |
| JP2003218350A (en) * | 2002-01-22 | 2003-07-31 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
| JP6327802B2 (en) * | 2013-06-12 | 2018-05-23 | キヤノン株式会社 | Radiation generating tube, radiation generating apparatus and radiation imaging system using the same |
| CN103337481B (en) * | 2013-07-02 | 2015-11-04 | 合肥工业大学 | Non-volatile memory based on p-type IIB-VIA group semiconductor nanowire Schottky junction and its preparation method |
| CN110828658A (en) * | 2018-08-08 | 2020-02-21 | 北京北方华创微电子装备有限公司 | Preparation method of resistive random access memory device and resistive random access memory device |
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| CN103233204A (en) * | 2008-06-06 | 2013-08-07 | 出光兴产株式会社 | Sputtering target for oxide thin film and manufacturing method thereof |
| CN103500703A (en) * | 2013-10-10 | 2014-01-08 | 中国科学院上海技术物理研究所 | Method for improving conductivity and light current of CdS (cadmium sulfide) and CdSe (cadmium selenide) nanometer material |
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