CN114188331B - Semiconductor device fabrication methods, semiconductor devices and memory - Google Patents

Semiconductor device fabrication methods, semiconductor devices and memory

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Publication number
CN114188331B
CN114188331B CN202111440500.3A CN202111440500A CN114188331B CN 114188331 B CN114188331 B CN 114188331B CN 202111440500 A CN202111440500 A CN 202111440500A CN 114188331 B CN114188331 B CN 114188331B
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Prior art keywords
layer
stack
select gate
semiconductor device
self
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CN202111440500.3A
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CN114188331A (en
Inventor
张坤
高庭庭
夏志良
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202111440500.3A priority Critical patent/CN114188331B/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

本发明公开了一种半导体器件的制作方法、半导体器件及存储器。所述方法包括：提供基底以及位于所述基底上的堆栈层，所述堆栈层包括顶部选择栅极；在所述堆栈层上形成膜层结构，所述膜层结构包括自对准图案；沿所述自对准图案形成顶部选择栅切槽，且所述顶部选择栅切槽贯穿所述顶部选择栅极；在所述顶部选择栅切槽中形成顶部选择栅隔线。本发明能够简化顶部选择栅隔线的制作难度，提高半导体器件的性能。

This invention discloses a method for fabricating a semiconductor device, a semiconductor device, and a memory. The method includes: providing a substrate and a stacked layer on the substrate, the stacked layer including a top select gate; forming a film structure on the stacked layer, the film structure including a self-aligned pattern; forming a top select gate trench along the self-aligned pattern, the top select gate trench penetrating the top select gate; and forming a top select gate isolation line in the top select gate trench. This invention simplifies the fabrication of the top select gate isolation line and improves the performance of the semiconductor device.

Description

Manufacturing method of semiconductor device, semiconductor device and memory
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor device, and a memory.
Background
In the existing semiconductor device, a top selection gate cutting groove (TSG CUT) is etched between two adjacent rows of storage Channel Holes (CH) through a mask layer (mask), but the size of an opening corresponding to the top selection gate cutting groove in the mask layer is smaller, so that the difficulty of Optical Proximity Correction (OPC) is increased, if the cross section of the top selection cutting groove is in a wave shape, the difficulty of optical proximity correction is further increased, and further, the formation of the top selection gate cutting groove meeting the requirement is more difficult. In addition, the mask layer is adopted for etching, so that the Overlay (OVL) of the top selection gate cutting groove between two adjacent rows of storage channel holes is not easy to control, and the gap between the top selection gate cutting groove and the adjacent storage channel holes is easy to be too small, and the performance of the semiconductor device is influenced.
Disclosure of Invention
The invention provides a manufacturing method of a semiconductor device, the semiconductor device and a memory, which can simplify the manufacturing difficulty of a top selection gate isolation line and improve the performance of the semiconductor device.
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a substrate and a stack layer on the substrate, the stack layer including a top select gate;
Forming a film layer structure on the stack layer, wherein the film layer structure comprises a self-aligned pattern;
Forming a top select gate trench along the self-aligned pattern, and the top select gate trench extending through the top select gate;
A top select gate spacer is formed in the top select gate trench.
Further preferably, the width of the top select gate spacer is smaller than a preset width.
Further preferably, the cross section of the top select gate spacer is curved.
Further preferably, the film layer structure further comprises a stop layer;
An upper surface of the stop layer is flush with an upper surface of the self-aligned pattern.
Further preferably, the step of forming a film structure on the stack layer includes:
Forming an initial self-aligned pattern on the stack layer;
forming an initial stop layer on the stack layer and the initial self-aligned pattern;
And grinding the initial stop layer and the initial self-alignment pattern to enable the ground initial stop layer to form the stop layer, and enabling the ground initial self-alignment pattern to form the self-alignment pattern.
Further preferably, the step of forming an initial self-aligned pattern on the stack layer includes:
Forming a dielectric layer on the stack layer;
forming a mask layer on the dielectric layer;
etching the dielectric layer through the mask layer to enable the etched dielectric layer to form the initial self-aligned pattern;
And removing the mask layer.
Further preferably, the step of forming a top select gate trench along the self-aligned pattern comprises:
And etching the film layer structure and the stack layer to remove the self-aligned pattern and the top selection grid corresponding to the self-aligned pattern, thereby obtaining the self-aligned top selection grid cutting groove.
Further preferably, the stack layer comprises a stack structure comprising the top select gate;
And a plurality of rows of storage channel structures penetrating through the stacked structure are formed in the stacked layer, the top selection gate isolation line is positioned between two adjacent rows of storage channel structures, and the distance between the top selection gate isolation line and the two adjacent rows of storage channel structures is equal.
Further preferably, the peripheral side of the storage channel structure further forms a transition layer, and the peripheral side of the transition layer further forms a barrier layer;
the spacing between the top select gate spacer and the adjacent two rows of storage channel structures is greater than the sum of the thicknesses of the transition layer and the barrier layer.
Further preferably, the step of forming a top select gate spacer in the top select gate trench includes:
filling an insulating layer in the top select gate trench;
And removing the film layer structure, part of the stack layer and part of the insulating layer to enable the residual insulating layer in the top selection gate cutting groove to form the top selection gate isolation line.
Further preferably, the memory channel structure comprises a sacrificial layer on top of the memory channel structure;
The step of removing the film structure, part of the stack layer and part of the insulating layer comprises the following steps:
And grinding the film layer structure, the stack layer and the insulating layer to remove the film layer structure, part of the stack layer and part of the insulating layer on one side of the sacrificial layer, which is far away from the substrate, so as to expose the sacrificial layer.
Further preferably, the method further comprises:
and removing the sacrificial layer and forming a plug on the top of the storage channel structure.
Further preferably, the step of removing the sacrificial layer and forming a plug on top of the storage channel structure includes:
Removing the sacrificial layer, and etching the peripheral side of the sacrificial layer to form an opening at the top of the storage channel structure;
the plug is filled in the opening.
Correspondingly, the invention also provides a semiconductor device, which comprises:
A substrate;
a stack structure on the substrate, the stack structure including a top select gate;
and the width of the top selection grid isolation line is smaller than a preset width.
Further preferably, the cross section of the top select gate spacer is curved.
Further preferably, the semiconductor device further comprises a multi-row memory channel structure extending through the stacked structure;
the top select gate spacer is located between two adjacent rows of storage channel structures, and the top select gate spacer is equidistant from the two adjacent rows of storage channel structures.
Further preferably, the peripheral side of the storage channel structure is also provided with a transition layer, and the peripheral side of the transition layer is also provided with a barrier layer;
The distance between the top selection gate isolation line and the adjacent two rows of storage channel structures is larger than the sum of the thicknesses of the transition layer and the barrier layer.
Further preferably, the memory channel structure includes an isolation layer, a channel layer disposed around the isolation layer, a memory medium layer disposed on the channel layer, and a plug disposed on top of the isolation layer;
The plug is connected with the channel layer, and the orthographic projection of the top of the isolation layer on the plug is positioned in the plug.
Correspondingly, the invention also provides a memory, which comprises a memory array structure and a peripheral structure connected with the memory array structure;
The memory array structure comprises the semiconductor device.
The method has the advantages that the film layer structure with the self-aligned pattern is formed on the stack layer, the top selection gate groove is formed in the stack layer along the self-aligned pattern, the top selection gate groove penetrates through the top selection gate in the stack layer, the top selection gate isolation line is formed in the top selection gate groove, a mask layer is not needed to etch the top selection gate groove, the manufacturing difficulty of the top selection gate groove is reduced, the manufacturing difficulty of the top selection gate isolation line is further reduced, the problem of alignment of the top selection gate groove between two adjacent rows of storage channel structures is solved, the distance between the top selection gate isolation line and the adjacent storage channel structures is ensured, and the performance of the semiconductor device is improved.
Drawings
In order to more clearly illustrate the embodiments or the technical solutions in the prior art, the following description will briefly introduce the drawings that are needed in the embodiments or the description of the prior art, it is obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2a is a top view of a stack layer region arrangement in a semiconductor device according to an embodiment of the present invention;
Fig. 2b is a top view of another stack layer region arrangement in a semiconductor device according to an embodiment of the present invention;
fig. 3a to fig. 3i are schematic structural diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a connection between a memory channel structure and a common source structure in a semiconductor device according to an embodiment of the present invention;
Fig. 5 is another schematic diagram illustrating connection between a memory channel structure and a common source structure in a semiconductor device according to an embodiment of the present invention;
Fig. 6 is a schematic diagram of still another connection between a memory channel structure and a common source structure in a semiconductor device according to an embodiment of the present invention;
Fig. 7 is a schematic structural diagram of a memory according to an embodiment of the present invention.
Detailed Description
Specific structural and functional details disclosed herein are merely representative and are for purposes of describing exemplary embodiments of the invention. The invention may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more. In addition, the term "include" and any variations thereof are intended to cover a non-exclusive inclusion.
In the description of the present invention, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected via an intervening medium, or in communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Referring to fig. 1, a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the invention is shown.
As shown in fig. 1, the method for manufacturing a semiconductor device according to the embodiment of the present invention includes steps 101 to 104, which are specifically as follows:
Step 101, providing a substrate and a stack layer on the substrate, wherein the stack layer comprises a top selection gate.
In the embodiment of the invention, the substrate may be a substrate, for example, a silicon substrate, or may be a substrate including other element semiconductors or compound semiconductors. The substrate may also include a plurality of semiconductor layers stacked, and the semiconductor layers may be polysilicon or the like. The substrate may also include other film layers, not specifically limited herein.
The stack layer may include a stack structure and a cover layer on the stack structure. The stacked structure includes a plurality of gate layers and interlayer insulating layers alternately stacked in a longitudinal direction, which is a direction perpendicular to an upper surface of the substrate. The number of stacked layers of the gate layer and the interlayer insulating layer is not limited, for example, 48 layers, 64 layers, 128 layers, and the like. The gate layer includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide, the interlayer insulating layer includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride, and the capping layer includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.
The stack layer may include a Core region SS and a step region Core. As shown in fig. 2a, the step areas SS may be located at opposite sides of the Core, i.e., the number of the step areas SS may be two, and the opposite sides of the Core are connected to one step area SS. As shown in fig. 2b, the Core areas Core may also be located at opposite sides of the step area SS, i.e. the number of Core areas Core may be two, and the opposite sides of the step area SS are connected to one Core area Core. The Core region SS and the step region Core may have other positional relationships, and are not particularly limited herein.
The step region SS of the stack layer is formed with a step structure. A memory channel structure longitudinally penetrating the stack structure is formed in the Core region Core of the stack layer, and a cover layer is positioned on the stack structure and covers the memory channel structure.
As shown in fig. 3a, a substrate 1 and a stack layer 2 on the substrate 1 are provided, the stack layer 2 includes a stack structure 21 on the substrate 1, the stack structure 21 includes a plurality of interlayer insulating layers 211 and gate layers 212 alternately stacked in a longitudinal direction, and at least one gate layer on top of the stack structure 21 may be a top select gate 212a. As shown in fig. 4 to 6, a barrier layer 24 may be further formed between the gate layer 212 and the interlayer insulating layer 211, and a transition layer 25 may be further formed between the barrier layer 24 and the gate layer 212. Wherein barrier layer 24 includes, but is not limited to, aluminum oxide and transition layer 25 includes, but is not limited to, titanium nitride for improving adhesion of gate layer 212.
The Core region Core of the stack layer 2 is formed with a plurality of memory channel structures 3 extending longitudinally through the stack structure 21 and into the substrate 1. The plurality of memory channel structures 3 may be distributed in a plurality of rows, and any two adjacent rows of memory channel structures 3 may be distributed in a staggered manner. The stack layer 2 further comprises a cover layer 22, which cover layer 22 is located on the stack structure 21 and covers the memory channel structure 3.
The memory channel structure 3 includes a channel layer 31 and a memory medium layer 32 disposed around the channel layer 31. The storage medium layer 32 includes a tunnel layer (not shown in the figure) provided around the peripheral side of the channel layer 31, a charge storage layer (not shown in the figure) provided around the peripheral side of the tunnel layer, and a charge blocking layer (not shown in the figure) provided around the peripheral side of the charge storage layer. The channel layer 31 may be polysilicon or the like, the tunnel layer may be oxide such as silicon oxide, silicon nitride, silicon oxynitride or the like, the charge storage layer may be an insulating layer including quantum dots or nanocrystals or a compound containing nitrogen and silicon, and the charge blocking layer may be oxide such as silicon oxide or the like. The memory channel structure 3 further includes an isolation layer 33 surrounded by the channel layer 31, and the isolation layer 33 may be an oxide such as silicon oxide. In some embodiments, the stack structure 21 may include a first sub-stack structure 21a, a second sub-stack structure 21b, and a third sub-stack structure 21c. The second sub-stack 21b is located on the first sub-stack 21a, and the third sub-stack 21c is located on the second sub-stack 21 b. Each of the first, second and third sub-stack structures 21a, 21b and 21c includes a plurality of interlayer insulating layers 211 and gate layers 212 alternately stacked in a longitudinal direction, and at least one gate layer located on top of the third sub-stack structure 21c may be a top select gate 212a.
The memory channel structure 3 includes a first sub memory channel structure 3a, a second sub memory channel structure 3b, and a third sub memory channel structure 3c. The first sub-memory channel structure 3a longitudinally penetrates the first sub-stack structure 21a and extends into the substrate 1, the second sub-memory channel structure 3b longitudinally penetrates the second sub-stack structure 21b, and the channel layer 31 in the second sub-memory channel structure 3b is connected with the channel layer 31 in the first sub-memory channel structure 3a, the third sub-memory channel structure 3c longitudinally penetrates the third sub-stack structure 21c, and the channel layer 31 in the third sub-memory channel structure 3c is connected with the channel layer 31 in the second sub-memory channel structure 3 b.
In addition, the Core region Core of the stack 2 also forms a slit structure 4, the slit structure 4 extending longitudinally through the stack 2 and into the substrate 1. The slit structure 4 may be an insulating material or a semiconductor material such as polysilicon, and the slit structure 4 may be a common source structure when the slit structure 4 is a semiconductor material.
The channel layer 31 in the memory channel structure 3 may be connected to the common source structure in different ways. In the first embodiment, as shown in fig. 4, the substrate 1 includes a common source layer 11, and the common source layer 11 has a common source structure. The common source layer 11 may be an N-type doped or P-type doped polysilicon layer. The stacked structure 21 is located on the common source layer 11, and the channel layer 31 in the memory channel structure 3 longitudinally penetrates the stacked structure 21 and extends into the common source layer 11 to be connected with the common source layer 11. The storage medium layer 32 in the storage channel structure 3 is located on the common source layer 11 and is arranged around the channel layer 31. The slit structure 4 longitudinally penetrates the stacked structure 21 and extends into the common source layer 11, and the slit structure 4 may be an insulating material.
The substrate 1 may further comprise an insulating dielectric layer 12 and conductive contacts 13. The insulating dielectric layer 12 is located on a side of the common source layer 11 facing away from the stacked structure 21, and the conductive contacts 13 penetrate the insulating dielectric layer 12 and extend into the common source layer 11.
In the second embodiment, as shown in fig. 5, the substrate 1 includes a first semiconductor layer 14, a second semiconductor layer 15, and a third semiconductor layer 16. The second semiconductor layer 15 is located on the first semiconductor layer 14, the third semiconductor layer 16 is located on the second semiconductor layer 15, and the stacked structure 21 is located on the third semiconductor layer 16. The first, second and third semiconductor layers 14, 15 and 16 may each be an N-type doped or P-type doped polysilicon layer.
The channel layer 31 in the memory channel structure 3 extends longitudinally through the stack structure 21, the third semiconductor layer 16 and the second semiconductor layer 15 and into the first semiconductor layer 14. The storage medium layer 32 in the storage channel structure 3 is arranged around the channel layer 31, and the second semiconductor layer 15 laterally penetrates the storage medium layer 32 to be connected with the channel layer 31, i.e. the storage medium layer 32 is disconnected at the second semiconductor layer 15 to ensure that the second semiconductor layer 15 can be connected with the channel layer 31. The second semiconductor layer 15 may be an epitaxial layer. The slit structure 4 may include a common source structure 41 and a barrier layer 42. The common source structure 41 longitudinally penetrates the stacked structure 21 and the third semiconductor layer 16 and extends into the second semiconductor layer 15, and the barrier layer 42 is disposed around the common source structure 41. The slit structure 4 may further comprise a transition layer 43, the transition layer 43 being located between the common source structure 41 and the barrier layer 42.
In the third embodiment, as shown in fig. 6, the base 1 includes a substrate 17, and the substrate 17 may be a semiconductor substrate, for example, a silicon substrate, or a substrate including another element semiconductor or a compound semiconductor. The bottom of the channel layer 31 in the memory channel structure 3 may be provided with an epitaxial layer 18 such that the channel layer 31 is connected to the substrate 17 through the epitaxial layer 18. The storage medium layer 32 in the storage channel structure 3 is arranged around the channel layer 31. The slit structure 4 may include a common source structure 41 and a barrier layer 42, the common source structure 41 extending longitudinally through the stacked structure 21 and into the substrate 17, the barrier layer 42 being disposed around the common source structure 41. The slit structure 4 may further comprise a transition layer 43, the transition layer 43 being located between the common source structure 41 and the barrier layer 42. Doped regions 19 are provided in the substrate 17 at the bottom of the slit structures 4 such that the common source structure 41 is connected to the doped regions 19. Doped region 19 may be an N-type doped region or a P-type doped region.
Step 102, forming a film structure on the stack layer, wherein the film structure comprises a self-aligned pattern.
In the embodiment of the invention, the position of the self-aligned pattern can correspond to the position of the top selection gate isolation line required to be formed subsequently, and the cross section of the self-aligned pattern can be completely the same as the cross section of the top selection isolation line required to be formed subsequently. The width of the self-aligned pattern is less than the preset width, which may be the width of the top select gate trench etched using the mask layer in the prior art, i.e., the width of the self-aligned pattern in this embodiment is less than the width of the top select gate trench in the prior art. The film structure further comprises a stop layer, wherein the stop layer and the self-aligned pattern are uniformly arranged on the stack layer, and the upper surface of the stop layer is flush with the upper surface of the self-aligned pattern so as to ensure that the top selection gate notch is etched rapidly according to the self-aligned pattern.
Specifically, the forming a film structure on the stack layer in step 102 includes:
Forming an initial self-aligned pattern on the stack layer;
forming an initial stop layer on the stack layer and the initial self-aligned pattern;
And grinding the initial stop layer and the initial self-alignment pattern to enable the ground initial stop layer to form the stop layer, and enabling the ground initial self-alignment pattern to form the self-alignment pattern.
Wherein, the initial self-aligned pattern can be obtained by etching the dielectric layer. Specifically, the step of forming an initial self-aligned pattern on the stack layer includes:
Forming a dielectric layer on the stack layer;
forming a mask layer on the dielectric layer;
etching the dielectric layer through the mask layer to enable the etched dielectric layer to form the initial self-aligned pattern;
And removing the mask layer.
As shown in fig. 3a, a dielectric layer 5 is formed on the stack layer 2, and the dielectric layer 5 may be an oxide such as silicon oxide. Then, a mask layer 6 is formed on the dielectric layer 5, and the mask layer 6 may be photoresist or the like. Mask layer 6 has openings 61, openings 61 corresponding to other locations in dielectric layer 5, other locations being other than where an initial self-aligned pattern is desired to be formed in dielectric layer 5.
As shown in fig. 3b, the dielectric layer 5 is etched through the opening 61 in the mask layer 6 to remove the film layer corresponding to the opening 61 in the dielectric layer 5, and the remaining dielectric layer 5 forms the initial self-aligned pattern 51. The width of the initial self-aligned pattern 51 is smaller than the preset width, the initial self-aligned pattern 51 corresponds to the gap between two adjacent rows of storage channel structures 3 in the stack layer 2, and the distances between the initial self-aligned pattern 51 and the two adjacent rows of storage channel structures 3 may be equal. When the adjacent two rows of storage channel structures 3 are staggered, the cross-section of the initial self-aligned pattern 51 may be curved, for example, may be wavy.
In this embodiment, the mask layer 6 is used to form the initial self-aligned pattern 51 in the dielectric layer 5, which reduces the cost and reduces the width of the subsequently formed top select gate trench, compared to the prior art in which the mask layer is used to form the top select gate trench in two adjacent rows of storage channel structures, thereby more easily controlling the etching position of the subsequently formed top select gate trench and reducing the overlay deviation of the top select gate trench between the two adjacent rows of storage channel structures.
After the initial self-aligned pattern 51 is formed, the mask layer 6 is removed as shown in fig. 3 c. An initial stop layer 7 is formed on the stack layer 2 and the initial self-aligned pattern 51 as shown in fig. 3 d. The initial stop layer 7 may be polysilicon (poly) or the like, and the material of the initial stop layer 7 is different from that of the initial self-alignment pattern 51. The thickness of the initial stop layer 7 may be smaller than the thickness of the initial self-aligned pattern 51, and the initial stop layer 7 covers the initial self-aligned pattern 51. Therefore, chemical Mechanical Polishing (CMP) may be used to polish the initial stop layer 7 and the initial self-aligned pattern 51 to remove a portion of the initial stop layer 7 covering the initial self-aligned pattern 51 and to remove a portion of the initial self-aligned pattern 51, so that the polished initial stop layer 7 forms the stop layer 71, the stop layer 71 is only located on the stack layer 2, the polished initial self-aligned pattern 51 forms the self-aligned pattern 52, and the upper surface of the self-aligned pattern 52 is level with the upper surface of the stop layer 71, and the self-aligned pattern 52 and the stop layer 71 form the film structure 10, as shown in fig. 3 e. The width of the self-aligned pattern 52 is smaller than the preset width, the self-aligned pattern 52 corresponds to the gap between two adjacent rows of storage channel structures 3 in the stack layer 2, and the spacing between the self-aligned pattern 52 and the two adjacent rows of storage channel structures 3 may be equal. The cross-section of the self-aligned pattern 52 may be curved, for example, may be wavy.
In some embodiments, after forming the initial self-aligned pattern 51, the initial stop layer 7 may be formed directly on the stack layer 2 and the mask layer 6 without removing the mask layer 6. Then, the initial stop layer 7, the mask layer 6 and the initial self-alignment pattern 51 are polished to remove a portion of the initial stop layer 7 covering the initial self-alignment pattern 51 and to remove the mask layer 6 and a portion of the initial self-alignment pattern 51. Similarly, the polished initial stop layer 7 forms a stop layer 71, the polished initial self-aligned pattern 51 forms a self-aligned pattern 52, the upper surface of the self-aligned pattern 52 is flush with the upper surface of the stop layer 71, and the self-aligned pattern 52 and the stop layer 71 form the film structure 10.
Step 103, forming a top select gate trench along the self-aligned pattern, and the top select gate trench extending through the top select gate.
In the embodiment of the present invention, since the film structure 10 has the self-aligned pattern 52, the self-aligned technology (SELF ALIGN) is used to etch the film structure 10 and the stack layer 2, so as to form the top selection gate trench meeting the requirement.
Specifically, the forming of the top select gate trench along the self-aligned pattern in step 103 includes:
And etching the film layer structure and the stack layer to remove the self-aligned pattern and the top selection grid corresponding to the self-aligned pattern, thereby obtaining the self-aligned top selection grid cutting groove.
As shown in fig. 3f, the self-aligned pattern 52 in the film structure 10 is removed using a self-alignment technique, so that only the stop layer 71 remains in the film structure 10. At the same time, the stack layer 2 is etched along the self-aligned pattern 52 in the film structure 10 to remove the top select gate 212a corresponding to the self-aligned pattern 52 in the stack layer 2 and the interlayer insulating layer 211 and the cap layer 22 corresponding to the self-aligned pattern 52 above the top select gate 212a, thereby forming the top select gate trench 23.
Since the self-aligned pattern 52 corresponds to the gap between two adjacent rows of the storage channel structures 3 in the stack layer 2, and the width of the self-aligned pattern 52 is smaller than the preset width, the top select gate trench 23 is located between two adjacent rows of the storage channel structures 3 in the stack layer 2, and the width of the top select gate trench 23 is smaller than the preset width, so that the adjustable range of the top select gate trench 23 between two adjacent rows of the storage channel structures 3 can be increased under the condition that the distance between two adjacent rows of the storage channel structures 3 is unchanged, and the overlay deviation of the top select gate trench 23 between two adjacent rows of the storage channel structures 3 can be reduced. In addition, the spacing between the top selection gate cutting groove 23 and the adjacent two rows of storage channel structures 3 can be equal, so that the problem of alignment of the top selection gate cutting groove 23 between the adjacent two rows of storage channel structures 3 is further solved. The cross-section of the self-aligned pattern 52 may be curved, and the cross-section of the top select gate trench 23 may also be curved, for example, wavy.
Step 104, forming a top select gate spacer in the top select gate trench.
In the embodiment of the present invention, the top select gate spacer may be formed in the top select gate trench 23 by filling the top select gate trench 23 with an insulating material, such as an oxide of silicon oxide or the like. The top select gate spacer is used to divide the Core region Core of the stack layer 2 into a plurality of memory blocks (blocks).
Specifically, the forming a top select gate spacer in the top select gate trench in step 104 includes:
filling an insulating layer in the top select gate trench;
And removing the film layer structure, part of the stack layer and part of the insulating layer to enable the residual insulating layer in the top selection gate cutting groove to form the top selection gate isolation line.
As shown in fig. 3g, an insulating layer 8 is formed over the membrane layer structure 10, and the insulating layer 8 fills the top select gate trench 23. Then, part of the insulating layer 8 on the film structure 10, part of the insulating layer 8 in the top selection gate trench 23, the film structure 10 and part of the stack layer 2 are removed, so that the remaining insulating layer 8 in the top selection gate trench 23 constitutes a top selection gate spacer.
Specifically, the step of removing the film layer structure, part of the stack layer and part of the insulating layer includes:
And grinding the film layer structure, the stack layer and the insulating layer to remove the film layer structure, part of the stack layer and part of the insulating layer on one side of the sacrificial layer, which is far away from the substrate, so as to expose the sacrificial layer.
The memory channel structure 3 further comprises a sacrificial layer 34 on top of the memory channel structure 3, in particular the sacrificial layer 34 is on top of the separation layer 33 of the memory channel structure 3, i.e. the sacrificial layer 34 is also surrounded by the channel layer 31. As shown in fig. 3h, the film structure 10, the stack layer 2 and the insulating layer 8 are polished by chemical mechanical polishing to remove the film structure 10, a portion of the stack layer 2 (i.e. the cap layer 22) and a portion of the insulating layer 8 (including a portion of the insulating layer 8 on the film structure 10 and a portion of the insulating layer 8 in the top select gate trench 23) on the side of the sacrificial layer 34 facing away from the substrate 1, so as to expose the sacrificial layer 34, and the remaining insulating layer 8 in the top select gate trench 23 forms the top select gate spacer 81.
The width of the top select gate trench 23 (i.e., the length of the top select gate trench 23 in the direction a) is less than the preset width such that the width of the top select gate spacer 81 (i.e., the length of the top select gate spacer 81 in the direction a) is less than the preset width. The top select gate slits 23 may be equally spaced from the adjacent two rows of memory channel structures 3 in the direction a such that the top select gate spacer 81 may be equally spaced from the adjacent two rows of memory channel structures 3 in the direction a. In addition, the peripheral side of the storage channel structure 3 can be further provided with a transition layer, the peripheral side of the transition layer can be further provided with a barrier layer, the distance between the top selection gate isolation line 81 and the adjacent storage channel structure 3 is larger than the sum of the thicknesses of the transition layer and the barrier layer, and therefore the formation of the top selection gate isolation line 81 is prevented from damaging the transition layer and the barrier layer, and the performance of the semiconductor device is improved. The cross-section of the top select gate trench 23 is curvilinear such that the cross-section of the top select gate spacer 81 is curvilinear, such as undulating. The curved top select gate spacer 81 can reduce the space between the top select gate spacer 81 and the adjacent memory channel structure 3, and increase the number of memory channel structures 3 in a unit area, thereby improving the memory density.
In addition, the slit structure 4 is polished while the film layer structure 10, the stack layer 2 and the insulating layer 8 are polished so that the upper surfaces of the polished slit structure 4, the stack layer 2 and the top select gate spacer 81 are flush. The slit structure 4 after grinding extends longitudinally through the stack 21 and into the substrate 1.
After exposing the sacrificial layer 34, the method further comprises:
and removing the sacrificial layer and forming a plug on the top of the storage channel structure.
The sacrificial layer 34 on top of the spacer 33 is replaced by a plug in the memory channel structure 3, which is connected to the channel layer 31. The plug may be a semiconductor material such as polysilicon or the like.
Specifically, the step of removing the sacrificial layer and forming a plug on top of the storage channel structure includes:
Removing the sacrificial layer, and etching the peripheral side of the sacrificial layer to form an opening at the top of the storage channel structure;
the plug is filled in the opening.
As shown in fig. 3i, the periphery side of the sacrificial layer 34 is etched, for example, the channel layer 31, the storage medium layer 32 and the stack layer 2 on the periphery side of the sacrificial layer 34 is etched, while the sacrificial layer 34 on the top of the separation layer 33 in the storage channel structure 3 is removed, to form an opening on the top of the storage channel structure 3, the cross-sectional area of which is larger than the cross-sectional area of the sacrificial layer 34, and the depth of which is equal to the thickness of the sacrificial layer 34. Then, the plug 35 is filled in the opening such that the cross-sectional area of the plug 35 is larger than the cross-sectional area of the sacrificial layer 34, so that a connection window (window) of the contact structure to the plug 35 can be enlarged when the contact structure is subsequently formed on the memory channel structure 3.
As can be seen from the foregoing, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, the film structure having the self-aligned pattern is formed on the stack layer, and the top select gate trench is formed in the stack layer along the self-aligned pattern, so that the top select gate trench penetrates through the top select gate in the stack layer, and the top select gate spacer is formed in the top select gate trench, without using a mask layer to etch the top select gate trench, so that the difficulty in manufacturing the top select gate trench is reduced, the difficulty in manufacturing the top select gate spacer is further reduced, the alignment problem of the top select gate trench between two adjacent rows of storage channel structures is solved, the spacing between the top select gate spacer and the adjacent storage channel structures is ensured, and the performance of the semiconductor device is improved.
Correspondingly, the embodiment of the invention also provides a semiconductor device which can be manufactured by adopting the manufacturing method of the semiconductor device.
Referring to fig. 3i, a schematic structural diagram of a semiconductor device according to an embodiment of the present invention is shown.
As shown in fig. 3i, the present embodiment provides a semiconductor device including a substrate 1, a stack structure 21, a plurality of memory channel structures 3, and a top select gate spacer 81.
The substrate 1 may be a substrate, for example, a silicon substrate, or a substrate including another element semiconductor or a compound semiconductor. The substrate 1 may include a plurality of semiconductor layers stacked, and the semiconductor layers may be polysilicon or the like. The substrate 1 may further comprise other film layers, which are not particularly limited herein. The film layer in the substrate 1 can be seen in fig. 4 to 6, and will not be described in detail here.
The stack structure 21 is positioned on the substrate 1, and the stack structure 21 may include a plurality of gate layers 212 and interlayer insulating layers 211 alternately stacked in a longitudinal direction. The number of stacked layers of the gate layer 212 and the interlayer insulating layer 211 is not limited, and is, for example, 48 layers, 64 layers, 128 layers, or the like. At least one gate layer located on top of the stack 21 may be a top select gate 212a.
The stack structure 21 may include a Core region SS and a step region Core. The specific positional relationship between the Core region SS and the step region Core can be seen in fig. 2a and 2b, and will not be described in detail herein. A plurality of memory channel structures 3 extending longitudinally through the stack structure 21 and into the substrate 1 are formed in the Core region Core of the stack structure 21. The plurality of memory channel structures 3 may be distributed in a plurality of rows, and any two adjacent rows of memory channel structures 3 may be distributed in a staggered manner.
The memory channel structure 3 includes an isolation layer 33, a channel layer 31 disposed around the isolation layer 33, and a memory medium layer 32 disposed around the channel layer 31. The storage medium layer 32 includes a tunnel layer (not shown in the figure) provided around the peripheral side of the channel layer 31, a charge storage layer (not shown in the figure) provided around the peripheral side of the tunnel layer, and a charge blocking layer (not shown in the figure) provided around the peripheral side of the charge storage layer. A slit structure 4 is also formed in the Core region Core of the stack 21, the slit structure 4 extending longitudinally through the stack 21 and into the substrate 1. The slit structure 4 may be an insulating material or a semiconductor material such as polysilicon, and the slit structure 4 may be a common source structure when the slit structure 4 is a semiconductor material. The specific connection relationship between the channel layer 31 and the common source structure in the memory channel structure 3 can be seen in fig. 4 to 6, and detailed description thereof is omitted herein.
The memory channel structure 3 further comprises a plug 35 on top of the isolation layer 33, and an orthographic projection of the top of the isolation layer 33 onto the plug 35 is located within the plug 35, the cross-sectional area of the plug 35 being larger than the area of the upper surface of the isolation layer 33. The plug 35 may also be located on top of the channel layer 31 and the storage medium layer 32, and the orthographic projections of the tops of the channel layer 31 and the storage medium layer 32 on top of the plug 35 are also located within the plug 35, i.e. the cross-sectional area of the plug 35 is larger than the sum of the areas of the isolation layer 33, the channel layer 31 and the upper surface of the storage medium layer 32, so that the contact structure to storage channel structure 3 connection window may be increased when subsequently forming a contact structure on the storage channel structure 3.
The top select gate spacer 81 extends longitudinally from the upper surface of the stacked structure 21 and extends through the top select gate 212a. The width of the top select gate spacer 81 is smaller than the preset width, increasing the adjustable range of the top select gate spacer 81 between two adjacent rows of memory channel structures 3. The top select gate spacer 81 is located between two adjacent rows of memory channel structures 3, and the spacing of the top select gate spacer 81 from the two adjacent rows of memory channel structures 3 in the direction a may be equal. The top select gate spacer is used to divide the Core region Core of the stack 21 into a plurality of memory blocks.
Further, the cross section of the top select gate spacer 81 is curved, such as wavy. The curved top select gate spacer 81 can reduce the space between the top select gate spacer 81 and the adjacent memory channel structure 3, and increase the number of memory channel structures 3 in a unit area, thereby improving the memory density.
Further, the peripheral side of the memory channel structure 3 is further provided with a transition layer (not shown in the figure), and the peripheral side of the transition layer is further provided with a barrier layer (not shown in the figure). The spacing between the top select gate spacer 81 and the adjacent two rows of storage channel structures 3 is larger than the sum of the thicknesses of the transition layer and the barrier layer, so that the formation of the top select gate spacer 81 is prevented from damaging the transition layer and the barrier layer, and the performance of the semiconductor device is improved.
Referring to fig. 7, a schematic diagram of a memory according to an embodiment of the present invention is shown.
As shown in fig. 7, the memory includes a memory array structure 100, and a peripheral structure 200 connected to the memory array structure 100. The memory array structure 100 may be a nonvolatile memory array structure, for example, the memory array structure 100 may be a NAND flash memory, a NOR flash memory, or the like. The memory array structure 100 may include the above-described semiconductor devices, which will not be described in detail herein.
The peripheral structure 200 may include devices such as CMOS (complementary metal oxide semiconductor), SRAM (static random access memory), DRAM (dynamic random access memory), FPGA (field programmable gate array), CPU (central processing unit), xpoint chip, and the like.
Specifically, the peripheral structure 200 may be located on the memory array structure 100, and the peripheral structure 200 is connected to the memory array structure 100. Other configurations of the memory array structure 100 and the peripheral structure 200 may be adopted, for example, the peripheral structure 200 is located under the memory array structure 100, i.e. PUC (periphery under core array) configurations, or the peripheral structure 200 is arranged in parallel with the memory array structure 100, i.e. PNC (PERIPHERY NEAR core array) configurations, etc., which are not limited herein.
In summary, although the present invention has been described in terms of the preferred embodiments, the preferred embodiments are not limited to the above embodiments, and various modifications and changes can be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention is defined by the appended claims.

Claims (19)

1. A method of fabricating a semiconductor device, comprising:
providing a substrate and a stack layer on the substrate, the stack layer including a top select gate;
Forming a film layer structure on the stack layer, wherein the film layer structure comprises a self-aligned pattern formed by etching a dielectric layer and a stop layer formed on the stack layer and the self-aligned pattern;
A top select gate spacer is formed in the top select gate trench.
2. The method of manufacturing a semiconductor device according to claim 1, wherein a width of the top select gate spacer is smaller than a predetermined width.
3. The method of manufacturing a semiconductor device according to claim 1, wherein a cross section of the top select gate spacer is curved.
4. The method for manufacturing a semiconductor device according to claim 1, wherein,
An upper surface of the stop layer is flush with an upper surface of the self-aligned pattern.
5. The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming a film structure on the stack layer comprises:
Forming an initial self-aligned pattern on the stack layer;
forming an initial stop layer on the stack layer and the initial self-aligned pattern;
And grinding the initial stop layer and the initial self-alignment pattern to enable the ground initial stop layer to form the stop layer, and enabling the ground initial self-alignment pattern to form the self-alignment pattern.
6. The method of fabricating a semiconductor device according to claim 5, wherein the step of forming an initial self-aligned pattern on the stack layer comprises:
Forming a dielectric layer on the stack layer;
forming a mask layer on the dielectric layer;
etching the dielectric layer through the mask layer to enable the etched dielectric layer to form the initial self-aligned pattern;
And removing the mask layer.
7. The method of fabricating a semiconductor device of claim 1, wherein the step of forming a top select gate trench along the self-aligned pattern comprises:
And etching the film layer structure and the stack layer to remove the self-aligned pattern and the top selection grid corresponding to the self-aligned pattern, thereby obtaining the self-aligned top selection grid cutting groove.
8. The method of manufacturing a semiconductor device according to claim 1, wherein the stack layer includes a stack structure including the top select gate;
And a plurality of rows of storage channel structures penetrating through the stacked structure are formed in the stacked layer, the top selection gate isolation line is positioned between two adjacent rows of storage channel structures, and the distance between the top selection gate isolation line and the two adjacent rows of storage channel structures is equal.
9. The method of manufacturing a semiconductor device according to claim 8, wherein a transition layer is further formed on a peripheral side of the memory channel structure, and a barrier layer is further formed on a peripheral side of the transition layer;
the spacing between the top select gate spacer and the adjacent two rows of storage channel structures is greater than the sum of the thicknesses of the transition layer and the barrier layer.
10. The method of fabricating a semiconductor device of claim 8, wherein the step of forming a top select gate spacer in the top select gate trench comprises:
filling an insulating layer in the top select gate trench;
And removing the film layer structure, part of the stack layer and part of the insulating layer to enable the residual insulating layer in the top selection gate cutting groove to form the top selection gate isolation line.
11. The method of fabricating a semiconductor device of claim 10, wherein the memory channel structure comprises a sacrificial layer on top of the memory channel structure;
The step of removing the film structure, part of the stack layer and part of the insulating layer comprises the following steps:
And grinding the film layer structure, the stack layer and the insulating layer to remove the film layer structure, part of the stack layer and part of the insulating layer on one side of the sacrificial layer, which is far away from the substrate, so as to expose the sacrificial layer.
12. The method of manufacturing a semiconductor device according to claim 11, further comprising:
and removing the sacrificial layer and forming a plug on the top of the storage channel structure.
13. The method of fabricating a semiconductor device of claim 12, wherein the removing the sacrificial layer and forming a plug on top of the memory channel structure comprises:
Removing the sacrificial layer, and etching the peripheral side of the sacrificial layer to form an opening at the top of the storage channel structure;
the plug is filled in the opening.
14. A semiconductor device manufactured by the manufacturing method of the semiconductor device according to any one of claims 1 to 13, comprising:
A substrate;
a stack structure on the substrate, the stack structure including a top select gate;
and the width of the top selection grid isolation line is smaller than a preset width.
15. The semiconductor device of claim 14, wherein a cross-section of the top select gate spacer is curvilinear.
16. The semiconductor device of claim 14, further comprising a multi-row memory channel structure extending through the stacked structure;
the top select gate spacer is located between two adjacent rows of storage channel structures, and the top select gate spacer is equidistant from the two adjacent rows of storage channel structures.
17. The semiconductor device of claim 16, wherein a periphery side of the memory channel structure further has a transition layer, the periphery side of the transition layer further having a barrier layer;
The distance between the top selection gate isolation line and the adjacent two rows of storage channel structures is larger than the sum of the thicknesses of the transition layer and the barrier layer.
18. The semiconductor device of claim 16, wherein the memory channel structure comprises an isolation layer, a channel layer disposed around the isolation layer, a memory medium layer disposed on the channel layer, and a plug on top of the isolation layer;
The plug is connected with the channel layer, and the orthographic projection of the top of the isolation layer on the plug is positioned in the plug.
19. A memory comprising a memory array structure and a peripheral structure coupled to the memory array structure;
The memory array structure comprising a semiconductor device as claimed in any one of claims 14 to 18.
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