CN113741154A - Method for measuring alignment deviation, semiconductor device and method for manufacturing the same - Google Patents

Abstract

Embodiments of the present disclosure disclose a method for measuring alignment deviation, a semiconductor device, and a method for fabricating the same. The measuring method includes: forming a first pattern in an edge region of a substrate with the same size as a first pattern in a core region of the substrate The second pattern; wherein, the first pattern and the second pattern are arranged side by side along a first direction and have a first preset distance, and the first direction is parallel to the substrate; formed in the edge area and the core area of the substrate The third pattern has the same size as a fourth pattern; wherein the third pattern and the fourth pattern are arranged side by side along the first direction and have a second preset distance, and the second pattern and the fourth pattern are staggered along the first direction; The first pattern and the third pattern are correspondingly overlapped along the first direction; the offset distance between the second pattern and the fourth pattern in the first direction is determined; according to the offset distance, the first preset distance and the second preset distance, determine The misalignment of the first pattern and the third pattern.

Description

Method for measuring alignment deviation, semiconductor device and method for manufacturing the same

technical field

Embodiments of the present disclosure relate to the technical field of semiconductors, and in particular, to a method for measuring alignment deviation, a semiconductor device, and a method for fabricating the same.

Background technique

Lithography is an important process in the semiconductor chip manufacturing process, which is used to print the fine patterns on the mask onto the wafer through light exposure. With the rapid development of semiconductor manufacturing technology, the integration of devices is getting higher and higher, and the feature size of semiconductor devices is constantly shrinking, which puts forward higher and higher requirements for the lithography process.

An important link in the lithography process is to perform interlayer alignment, that is, the alignment between the current layer pattern and the previous layer pattern that already exists on the silicon wafer. Usually, the alignment accuracy between the current layer graphics and the previous layer graphics is measured by measuring the alignment deviation (overlay) between the current layer graphics and the previous layer graphics. There are many problems that need to be solved urgently in the measurement of alignment accuracy in the prior art.

SUMMARY OF THE INVENTION

In view of this, embodiments of the present disclosure provide a method for measuring alignment deviation, a semiconductor device, and a method for fabricating the same.

According to a first aspect of the embodiments of the present disclosure, a method for measuring alignment deviation is provided, including:

A second pattern having the same size as the first pattern in the core region of the substrate is formed in the edge region of the substrate; wherein the first pattern and the second pattern are arranged side by side along a first direction and have a first pre- Set a distance, the first direction is parallel to the base;

A fourth pattern having the same size as the third pattern in the core region of the substrate is formed in the edge region; wherein the third pattern and the fourth pattern are arranged side by side along the first direction and having a second preset distance, the second pattern and the fourth pattern are staggered along the first direction; the first pattern and the third pattern are correspondingly overlapped along the first direction;

determining the offset distance between the second pattern and the fourth pattern in the first direction;

According to the offset distance, the first preset distance and the second preset distance, the alignment deviation of the first pattern and the third pattern is determined.

In some embodiments, the determining an offset distance between the second pattern and the fourth pattern in the first direction includes:

Obtain a first image of the second pattern, and determine the centerline of the second pattern according to the grayscale information of the first image; obtain the centerline of the second pattern according to the centerline of the second pattern Position coordinates;

Obtain a second image of the fourth pattern, and determine the centerline of the fourth pattern according to the grayscale information of the second image; obtain the centerline of the fourth pattern according to the centerline of the fourth pattern Position coordinates;

The offset distance is determined according to the position coordinates of the center line of the second pattern and the position coordinates of the center line of the fourth pattern.

In some embodiments, the determining the alignment deviation between the first pattern and the third pattern according to the offset distance, the first preset distance and the second preset distance includes:

acquiring first difference information between the first preset distance and the second preset distance;

Second difference information between the offset distance and the first difference information is determined to obtain the alignment deviation between the first pattern and the third pattern.

In some embodiments, the core region includes a plurality of the first patterns and a plurality of the third patterns arranged side by side along a first direction, and the edge region includes a plurality of the first patterns arranged side by side along the first direction the second pattern and a plurality of the fourth patterns; the second patterns are arranged in a one-to-one correspondence with the first patterns in the preset sub-regions in the core region, and the fourth patterns are arranged with the core The third patterns in the preset sub-regions in the region are set in a one-to-one correspondence; each of the second patterns and the corresponding first pattern has the first preset distance along the first direction, There is the second preset distance along the first direction between each of the fourth patterns and the corresponding third pattern;

The determining the offset distance between the second pattern and the fourth pattern in the first direction includes:

determining first position coordinates of the symmetry axis of the plurality of second patterns in the first direction;

determining second position coordinates of the symmetry axis of the plurality of fourth patterns in the first direction;

An offset distance between the second pattern and the fourth pattern is determined according to the first position coordinate and the second position coordinate.

In some embodiments, the first pattern includes: conductive contact posts in the core region;

the second pattern comprising: support posts in the edge region;

The third pattern includes: conductive first interconnect lines in the core region that are electrically connected to the contact pillars;

The forming of the fourth pattern includes: a second conductive line in the edge region.

According to a second aspect of the embodiments of the present disclosure, a method for fabricating a semiconductor device is provided, including:

patterning the first mask layer covering the core region and the edge region of the substrate to form a first preset pattern in the first mask layer covering the core region, and forming a first preset pattern in the first mask layer covering the edge region A second preset pattern is formed in the first mask layer; wherein, the first preset pattern and the second preset pattern are arranged side by side along a first direction and have a first preset distance, and the first direction parallel to the base;

Based on the first preset pattern and the second preset pattern, correspondingly forming a first pattern in the core region and forming a second pattern in the edge region;

After forming the first pattern and the second pattern, a second mask layer covering the core region and the edge region is patterned to form in the second mask layer covering the core region a third preset pattern, and a fourth preset pattern is formed in the second mask layer covering the edge region; wherein the third preset pattern and the fourth preset pattern are along the first Arranged side by side in one direction and have a second preset distance;

Based on the third preset pattern and the fourth preset pattern, a third pattern is correspondingly formed in the core region, and a fourth pattern is formed in the edge region; wherein the second pattern and the first Four patterns are staggered along the first direction; the first pattern and the third pattern are correspondingly overlapped along the first direction; the second pattern and the fourth pattern are used to determine the first pattern misalignment with the third pattern.

In some embodiments, along the first direction, the patterned second mask layer includes a plurality of the third preset patterns arranged at equal intervals and a plurality of all the predetermined patterns arranged at equal intervals. the fourth preset pattern; wherein, the distance between two adjacent fourth preset patterns is equal to the distance between two adjacent third preset patterns;

Along the first direction, the patterned first mask layer includes a plurality of the first preset patterns arranged at equal intervals and a plurality of the second preset patterns arranged at equal intervals ;in,

The distance between two adjacent second preset patterns is equal to the distance between two adjacent first preset patterns;

or,

The distance between two adjacent second preset patterns is equal to twice the distance between two adjacent first preset patterns.

In some embodiments, along the first direction, the patterned first mask layer includes a plurality of the first preset patterns arranged at equal intervals, and a plurality of first predetermined patterns arranged at equal intervals the second preset pattern; wherein, the distance between two adjacent second preset patterns is equal to the distance between two adjacent first preset patterns;

Along the first direction, the patterned second mask layer includes a plurality of the third preset patterns arranged at equal intervals and a plurality of the fourth predetermined patterns arranged at equal intervals ; wherein, the distance between two adjacent fourth preset patterns is equal to 3 times the distance between two adjacent third preset patterns.

According to a third aspect of the embodiments of the present disclosure, there is provided a semiconductor device, comprising:

A second pattern located in the edge region of the substrate, the first pattern and the second pattern have the same size, and the first pattern and the second pattern are arranged side by side along a first direction and have a first pre Set a distance; wherein, the first direction is parallel to the base;

a third pattern located in the core region, the third pattern penetrates through the dielectric layer covering the substrate; and the third pattern and the first pattern are arranged in a one-to-one correspondence along the first direction;

a fourth pattern located in the edge region, the fourth pattern penetrates the dielectric layer; the third pattern and the fourth pattern have the same size, and the third pattern and the fourth pattern are along the The first direction is arranged side by side and has a second preset distance; the fourth pattern and the second pattern are staggered along the first direction;

Wherein, the second pattern and the fourth pattern are used to determine the alignment deviation between the first pattern and the third pattern.

In some embodiments, along the first direction, the semiconductor device includes:

A plurality of the third patterns arranged at equal intervals and a plurality of the fourth patterns arranged at equal intervals; wherein, along the first direction, the distance between two adjacent fourth patterns is equal to the distance between two adjacent third patterns;

A plurality of the first patterns arranged at equal intervals and a plurality of the second patterns arranged at equal intervals; wherein,

The distance between two adjacent second patterns is equal to the distance between two adjacent first patterns;

or,

The distance between two adjacent second patterns is equal to twice the distance between two adjacent first patterns.

In some embodiments, along the first direction, the semiconductor device includes:

A plurality of the first patterns arranged at equal intervals and a plurality of second patterns arranged at equal intervals; wherein, the distance between two adjacent second patterns is equal to two adjacent first patterns the distance between;

A plurality of the third patterns arranged at equal intervals and a plurality of the fourth patterns arranged at equal intervals; wherein, along the first direction, the distance between two adjacent fourth patterns is equal to 3 times the distance between two adjacent third patterns.

In the embodiment of the present disclosure, a second pattern with the same size as the first pattern in the core region is formed in the edge region, and a fourth pattern with the same size as the third pattern in the core region is formed in the edge region around the core region, and along a direction parallel to the substrate In the first direction, the first pattern and the second pattern have a first preset distance, the third pattern and the fourth pattern have a second preset distance, and the second pattern and the fourth pattern do not overlap. In this way, even if the first pattern and the third pattern overlap so that the alignment deviation between the first pattern and the third pattern cannot be directly measured, since the second pattern does not overlap with the fourth pattern, it is possible to directly measure the alignment deviation between the first pattern and the third pattern. The offset distance between the second pattern and the fourth pattern in the first direction is combined with the first preset distance and the second preset distance to obtain the alignment deviation between the first pattern and the third pattern, which improves the first pattern The measurement accuracy of the misalignment with the third pattern.

Description of drawings

FIG. 1 is a schematic diagram of a method for manufacturing a metal wire according to an exemplary embodiment;

FIG. 2 is a schematic diagram illustrating another method for fabricating metal wires according to an exemplary embodiment;

3 is a flowchart of a method for measuring alignment deviation according to an exemplary embodiment;

4 is a schematic diagram of a method for measuring alignment deviation according to an exemplary embodiment;

5 is a schematic diagram illustrating a method for determining a pattern center line according to an exemplary embodiment;

6a and 6b are schematic diagrams illustrating another method for measuring alignment deviation according to an exemplary embodiment;

FIG. 7 is a flowchart of a method for fabricating a semiconductor device according to an exemplary embodiment;

8a and 8b are schematic diagrams illustrating a method for fabricating a semiconductor device according to an exemplary embodiment;

FIG. 9a and FIG. 9b are schematic diagrams illustrating another method for fabricating a semiconductor device according to an exemplary embodiment;

FIG. 10 is a schematic structural diagram of a semiconductor device according to an exemplary embodiment;

11a, 11b, 12a, and 12b are schematic structural diagrams of another four types of semiconductor devices according to an exemplary embodiment.

Detailed ways

The technical solutions of the present disclosure will be further elaborated below with reference to the accompanying drawings and specific embodiments of the description.

In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence.

In the embodiment of the present disclosure, the term "A and B are in contact" includes the situation that A and B are in direct contact, or the situation that other components are interposed between A and B, and A is indirectly in contact with B.

In embodiments of the present disclosure, the term "layer" refers to a portion of a material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically and/or along inclined surfaces. Also, a layer may include multiple sub-layers.

It is to be understood that the meanings of "on," "on," and "over" in this disclosure should be read in the broadest possible manner, such that "on" means not only It means "on" something "on" without intervening features or layers (ie, directly on something), but also includes the meaning of "on" something "on" with intervening features or layers.

It should be noted that although this specification is described in terms of embodiments, not every embodiment only includes an independent technical solution, and this description in the description is only for the sake of clarity, and those skilled in the art should take the description as a whole , the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Self-aligned double patterning (SADP) technology is one of the most common methods to achieve half-pitch processes below 40 nm using Deep Ultraviolet Lithography (DUV) lithography equipment. As the line width of the device decreases, the lithography process requires higher and higher alignment accuracy. The key to realizing high-precision alignment control is to accurately measure the alignment deviation of the final actual pattern.

The general measurement method of the alignment deviation is characterized by measuring the offset of the alignment mark (overlay mark) formed by exposure together with the current layer pattern, but due to the difference between the alignment mark and the actual pattern in the environment, the line Therefore, it will be affected by the aberration of the lithography equipment, the influence of the etching process, etc., which will eventually lead to the difference between the measured offset of the alignment mark and the offset of the actual pattern, that is, by measuring the alignment mark The offset does not reflect the actual offset of the actual graphics.

For example, in the related art, the alignment marks are usually formed on the scribe line area of the wafer. Due to the small scribe line area, the feature size (line width, line spacing, etc.) of the alignment marks is much smaller than the size of the actual pattern. There is an error in the measurement of the position of the alignment marks, and there is a certain gap between the deviation between the alignment marks and the deviation between the actual graphics.

In the metal processing process, for the metal interconnect structure, the metal wires need to maintain good alignment with the underlying contact holes. There are usually two methods for making metal wires.

Method 1: Referring to FIG. 1, the contact hole 11 is located in the substrate 10, the metal layer 12 is deposited on the substrate 10, and then a patterned photoresist 13 is formed on the metal layer 12, and the photolithography and etching processes are performed. The metal layer 12 is etched to form metal wires 14 above the aligned contact holes 11 , and then the gaps between adjacent metal wires 14 are filled with a dielectric layer 15 .

Method 2: Referring to FIG. 2, the contact hole 21 is located in the substrate 20, a dielectric layer 22 is formed on the substrate 20, and a patterned photoresist 23 is formed on the dielectric layer 22, and the photolithography and etching processes are performed. The dielectric layer 22 is etched to form a groove 24 exposing the contact hole 21, the groove 24 is filled with a metal material to form a metal layer 25, and then the metal layer 25 covering the dielectric layer 22 is removed by chemical mechanical polishing (CMP) and other means, Separate metal wires 26 are formed.

Since there is a large error in characterizing the alignment deviation of the actual pattern by measuring the alignment deviation of the alignment marks, a solution to accurately obtain the alignment deviation of the actual pattern is to directly measure the alignment deviation of the actual pattern without by means of alignment marks. For example, in the above-mentioned method 2, the alignment deviation between the groove 24 and the contact hole 21 may be directly measured after the groove 24 is formed above the contact hole 21 and before the metal layer 25 is formed. It can be understood that since the metal wires 26 are filled in the grooves 24 , the alignment deviation between the grooves 24 and the contact holes 21 can represent the actual alignment deviation between the metal wires 26 and the contact holes 21 .

However, in the above method 1, since the metal wire 14 is formed by etching the metal layer 12, the conductive contact hole 11 is covered by the metal material forming the metal wire 14 during the whole process, so it is impossible to directly measure the contact between the metal wire 14 and the metal wire 14. Misalignment between holes 11.

FIG. 3 shows a method for measuring alignment deviation according to an exemplary embodiment. Referring to FIG. 3 , the method includes the following steps:

S110 : forming a second pattern in the edge region of the substrate with the same size as the first pattern in the core region of the substrate; wherein the first pattern and the second pattern are juxtaposed along the first direction and have a first preset distance , the first direction is parallel to the base;

S120 : forming a fourth pattern in the edge region with the same size as the third pattern in the core region of the substrate; wherein the third pattern and the fourth pattern are arranged side by side along the first direction and have a second preset distance, the third pattern The second pattern and the fourth pattern are staggered along the first direction; the first pattern and the third pattern are correspondingly overlapped along the first direction;

S130: Determine the offset distance between the second pattern and the fourth pattern in the first direction;

S140: Determine the alignment deviation between the first pattern and the third pattern according to the offset distance, the first preset distance, and the second preset distance.

Exemplarily, the core region of the substrate includes a functional region formed with functional circuit structures, the edge region includes a region around the core region where no functional circuit is formed, and the edge region may or may not be adjacent to the core region. It will be appreciated that the edge region does not perform an electrical function.

Exemplarily, the first pattern and the second pattern may include the same patterns located in different regions and arranged in the same direction, and may be formed simultaneously by the same mask.

It should be noted that, when the patterns described in the present disclosure are symmetrical patterns, the distances or spacings between the patterns described in the present disclosure may include the distances between the centers of the patterns or the centerlines. It can be understood that the first pattern and the second pattern may include patterns of the same layer formed simultaneously using one mask, and the third pattern and the fourth pattern may include patterns of another layer formed simultaneously using one mask. The alignment deviation between the first pattern and the third pattern along the first direction can be represented by the alignment deviation between the second pattern and the fourth pattern along the first direction.

Exemplarily, in the edge region of the substrate, the second pattern and the fourth pattern are staggered along the first direction, including: along the direction perpendicular to the substrate, the projections of the second pattern and the fourth pattern on the substrate are completely separated, and there is no overlap part. In this way, the positional deviation between the second pattern and the fourth pattern can be directly measured.

Exemplarily, as shown in FIG. 4 , the first pattern 41 and the second pattern 42 may be formed on the substrate by using the first mask, and then the third pattern 43 and the fourth pattern may be formed on the substrate by using the second mask. pattern 44, and the third pattern 43 and the first pattern 41 are aligned and overlapped along the first direction, through the first preset distance d1 between the _first pattern 41 and the second pattern 42 and the third pattern 43 and the fourth pattern The second preset distance d ₂ between the patterns 44 can obtain the preset distance between the second pattern and the fourth pattern on the substrate, that is, the difference between the first preset distance d ₁ and the second preset distance d ₂ . Since the second pattern 42 and the fourth pattern 44 are staggered along the first direction, the offset distance between the second pattern 42 and the fourth pattern 44 on the substrate can be directly measured. The alignment deviation between the first pattern 41 and the third pattern 43 is obtained by the preset distance and the offset distance between the second pattern 42 and the fourth pattern 44 .

It should be emphasized that, in some embodiments, the edge region of the substrate may further include: a fifth pattern with the same structure as the first pattern, and a sixth pattern with the same structure as the third pattern. Further, the positional relationship between the fifth pattern and the sixth pattern is the same as the positional relationship between the first pattern and the third pattern.

In the embodiment of the present disclosure, by forming a second pattern in the edge region with the same size as the first pattern in the core region, and forming a fourth pattern in the edge region with the same size as the third pattern in the core region, along the first direction parallel to the substrate, The first pattern and the second pattern have a first predetermined distance, the third pattern and the fourth pattern have a second predetermined distance, and the second pattern and the fourth pattern do not overlap. In this way, even if the first pattern and the third pattern overlap so that the alignment deviation between the first pattern and the third pattern cannot be directly measured, since the second pattern does not overlap the fourth pattern, the first pattern can be directly measured. The offset distance between the second pattern and the fourth pattern in the first direction is combined with the first preset distance and the second preset distance to obtain the alignment deviation between the first pattern and the third pattern, which improves the first pattern The measurement accuracy of the misalignment with the third pattern.

In addition, in the embodiment of the present disclosure, by arranging the second pattern and the fourth pattern in the edge area around the core area, compared with forming the second pattern and the fourth pattern in the core area of the substrate or separately disposing other areas, and compared with In order to separately form alignment marks with smaller feature size and larger measurement error in the scribe line area or other areas of the substrate, the present disclosure utilizes the edge area around the core area where no functional circuit is originally formed to set the second pattern and the fourth pattern. Without additionally occupying the substrate area and without affecting the area of the core area, not only the measurement of the alignment deviation of the first pattern and the third pattern is realized, but also the alignment of the first pattern and the third pattern in the core area is reduced. The measurement error of the position deviation improves the accuracy of the position deviation measurement and the utilization rate of the substrate area.

In some embodiments, S130 may include:

acquiring the first image of the second pattern, and determining the centerline of the second pattern according to the grayscale information of the first image; acquiring the position coordinates of the centerline of the second pattern according to the centerline of the second pattern;

acquiring the second image of the fourth pattern, and determining the centerline of the fourth pattern according to the grayscale information of the second image; acquiring the position coordinates of the centerline of the fourth pattern according to the centerline of the fourth pattern;

The offset distance is determined according to the position coordinates of the center line of the second pattern and the position coordinates of the center line of the fourth pattern.

Exemplarily, the detection image of the edge region of the substrate obtained by scanning electron microscope (CD-SEM) for feature size measurement can be used to obtain the first image of the second pattern and the second image of the fourth pattern, and grayscale information can be obtained. analyze. Different material compositions present different grayscale values. Since the second pattern and the fourth pattern are different from the material composition of the substrate, the first image and the second image and the detected image of the substrate material have a clear degree of distinction, which can be easily distinguished. The center lines of the second pattern and the fourth pattern are determined according to the grayscale information in the detected image, and the position coordinates of the center lines of the second pattern and the fourth pattern are obtained.

5 shows a schematic diagram of the first image and the second image, the curve A corresponds to the grayscale signal intensity distribution of the second pattern 42, and the curve B corresponds to the grayscale signal intensity distribution of the fourth pattern 44. signal strength distribution. The peak position in the grayscale signal intensity distribution curve A indicates the centerline position of the second pattern 42 , and the peak position in the grayscale signal intensity distribution curve B indicates the centerline position of the fourth pattern 44 .

5, the second pattern 42 and the fourth pattern 44 are arranged along the x direction parallel to the substrate, the center line L1 of the second pattern 42 is determined according to the position of the wave crest on the curve A, and the first pattern is determined according to the position of the wave crest on the curve B. The center line L3 of the four patterns 44 . Both the center line L1 and the center line L3 are perpendicular to the x direction. The offset distance between the second pattern 42 and the fourth pattern 44 may be determined according to the center line L1 and the center line L3.

It should be noted that, in some embodiments, the grayscale signal detected at the edge of the pattern is the strongest, that is, the peak in the grayscale signal intensity distribution curve appears at the edge of the pattern. The peak of the pattern is fitted to obtain the peak indicating the center position of the pattern. Therefore, the grayscale signal intensity distribution curve A and the grayscale signal intensity distribution curve B shown in FIG. 5 may be grayscale signal intensity distribution curves obtained after graphic processing.

In some embodiments, S140 may include:

acquiring first difference information between the first preset distance and the second preset distance;

The second difference information between the offset distance and the first difference information is determined to obtain the alignment deviation between the first pattern and the third pattern.

Exemplarily, referring to FIG. 4 , the first preset distance between the first pattern 41 and the second pattern 42 is d ₁ , and the second preset distance between the third pattern 43 and the fourth pattern 44 is d ₂ , the first difference information is (d ₁ -d ₂ ), and the first difference information may represent a preset distance between the second pattern 42 and the fourth pattern 44 . Since the second pattern 42 and the fourth pattern 44 do not overlap, the offset distance Δd between the second pattern 42 and the fourth pattern 44 can be directly measured, and the offset distance Δd and the first difference information (d ₁ − The second difference information ΔL of d ₂ ), that is, the second difference information ΔL is equal to the difference between the offset distance Δd and the first difference information (d ₁ -d ₂ ), and the second difference information ΔL is sufficient The misalignment between the first pattern 41 and the third pattern 43 is characterized. It should be noted that the first difference information (d ₁ -d ₂ ), the offset distance Δd, and the second difference information ΔL are all numerical values representing distances, and do not include negative values.

It can be understood that, referring to FIG. 4 , the first pattern 41 and the third pattern 43 are located on the left side of the second pattern 42 and the fourth pattern 44 respectively, when the first preset distance d ₁ is smaller than the second preset distance When it is d ₂ , if the offset distance Δd is greater than the first difference information (d ₁ -d ₂ ), it means that the third pattern 43 is shifted to the right by ΔL relative to the first pattern 41 along the first direction; if the offset distance If Δd is smaller than the first difference information (d ₁ -d ₂ ), it means that the third pattern 43 is shifted to the left by ΔL in the first direction relative to the first pattern 41 . When the first preset distance d ₁ is greater than the second preset distance d ₂ , if the offset distance Δd is greater than the first difference information (d ₁ -d ₂ ), it means that the third pattern 43 is relative to the first pattern 41 is shifted to the left by ΔL along the first direction; if the offset distance Δd is smaller than the first difference information (d ₁ -d ₂ ), it means that the third pattern 43 is shifted to the right along the first direction relative to the first pattern 41 ΔL.

In some embodiments, the core region includes a plurality of first patterns and a plurality of third patterns arranged side by side along the first direction, and the edge region includes a plurality of second patterns and a plurality of fourth patterns arranged side by side along the first direction pattern; the second pattern is set in a one-to-one correspondence with the first pattern in the preset sub-region in the core region, and the fourth pattern is set in a one-to-one correspondence with the third pattern in the preset sub-region in the core region; There is a first preset distance between the corresponding first patterns along the first direction, and each fourth pattern and the corresponding third pattern have a second preset distance along the first direction;

Determine the offset distance between the second pattern and the fourth pattern in the first direction, including:

determining the coordinates of the first positions of the axes of symmetry of the plurality of second patterns in the first direction;

determining second position coordinates of the symmetry axes of the plurality of fourth patterns in the first direction;

According to the first position coordinate and the second position coordinate, the offset distance between the second pattern and the fourth pattern is determined.

When the second pattern is a hole-like structure or a structure obtained from a hole-like structure, due to the uniformity of the actual etching process, the shape of the actually formed second pattern is irregular or the edges are irregular, which is inconvenient to determine a single second pattern. The center of the pattern has a large measurement error. By setting a plurality of second patterns, the center of the whole composed of the plurality of second patterns can be taken, and the coordinates of the center can be used as the first position coordinates, so as to reduce the measurement error and improve the measurement accuracy.

Similarly, by setting a plurality of fourth patterns, the measurement error can also be reduced, and the measurement accuracy can be improved.

When a plurality of first patterns and a plurality of second patterns are included, the plurality of second patterns of the edge region and the plurality of first patterns of the core region may have the same arrangement. For example, the distance between two adjacent first patterns is the same as the distance between two adjacent second patterns.

Alternatively, the first patterns and the second patterns are arranged in different ways but have a set positional relationship. For example, the distance between two adjacent first patterns and the distance between two adjacent second patterns satisfy a certain relationship.

Exemplarily, the third pattern and the fourth pattern are the same pattern located in different regions, have the same arrangement direction as the first pattern and the second pattern, and can be formed simultaneously by the same mask.

When a plurality of third patterns and a plurality of fourth patterns are included, the plurality of fourth patterns in the edge region and the plurality of third patterns in the core region may have the same arrangement, for example, between two adjacent third patterns The spacing is the same as the spacing between two adjacent fourth patterns;

Alternatively, the third patterns and the fourth patterns are arranged in different ways but have a set positional relationship. For example, the distance between two adjacent third patterns and the distance between two adjacent fourth patterns satisfy a certain relationship.

6a, the core region includes a plurality of first patterns and a plurality of third patterns arranged side by side at equal intervals along the x-direction, for example, including four first patterns 41a, 41b, 41c and 41d, and four third patterns 43a, 43b, 43c, and 43d are located in the predetermined sub-region S1 in the core region, and the third patterns 43a, 43b, 43c, 43d and the first patterns 41a, 41b, 41c, 41d overlap in one-to-one correspondence . Second patterns 42a and 42b and fourth patterns 44a and 44b are formed in the edge region. Dummy second patterns 45a and 45b may also be formed in the edge region, which are the same size as the second patterns 42a and 42b. And the distances between the dummy second pattern 45a and the second pattern 42a, between the second pattern 42a and the second pattern 42b, and between the second pattern 42b and the dummy second pattern 45b are equal, and are equal to two adjacent first patterns Spacing between patterns. The fourth patterns 44a and 44b may correspondingly overlap with the dummy second patterns 45a and 45b, respectively.

There is a first preset distance between the second pattern 42a and the first pattern 41b, and between the second pattern 42b and the first pattern 41c; between the fourth pattern 44a and the third pattern 43a, and between the fourth pattern 44b and the third pattern There is a second preset distance between 43d.

Fig. 6b is a partial schematic diagram of the edge region in Fig. 6a. Referring to Fig. 6b, first determine the symmetry axis L12 of the second patterns 42a and 42b according to the centerline L1 of the second pattern 42a and the centerline L2 of the second pattern 42b. Then, according to the center line L3 of the fourth pattern 44a and the center line L4 of the fourth pattern 44b, the symmetry axis L34 of the fourth patterns 44a and 44b is determined. Calculate the difference according to the coordinates of the symmetry axis L12 and the symmetry axis L34 in the x direction to obtain the offset distance ΔL between the second pattern and the fourth pattern along the x direction, at this time the offset distance between the second pattern and the fourth pattern ΔL can directly characterize the alignment deviation between the first pattern and the third pattern.

Alternatively, first calculate the first difference between the coordinates of the center line L1 of the second pattern 42a and the coordinates of the center line L3 of the fourth pattern 44a, and the second difference between the first preset distance and the second preset distance value, the first difference and the second difference are calculated to obtain the first deviation from the fourth pattern 44a and the second pattern 42a. Similarly, by calculating the third difference between the coordinates of the center line L2 of the second pattern 42b and the coordinates of the center line L4 of the fourth pattern 44b, the third difference and the second difference are calculated to obtain the difference between the fourth pattern 44b and the fourth pattern 44b. The second offset between the two patterns 42b. The first deviation and the second deviation are averaged to obtain the deviation between the second pattern and the fourth pattern, that is, the alignment deviation between the first pattern and the third pattern is obtained. It can be understood that by taking the average value of the deviation between two or more sets of second patterns and the fourth pattern, it is beneficial to improve the accuracy of the measured alignment deviation between the first pattern and the third pattern. .

In some embodiments, the first pattern includes: conductive contact posts in the core region;

A second pattern comprising: support posts in the edge region;

The third pattern includes: conductive first interconnect lines in the core area that are electrically connected to the contact pillars;

The fourth pattern includes: conductive second interconnect lines in the edge region.

Exemplarily, the first pattern in the core region of the substrate may be a contact pillar obtained by filling the contact hole with a conductive material, the second pattern in the edge region may be a support pillar formed together with the first pattern, and the contact pillar and the support pillar have same shape and size. The contact pillars in the core region are aligned and overlapped with the first interconnect lines, and the support pillars in the edge regions do not overlap with the second interconnect lines.

It can be understood that the contact post and the support post may have the same structure, but the support post does not perform an electrical function.

FIG. 7 is a flow chart of a method for fabricating a semiconductor device according to an exemplary embodiment. Referring to Figure 7, the method includes the following steps:

S210 : patterning the first mask layer covering the core region and the edge region of the substrate to form a first preset pattern in the first mask layer covering the core region, and forming a first preset pattern in the first mask layer covering the edge region forming a second preset pattern; wherein, the first preset pattern and the second preset pattern are arranged side by side along a first direction and have a first preset distance, and the first direction is parallel to the substrate;

S220: Based on the first preset pattern and the second preset pattern, correspondingly form the first pattern in the core region, and form the second pattern in the edge region;

S230: After forming the first pattern and the second pattern, patterning the second mask layer covering the core area and the edge area to form a third preset pattern in the second mask layer covering the core area, and A fourth preset pattern is formed in the second mask layer covering the edge region; wherein the third preset pattern and the fourth preset pattern are arranged side by side along the first direction and have a second preset distance;

S240: Based on the third preset pattern and the fourth preset pattern, correspondingly form a third pattern in the core region, and form a fourth pattern in the edge region; wherein the second pattern and the fourth pattern are staggered along the first direction; the first The pattern and the third pattern are correspondingly overlapped along the first direction; the second pattern and the fourth pattern are used to determine the alignment deviation between the first pattern and the third pattern.

Exemplarily, the first preset pattern and the second preset pattern have the same shape and size, and the first preset pattern and the second preset pattern may be formed simultaneously. The third preset pattern and the fourth preset pattern have the same shape and size, and the third preset pattern and the fourth preset pattern can be formed simultaneously.

Exemplarily, when the first pattern is a conductive contact post, and when the first pattern is a conductive support post, the first preset pattern and the second preset pattern are respectively formed in the first mask layer and the first pattern. The opening corresponding to the shape of the second pattern forms a corresponding hole structure in the core area and the edge area of the substrate through the opening, and the hole structure is filled with a conductive material to obtain a contact column and a support column, and there is a first pre-preg between the contact column and the support column. Set distance. Similarly, specific structures of the third pattern and the fourth pattern can be formed.

It can be understood that the first preset distance is not equal to the second preset distance, so that when the first pattern and the third pattern overlap in the first direction, the second pattern and the fourth pattern can be staggered, so that the substrate can be directly measured. The offset distance between the second pattern and the fourth pattern is combined with the first preset distance and the second preset distance to obtain the alignment deviation of the first pattern and the third pattern.

In some embodiments, as shown in FIGS. 8 a and 8 b , along the first direction, the patterned second mask layer includes a plurality of third preset patterns 33 arranged at equal intervals and arranged at equal intervals A plurality of fourth preset patterns 34; wherein, the distance between two adjacent fourth preset patterns 34 is equal to the distance between two adjacent third preset patterns 33;

Along the first direction, the patterned first mask layer includes a plurality of first preset patterns 31 arranged at equal intervals and a plurality of second preset patterns 32 arranged at equal intervals; wherein,

The distance between two adjacent second preset patterns 32 is equal to the distance between two adjacent first preset patterns 31;

or,

The distance between two adjacent second preset patterns 32 is equal to twice the distance between two adjacent first preset patterns 31 .

Referring to FIG. 8a, the spacing between two adjacent first preset patterns 31 is equal to the spacing between two adjacent third preset patterns 33, and the spacing between two adjacent second preset patterns 32 equal to the distance between two adjacent fourth preset patterns 34, and the second preset pattern 32 is located at the midpoint of the gap between the fourth preset patterns 34, that is, the second preset pattern 32 is adjacent to it The distance between the two fourth preset patterns 34 is equal.

Referring to FIG. 8 b , the spacing between two adjacent first preset patterns 31 is equal to the spacing between two adjacent third preset patterns 33 , and is equal to the spacing between two adjacent fourth preset patterns 34 Pitch. The spacing between two adjacent second preset patterns 32 is twice the distance between two adjacent first preset patterns 31 , and the second preset pattern 32 is located in the gap between the fourth preset patterns 34 at the midpoint of .

In the related art, usually, contact hole structures with the same spacing and the same size can be formed in the edge region and the core region, and metal wire structures covering the contact holes are correspondingly formed in the edge region and the core region.

In the solution provided by the embodiments of the present disclosure, a mask for forming the first preset pattern is designed by translating the two groups of contact hole structures in the edge region by a half pitch distance relative to the metal wire structure. It should be emphasized that, at this time, the mask layout for forming the metal wire structure remains unchanged.

In some embodiments, the two groups of contact holes can be translated in the same direction along the direction parallel to the x-axis, and the first preset pattern and the second preset pattern are formed when the mask layout for forming the metal wire structure remains unchanged. The relationship between the patterns is shown in Fig. 8a.

In other embodiments, the adjacent two groups of contact holes can be reversely translated along the direction parallel to the x-axis, and when the layout of the mask used for forming the metal wire structure remains unchanged, the first preset pattern and The relationship between the second preset patterns is shown in FIG. 8b.

In some embodiments, referring to FIGS. 9 a and 9 b , along the first direction, the patterned first mask layer includes a plurality of first preset patterns 31 arranged at equal intervals, and rows of equal intervals. A plurality of second preset patterns 32 of the cloth; wherein, the distance between two adjacent second preset patterns 32 is equal to the distance between two adjacent first preset patterns 31;

Along the first direction, the patterned second mask layer includes a plurality of third preset patterns 33 arranged at equal intervals and a plurality of fourth predetermined patterns 34 arranged at equal intervals; The distance between two adjacent fourth preset patterns 34 is equal to three times the distance between two adjacent third preset patterns 33 .

Exemplarily, referring to FIG. 9a, the spacing between two adjacent second preset patterns 32 is equal to the spacing between two adjacent first preset patterns 31, and the spacing between two adjacent fourth preset patterns The spacing between 34 is three times the spacing between two adjacent third preset patterns 33, and the spacing between the fourth preset pattern 34 and its adjacent second preset pattern 32 is equal to the spacing between two adjacent third preset patterns 33. The distance between the two preset patterns 32 .

In some embodiments, the spacing between the fourth preset pattern 34 and the second preset pattern 32 adjacent thereto may also be unequal.

Exemplarily, referring to FIG. 9b, the distance between two adjacent second preset patterns 32 is equal to the distance between two adjacent first preset patterns 31, and the fourth preset pattern 34 is located in the second The midpoint position of the gap between the preset patterns 32 , that is, the distance between the fourth preset pattern 34 and the second preset pattern 32 adjacent to it is equal, and between two adjacent fourth preset patterns 34 The spacing is equal to three times the distance between two adjacent third preset patterns 33 .

In the solution provided by the embodiments of the present disclosure, a mask for forming the second predetermined pattern is designed by the absence of two groups of metal wire structures in the edge region.

In some embodiments, the gap between the first preset pattern and the second preset pattern is formed by the absence of two groups of metal wire structures in the edge region and the mask layout for forming the contact hole structure remains unchanged. The relationship is shown in Figure 9a.

In other embodiments, the first preset pattern and the second preset pattern are formed by the absence of two groups of metal wire structures in the edge region and the two groups of contact holes can be translated in the same direction along the direction parallel to the x-axis. The relationship between them is shown in Fig. 9b.

In some embodiments, the spacing between the fourth preset pattern 34 and the second preset pattern 32 adjacent thereto may also be unequal, or the distance between the fourth preset pattern 34 and the second preset pattern 32 adjacent thereto may also be unequal. The distance between them may not be equal to the distance between the adjacent second preset patterns 32 .

FIG. 10 is a schematic diagram illustrating a semiconductor device 100 according to an exemplary embodiment, and the semiconductor device 100 is fabricated by the method described in any of the foregoing embodiments. 10 is a schematic partial cross-sectional view of the semiconductor device 100 in the xoz plane. Referring to FIG. 10 , the semiconductor device 100 includes:

the first pattern 110 in the core region of the substrate 101;

The second pattern 120 located in the edge region of the substrate 101, the first pattern 110 and the second pattern 120 have the same size, and the first pattern 110 and the second pattern 120 are arranged side by side along the first direction and have a first predetermined distance d ₁ ; Wherein, the first direction is parallel to the substrate 101;

the third pattern 130 located in the core region, the third pattern 130 penetrates through the dielectric layer 102 covering the substrate 101; and the third pattern 130 and the first pattern 110 are arranged in a one-to-one correspondence along the first direction;

The fourth pattern 140 located in the edge region, the fourth pattern 140 penetrates the dielectric layer 102; the third pattern 130 and the fourth pattern 140 have the same size, and the third pattern 130 and the fourth pattern 140 are arranged side by side along the first direction and have the first two preset distances d ₂ ; the fourth pattern 140 and the second pattern 120 are staggered along the first direction;

The second pattern 120 and the fourth pattern 140 are used to determine the alignment deviation between the first pattern 110 and the third pattern 130.

Exemplarily, the core area of the substrate 101 includes a functional area where functional circuit structures are formed, and the edge area around the core area includes an area around the core area where no functional circuit is formed. It will be appreciated that the edge region does not perform an electrical function.

Exemplarily, the first pattern 110 and the second pattern 120 are the same pattern located in different regions of the same layer, and can be formed simultaneously by the same mask, and the third pattern 130 and the fourth pattern 140 are the same pattern located in different regions of the same layer. , can be formed simultaneously through the same mask.

Along the first direction (parallel to the x direction) the second pattern 120 and the fourth pattern 140 do not overlap, the second pattern 120 and the fourth pattern 140 do not play an electrical function, and can be used to determine the distance between the third pattern 130 and the first pattern 110 alignment deviation.

Exemplarily, the third pattern 130 and the fourth pattern 140 can be obtained by first forming a pattern material layer covering the substrate 101, and then patterning the pattern material layer through photolithography and etching processes to obtain the third pattern 130 and the fourth pattern 140. Since the second pattern 120 and the fourth pattern 140 are completely staggered along the first direction, the position information of the second pattern 120 and the fourth pattern 140 can be directly detected.

Therefore, in the process of fabricating the semiconductor device 100 , the offset distance between the second pattern 120 and the fourth pattern 140 can be measured, that is, the actual distance between the actually formed second pattern 120 and the fourth pattern 140 . The difference between the first preset distance d ₁ and the second preset distance d ₂ may represent the preset distance between the second pattern 120 and the fourth pattern 140 , through the actual distance between the second pattern 120 and the fourth pattern 140 The distance and the preset distance can obtain the positional deviation between the second pattern 120 and the fourth pattern 140 along the first direction, and then obtain the alignment deviation of the first pattern 110 and the third pattern 130 .

In some embodiments, even after the thin dielectric layer 102 is formed on the second pattern 120, light can penetrate the dielectric layer 102, and the position of the second pattern 120 can be directly measured.

In the embodiment of the present disclosure, a second pattern with the same size as the first pattern in the core region is arranged in the edge region around the core region, and a fourth pattern with the same size as the third pattern in the core region is arranged in the edge region around the core region, and the third pattern is There is a first preset distance between a pattern and the second pattern, a second preset distance between the third pattern and the fourth pattern, and the second pattern does not overlap the fourth pattern. When the alignment deviation between the first pattern and the third pattern cannot be directly measured, the offset distance between the second pattern and the fourth pattern in the first direction can be directly measured, and the first preset distance and the third pattern can be combined. Two preset distances, the real alignment deviation between the first pattern and the third pattern can be obtained.

In addition, in the embodiment of the present disclosure, by arranging the second pattern and the fourth pattern in the edge area around the core area, compared with forming the second pattern and the fourth pattern in the core area of the substrate or separately disposing other areas, and compared with In order to separately form alignment marks with smaller feature size and larger measurement error in the scribe line area or other areas of the substrate, the present disclosure utilizes the edge area around the core area where no functional circuit is originally formed to set the second pattern and the fourth pattern. Without additionally occupying the substrate area and without affecting the area of the core area, not only the measurement of the alignment deviation of the first pattern and the third pattern is realized, but also the alignment of the first pattern and the third pattern in the core area is reduced. The measurement error of the position deviation improves the accuracy of the position deviation measurement and the utilization rate of the substrate area.

In some embodiments, along the first direction, the semiconductor device 100 includes:

A plurality of third patterns 130 arranged at equal intervals and a plurality of fourth patterns 140 arranged at equal intervals; wherein, along the first direction, the distance between two adjacent fourth patterns 140 is equal to two adjacent fourth patterns 140 . The distance between the three patterns 130;

A plurality of first patterns 110 arranged at equal intervals and a plurality of second patterns 120 arranged at equal intervals; wherein,

The distance between two adjacent second patterns 120 is equal to the distance between two adjacent first patterns 110;

or,

The distance between two adjacent second patterns 120 is equal to twice the distance between two adjacent first patterns 110 .

Exemplarily, as shown in FIG. 11 a , the first patterns 110 and the third patterns 130 in the core region overlap in a one-to-one correspondence. The plurality of third patterns 130 arranged at equal intervals and the plurality of fourth patterns 140 arranged at equal intervals are located in the dielectric layer 102 on the substrate 101, and the distance between two adjacent fourth patterns 140 is equal to two adjacent fourth patterns 140 The distance between the third patterns 130 . The first pattern 110 and the second pattern 120 are located in the substrate 101 , and the distance between two adjacent second patterns 120 is equal to the distance between two adjacent first patterns 110 .

The dotted box in FIG. 11a is a preset sub-region R1 in the core region, the second patterns 120-1, 120-2, 120-3, 120-4 in the edge region are respectively the same as the first pattern in the preset sub-region R1 110-1, 110-2, 110-3, 110-4 have a one-to-one correspondence with a first preset distance, and the fourth patterns 140-1, 140-2, 140-3, 140-4 in the edge area and the preset The third patterns 130-1, 130-2, 130-3, 130-4 in the region R1 have a second predetermined distance in a one-to-one correspondence, and the second patterns 120-1, 120-2, 120-3, 120- 4 and the fourth patterns 140-1, 140-2, 140-3, 140-4 are staggered and not overlapped with each other along the first direction (parallel to the x direction). Preferably, the distance between the fourth pattern 140-1 and the second pattern 120-1 is equal to the distance between the fourth pattern 140-1 and the second pattern 120-2.

11b, a plurality of third patterns 130 arranged at equal intervals and a plurality of fourth patterns 140 arranged at equal intervals are located in the dielectric layer 102 on the substrate 101, and two adjacent fourth patterns 140 The distance between them is equal to the distance between two adjacent third patterns 130 . The first pattern 110 and the second pattern 120 are located in the substrate 101 , and the distance between two adjacent second patterns 120 is equal to twice the distance between two adjacent first patterns 110 .

The dotted box in FIG. 11b is a preset sub-region R2 in the core region, and the second patterns 120-1 and 120-2 in the edge region are respectively the same as the first patterns 110-1 and 110-3 in the preset sub-region R1. There is a first predetermined distance in a one-to-one correspondence, or the second patterns 120-1 and 120-2 in the edge region have a first predetermined distance in a one-to-one correspondence with the first patterns 110-2 and 110-4 in the predetermined sub-region R1, respectively. Set the distance, the fourth patterns 140-1, 140-2, 140-3, 140-4 in the edge area are respectively connected to the third patterns 130-1, 130-2, 130-3, 130- in the preset sub-region R1 4 have a second preset distance in a one-to-one correspondence, and the second patterns 120-1, 120-2 and the fourth patterns 140-1, 140-2, 140-3, 140-4 are along the first direction (parallel to the x direction ) are staggered and do not overlap each other. Preferably, the distance between the second pattern 120-1 and the fourth pattern 140-1 is equal to the distance between the second pattern 120-1 and the fourth pattern 140-2.

In some embodiments, along the first direction, the semiconductor device 100 includes:

A plurality of first patterns 110 arranged at equal intervals and a plurality of second patterns 120 arranged at equal intervals; wherein, the distance between two adjacent second patterns 120 is equal to the distance between two adjacent first patterns 110 the distance;

A plurality of third patterns 130 arranged at equal intervals and a plurality of fourth patterns 140 arranged at equal intervals; wherein,

Along the first direction, the distance between two adjacent fourth patterns 140 is equal to three times the distance between two adjacent third patterns 130.

Exemplarily, as shown in FIG. 12 a , the first patterns 110 and the third patterns 130 in the core area overlap in a one-to-one correspondence, and the distance between two adjacent second patterns 120 is equal to the distance between two adjacent first patterns 110 The distance between two adjacent fourth patterns 140 is equal to three times the distance between two adjacent third patterns 130 . The second patterns 120-1 and 120-2 in the edge region respectively correspond to the first patterns 110-2 and 110-3 in the predetermined sub-region R3 of the core region and have a first predetermined distance, or the second patterns 120- 1 and 120-2 respectively correspond to the first patterns 110-1 and 110-2 in the preset sub-region R3 and have a first preset distance, or the second patterns 120-1 and 120-2 respectively correspond to the preset sub-regions R3. The first patterns 110 - 3 and 110 - 4 in the region R3 have a first predetermined distance in a one-to-one correspondence. The fourth patterns 140-1 and 140-2 in the edge region have a second predetermined distance in one-to-one correspondence with the third patterns 130-1 and 130-4 in the predetermined sub-region R3, respectively. Preferably, the distance between the fourth pattern 140-1 and the second pattern 120-1 is equal to the distance between the second pattern 120-1 and the second pattern 120-2.

Exemplarily, as shown in FIG. 12 b , the first patterns 110 and the third patterns 130 in the core region overlap in a one-to-one correspondence, and the distance between two adjacent second patterns 120 is equal to the distance between two adjacent first patterns 110 The distance between two adjacent fourth patterns 140 is equal to three times the distance between two adjacent third patterns 130 . The second patterns 120-1, 120-2, 120-3, 120-4 in the edge region are respectively the first patterns 110-1, 110-2, 110-3, 110-4 in the predetermined sub-region R4 of the core region There is a first preset distance in a one-to-one correspondence, and the fourth patterns 140-1, 140-2 in the edge region have a second preset in a one-to-one correspondence with the third patterns 130-1, 130-4 in the preset sub-region R3, respectively distance. Preferably, the distance between the fourth pattern 140-1 and the second pattern 120-1 is equal to the distance between the fourth pattern 140-1 and the second pattern 120-2.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited to this. should be included within the scope of protection of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims (11)

1. A method for measuring alignment deviation, comprising:

forming a second pattern having the same size as the first pattern in the core region of the substrate in the edge region of the substrate; the first pattern and the second pattern are arranged in parallel along a first direction and have a first preset distance, and the first direction is parallel to the substrate;

forming a fourth pattern in the edge region having the same size as the third pattern in the core region of the substrate; the third pattern and the fourth pattern are arranged in parallel along the first direction and have a second preset distance, and the second pattern and the fourth pattern are staggered along the first direction; the first pattern and the third pattern are correspondingly overlapped along the first direction;

determining an offset distance of the second pattern from the fourth pattern in the first direction;

and determining the alignment deviation of the first pattern and the third pattern according to the offset distance, the first preset distance and the second preset distance.

2. The method of claim 1, wherein determining the offset distance of the second pattern from the fourth pattern in the first direction comprises:

acquiring a first image of the second pattern, and determining a central line of the second pattern according to gray information of the first image; acquiring the position coordinate of the central line of the second pattern according to the central line of the second pattern;

acquiring a second image of the fourth pattern, and determining a central line of the fourth pattern according to gray information of the second image; acquiring the position coordinate of the center line of the fourth pattern according to the center line of the fourth pattern;

and determining the offset distance according to the position coordinates of the central line of the second pattern and the position coordinates of the central line of the fourth pattern.

3. The method of claim 1, wherein determining the alignment deviation of the first pattern from the third pattern according to the offset distance, the first predetermined distance, and the second predetermined distance comprises:

acquiring first difference information of the first preset distance and the second preset distance;

and determining second difference information of the offset distance and the first difference information to obtain the alignment deviation of the first pattern and the third pattern.

4. The method of claim 1,

the core region comprises a plurality of first patterns and a plurality of third patterns which are arranged in parallel along a first direction, and the edge region comprises a plurality of second patterns and a plurality of fourth patterns which are arranged in parallel along the first direction; the second patterns are arranged in a one-to-one correspondence with the first patterns in preset sub-areas in the core area, and the fourth patterns are arranged in a one-to-one correspondence with the third patterns in the preset sub-areas in the core area; the first preset distance is arranged between each second pattern and the corresponding first pattern along the first direction, and the second preset distance is arranged between each fourth pattern and the corresponding third pattern along the first direction;

the determining an offset distance of the second pattern from the fourth pattern in the first direction comprises:

determining a first position coordinate of an axis of symmetry of the plurality of the second patterns in the first direction;

determining a second position coordinate of an axis of symmetry of the plurality of the fourth patterns in the first direction;

determining an offset distance of the second pattern from the fourth pattern according to the first position coordinate and the second position coordinate.

5. The method of claim 1,

the first pattern includes: a conductive contact post in the core region;

the second pattern, comprising: support posts in the edge region;

the third pattern, comprising: a conductive first interconnect in the core region electrically connected to the contact stud;

the fourth pattern, comprising: and the second interconnection line is conductive in the edge area.

6. A method of manufacturing a semiconductor device, comprising:

patterning a first mask layer covering a core region and an edge region of a substrate to form a first preset pattern in the first mask layer covering the core region and a second preset pattern in the first mask layer covering the edge region; the first preset pattern and the second preset pattern are arranged in parallel along a first direction and have a first preset distance, and the first direction is parallel to the substrate;

forming a first pattern in the core region correspondingly based on the first preset pattern and the second preset pattern, and forming a second pattern in the edge region;

after the first pattern and the second pattern are formed, patterning a second mask layer covering the core region and the edge region to form a third preset pattern in the second mask layer covering the core region, and forming a fourth preset pattern in the second mask layer covering the edge region; the third preset pattern and the fourth preset pattern are arranged in parallel along the first direction and have a second preset distance;

forming a third pattern in the core region correspondingly based on the third preset pattern and the fourth preset pattern, and forming a fourth pattern in the edge region; wherein the second pattern is staggered from the fourth pattern along the first direction; the first pattern and the third pattern are correspondingly overlapped along the first direction; the second pattern and the fourth pattern are used for determining the alignment deviation of the first pattern and the third pattern.

7. The method of claim 6,

along the first direction, the patterned second mask layer comprises a plurality of third preset patterns arranged at equal intervals and a plurality of fourth preset patterns arranged at equal intervals; the distance between two adjacent fourth preset patterns is equal to the distance between two adjacent third preset patterns;

along the first direction, the patterned first mask layer comprises a plurality of first preset patterns arranged at equal intervals and a plurality of second preset patterns arranged at equal intervals; wherein,

the distance between every two adjacent second preset patterns is equal to the distance between every two adjacent first preset patterns;

or,

the distance between two adjacent second preset patterns is equal to 2 times of the distance between two adjacent first preset patterns.

8. The method of claim 6,

along the first direction, the patterned first mask layer comprises a plurality of first preset patterns which are arranged at equal intervals and a plurality of second preset patterns which are arranged at equal intervals; the distance between two adjacent second preset patterns is equal to the distance between two adjacent first preset patterns;

along the first direction, the patterned second mask layer comprises a plurality of third preset patterns arranged at equal intervals and a plurality of fourth preset patterns arranged at equal intervals; and the distance between two adjacent fourth preset patterns is equal to 3 times of the distance between two adjacent third preset patterns.

9. A semiconductor device, comprising: a first pattern in a core region of a substrate;

the first pattern and the second pattern are the same in size, arranged in parallel along a first direction and provided with a first preset distance; wherein the first direction is parallel to the substrate;

a third pattern in the core region, the third pattern penetrating through the dielectric layer covering the substrate; the third patterns and the first patterns are correspondingly arranged in an overlapping mode along the first direction;

a fourth pattern located in the edge region, wherein the fourth pattern penetrates through the dielectric layer; the third pattern and the fourth pattern are the same in size, and are arranged in parallel along the first direction and have a second preset distance; the fourth pattern is staggered with the second pattern along the first direction;

the second pattern and the fourth pattern are used for determining the alignment deviation of the first pattern and the third pattern.

10. The semiconductor device according to claim 9, wherein along the first direction, the semiconductor device comprises:

a plurality of the third patterns arranged at equal intervals and a plurality of the fourth patterns arranged at equal intervals; wherein, along the first direction, the distance between two adjacent fourth patterns is equal to the distance between two adjacent third patterns;

a plurality of the first patterns arranged at equal intervals and a plurality of the second patterns arranged at equal intervals; wherein,

the distance between two adjacent second patterns is equal to the distance between two adjacent first patterns;

or,

the distance between two adjacent second patterns is equal to 2 times of the distance between two adjacent first patterns.

11. The semiconductor device according to claim 9, wherein along the first direction, the semiconductor device comprises:

a plurality of the first patterns arranged at equal intervals and a plurality of the second patterns arranged at equal intervals; wherein, the distance between two adjacent second patterns is equal to the distance between two adjacent first patterns;

a plurality of the third patterns arranged at equal intervals and a plurality of the fourth patterns arranged at equal intervals; wherein, along the first direction, the distance between two adjacent fourth patterns is equal to 3 times of the distance between two adjacent third patterns.

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