CN113674699A - Driving method and device and display device - Google Patents

Abstract

Embodiments of the present disclosure provide a driving method and device, and a display device. The driving method includes: when the display panel is driven, the following operations are performed for each frame of display duration: in a first display period, a first scan start signal and an enable initial signal are provided to a first gate driver to control the first gate driver The gate driver performs line-by-line scanning on a plurality of gate lines in the first display area in the first driving period, and suspends operation in the first holding period after the first driving period; in the second display period, the gate driver is provided with The second scan start signal and the enable initial signal control the second gate driver to scan the plurality of gate lines of the second display area line by line during the second driving period, and during the second maintaining period after the second driving period Pause work.

Description

Driving method and device, and display device

technical field

The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, relate to a driving method and device, and a display device.

Background technique

Organic Light Emitting Diode (OLED) is an active light-emitting display device, which has the advantages of self-luminescence, wide viewing angle, high contrast ratio, extremely high response speed, thinness, flexibility and low cost. With the continuous development of display technology, display devices using OLEDs as light-emitting devices and signal-controlled by thin film transistors (Thin Film Transistor, TFT) have become mainstream products in the display field at present.

SUMMARY OF THE INVENTION

The following is an overview of the topics detailed in this article. This summary is not intended to limit the scope of protection of the claims.

In a first aspect, an embodiment of the present disclosure provides a driving method, applied to a display panel, the display panel includes: a first display area and a second display area, a plurality of grid lines in the first display area and a first grid The driver is connected, and the plurality of gate lines in the second display area are connected to the second gate driver; the driving method includes: when the display panel is driven, the following operations are performed for each frame display duration:

During the first display period, a first scan start signal and an enable initial signal are provided to the first gate driver, so as to control the first gate driver to control the plurality of gate lines of the first display area during the first driving period performing progressive scanning, and suspending work in the first holding period after the first driving period;

During the second display period, a second scan start signal and the enable initial signal are provided to the second gate driver, and the second gate driver is controlled to scan the second display area during the second driving period. The plurality of gate lines are scanned row by row, and the operation is suspended during the second holding period after the second driving period.

In a second aspect, an embodiment of the present disclosure provides a driving device applied to a display panel, where the display panel includes: a first display area and a second display area, and the first display area and the second display area respectively include: multiple grid lines;

The driving device includes a driving controller, a first gate driver and a second gate driver connected to the driving controller, the first gate driver and a plurality of gate lines of the first display area connected, the second gate driver is connected to a plurality of gate lines of the second display area; wherein,

The drive controller is configured to provide a first scan start signal and an enable initial signal to the first gate driver during a first display period, and to control the first gate driver to scan the first gate driver during a first drive period. The plurality of gate lines in the first display area are scanned row by row, and the operation is suspended in the first holding period after the first driving period; in the second display period, a second scanning start signal is provided to the second gate driver and the enable initial signal to control the second gate driver to perform progressive scanning on a plurality of gate lines of the second display area in a second driving period, and a second holding period after the second driving period suspend work;

The first gate driver is configured to perform line-by-line scanning on the plurality of gate lines of the first display area during a first driving period based on the first scan start signal and the enable initial signal, and perform line-by-line scanning on the plurality of gate lines in the first display area during the first driving period. Suspend work during the first hold period;

The second gate driver is configured to perform progressive scanning on a plurality of gate lines in the second display area during a second driving period based on the second scan start signal and the enable initial signal, Suspend work during the second hold period.

In a third aspect, embodiments of the present disclosure provide a display device, comprising: a display panel and the driving device described in the above embodiments, wherein the display panel includes: a first display area and a second display area, the The first display area and the second display area respectively include: a plurality of gate lines.

In the driving method, device and display device provided by the embodiments of the present disclosure, by dividing the display panel into at least a first display area and a second display area, the grid lines of the display panel are divided into at least a plurality of grid lines and a plurality of grid lines of the first display area and a second display area. A plurality of gate lines in the second display area, and when the display panel is driven, in the display duration of each frame, in the first display period, under the control of the first scan start signal GSTV1 and the enable initial signal ESTV , the multiple gate lines in the first display area are scanned row by row by the first gate driver, after the multiple gate lines in the first display area are scanned, the first gate driver suspends work for a certain period of time; In the second display period after the first display period, under the control of the second scan start signal GSTV2 and the enable initial signal ESTV, the second gate driver performs progressive scanning on the plurality of gate lines in the second display area , after the scanning of the plurality of gate lines in the second display area is completed, the second gate driver suspends operation for a certain period of time. In this way, compared with the driving scheme that drives all the gate lines of the display panel within the display duration of each frame, when the driving frequency remains unchanged (that is, the display duration of one frame remains unchanged), the multiple gate lines in each display area are After the line scan is over, the gate driver is controlled to suspend work, which can effectively reduce part of the power consumption.

Other features and advantages of the present disclosure will be set forth in the description that follows, and in part will be apparent from the description, or will be learned by practice of the present disclosure. Other advantages of the present disclosure may be realized and attained by the aspects described in the specification and drawings.

Other aspects will become apparent upon reading and understanding of the drawings and detailed description.

Description of drawings

The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not limit the technical solutions of the present disclosure. The shapes and sizes of the various components in the drawings do not reflect true scale, and are only intended to illustrate the present disclosure.

FIG. 1 is a schematic diagram of signal timing in a driving mode;

FIG. 2 is a schematic structural diagram of a display panel in an exemplary embodiment of the present disclosure;

FIG. 3 is a schematic flowchart of a driving method in an exemplary embodiment of the present disclosure;

FIG. 4 is a schematic diagram of signal timing in a driving method in an exemplary embodiment of the present disclosure;

FIG. 5 is a schematic structural diagram of a driving device in an exemplary embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of a display device in an exemplary embodiment of the present disclosure.

Detailed ways

Various embodiments are described herein, but the description is exemplary rather than restrictive, and further embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Unless expressly limited, any feature or element of any embodiment may be used in combination with, or may be substituted for, any other feature or element of any other embodiment.

In describing representative embodiments, the specification may have presented methods and/or processes as a particular sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps herein, the method or process should not be limited to the specific order of the steps. Other sequences of steps are possible, as will be understood by those of ordinary skill in the art. Therefore, the specific order of steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to performing their steps in the order written, as those skilled in the art will readily appreciate that these orders may be varied and still remain within the spirit and scope of the disclosed embodiments Inside.

In the drawings of the present disclosure, the size of each constituent element, the thickness of a layer, or a region are sometimes exaggerated for clarity. Therefore, one form of the present disclosure is not necessarily limited to this size, and the shapes and sizes of the various components in the drawings do not reflect true scale. In addition, the drawings schematically show ideal examples, and one form of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

In the exemplary embodiments of the present disclosure, ordinal numbers such as "first", "second", and "third" are set to avoid confusion of constituent elements, rather than to limit the quantity.

In the exemplary embodiments of the present disclosure, "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top" and "bottom" are used for convenience , "inside", "outside" and other words indicating orientation or positional relationship are used to describe the positional relationship of the constituent elements with reference to the accompanying drawings, which are only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the indicated device or element must be It has a particular orientation, is constructed and operates in a particular orientation, and therefore should not be construed as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

In the exemplary embodiments of the present disclosure, the terms "installed", "connected" and "connected" should be construed in a broad sense unless otherwise expressly specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood in specific situations.

In this specification, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (also known as a drain terminal, drain region, or drain electrode) and a source electrode (also known as a source terminal, source region, or source electrode), and current can flow through the drain electrode, channel region and source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

In this specification, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. The functions of the "source electrode" and the "drain electrode" may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements. Examples of "elements having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

"About" in an exemplary embodiment of the present disclosure refers to a numerical value within an acceptable range of process and measurement error without strictly defining a limit.

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure.

Current OLED display devices have been pursuing low power consumption and multi-frequency driving, and the carrier mobility of Low Temperature Polycrystalline Oxide (LTPO) is 20% of that of amorphous silicon (a-Si). To 30 times, can greatly improve the thin film transistor (Thin Film Transistor, TFT) charge and discharge rate of the pixel electrode, improve the pixel response speed, achieve a faster refresh rate, while the faster response also greatly improves the pixel line scan speed, making ultra-high resolution (Pixel Per Inch, PPI) possible in OLED display devices. However, as shown in FIG. 1, the current driving scheme, when driving a Low Temperature Poly-Silicon (LTPS) OLED display device, is usually controlled by the scanning start signal GSTV and the enable initial signal ESTV. The driving method for driving all gate lines of the display panel during each frame display duration, therefore, the pixel driving circuit connected to the gate lines is continuously powered during each frame display duration, resulting in high power consumption of the display panel.

Embodiments of the present disclosure provide a driving method, which can be applied to driving a display panel. For example, the display panel may include: a first display area and a second display area, a plurality of gate lines in the first display area are connected to the first gate driver, and a plurality of gate lines in the second display area are connected to the second gate driver . The driving method includes: when the display panel is driven, the following operations are performed for each frame of display duration: in a first display period, a first scan start signal and an enable initial signal are provided to a first gate driver to control the first gate driver The gate driver performs line-by-line scanning on a plurality of gate lines in the first display area in the first driving period, and suspends operation in the first holding period after the first driving period; in the second display period, the gate driver provides The second scan start signal and the enable initial signal control the second gate driver to scan the plurality of gate lines of the second display area line by line during the second drive period, and during the second hold period after the second drive period Pause work.

In an exemplary embodiment, "the first gate driver performs line-by-line scanning on a plurality of gate lines in the first display area during the first driving period" may include: the first gate driver sequentially scans all gate lines in the first display area in sequence. The pixel driving circuits respectively connected to the plurality of gate lines included output scan signals to turn on the pixel driving circuits respectively connected to the plurality of gate lines included in the first display area.

In an exemplary embodiment, "the first gate driver suspends operation for the first holding period after the first driving period" may refer to the first holding period of the first gate driver after the first driving period, not the Any one of the plurality of gate lines in the first display area is scanned, but the pixels in the first display area can keep the light-emitting state. For example, "the first gate driver suspends operation during the first maintaining period after the first driving period" may include: the first maintaining period of the first gate driver after the first driving period The pixel drive circuits connected to each of the gate lines stop outputting the scan signal or output the invalid signal, so as not to scan any one of the multiple gate lines in the first display area. At this time, the first gate driver stops the The pixel driving circuit corresponding to a pixel in a display area is charged, and the pixel driving circuit only needs to keep it, and no power is needed to maintain the power of the pixel. The good TFT characteristics in the pixel driving circuit can maintain enough power to maintain the brightness of the pixel. .

In an exemplary embodiment, "the second gate driver performs line-by-line scanning on a plurality of gate lines in the second display area during the second driving period" may include: the second gate driver sequentially scans all gate lines in the second display area in sequence. The pixel driving circuits respectively connected to the plurality of gate lines included output valid scan signals to turn on the pixel driving circuits respectively connected to the plurality of gate lines included in the second display area.

In an exemplary embodiment, "the second gate driver suspends operation for the second holding period after the second driving period" may refer to the second holding period of the second gate driver after the second driving period, not the Any one of the plurality of gate lines in the second display area is scanned, but the pixels in the second display area can keep the light-emitting state. For example, "the second gate driver suspends operation during the second maintaining period after the second driving period" may include: the second maintaining period of the second gate driver after the second driving period The pixel drive circuits connected to each of the gate lines stop outputting the scan signal or output the invalid signal, so as not to scan any gate line among the multiple gate lines in the second display area, at this time, the second gate driver stops scanning the first gate line. The pixel driving circuit corresponding to the pixels in the second display area is charged, and the pixel driving circuit only needs to keep it. It does not need to be powered on to maintain the power of the pixel. The good TFT characteristics in the pixel driving circuit can maintain enough power to maintain the brightness of the pixel. .

In the driving method provided by the embodiments of the present disclosure, by dividing the display panel into at least a first display area and a second display area, the grid lines of the display panel are divided into at least a plurality of grid lines of the first display area and a plurality of grid lines of the second display area. A plurality of gate lines, and when the display panel is driven, in the display duration of each frame, in the first display period, under the control of the first scan start signal GSTV1 and the enable initial signal ESTV, through the first gate The gate driver scans the plurality of gate lines in the first display area line by line. After the scanning of the plurality of gate lines in the first display area is completed, the first gate driver suspends work for a certain period of time; then, after the first display period In the second display period, under the control of the second scan start signal GSTV2 and the enable initial signal ESTV, the second gate driver scans the plurality of gate lines in the second display area row by row. After each gate line is scanned, the second gate driver suspends operation for a certain period of time. In this way, when the driving method is applied to drive the LTPO display panel, the pause operation period is increased after the scanning of a plurality of gate lines in each display area is completed, and the gate driver pauses the operation during the pause operation (paμse) operation. , that is, the gate line is not scanned, but the pixel can keep the light-emitting state. At this time, the pixel drive circuit only needs to keep it, and no power is needed to maintain the power of the pixel. The good TFT characteristics of LTPO can maintain enough power. To maintain the brightness of the pixel, the advantage of this is to reduce power consumption. Therefore, compared with the driving method that drives all the gate lines of the display panel within the display duration of each frame, when the driving frequency remains unchanged (that is, the display duration of one frame remains unchanged), by increasing the duration of the pause operation, it is possible to reduce the The scanning time of the gate line reduces the charging time of the TFT, thereby effectively reducing a part of the power consumption. Moreover, during the pause (paμse) operation, due to the good TFT characteristics of the LTPO, sufficient power can be maintained to maintain the brightness of the pixel, which can effectively improve flicker, thereby improving the display effect of the display panel.

The driving method provided by the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

FIG. 2 is a schematic structural diagram of a display panel in an exemplary embodiment of the present disclosure. As shown in FIG. 2 , on a plane parallel to the display panel, the display panel may include: a display area 100 and a non-display area around the display area 100 , The non-display area may include: the binding area 200 on one side of the display area 100 and the border area 300 on the other side of the display area 100 . For example, the binding area 200 may be located on one side (upper side) of the display area 100 in the first direction DR1.

In an exemplary embodiment, the display area 100 may include: a plurality of display areas. For example, the display area may include: two display areas, three display areas, or four display areas, and the like. For example, the plurality of display areas may be divided uniformly, or may be divided non-uniformly. Here, this embodiment of the present disclosure does not limit this.

In an exemplary embodiment, according to the number of grid lines included in the display panel, the number of display areas included in the display panel may be divided by a uniform division manner or a non-uniform division manner, wherein when the uniform division manner is adopted, more The number of grid lines included in each display area may be equal, or, when a non-uniform division method is adopted, the number of grid lines included in at least two display areas in the plurality of display areas may be unequal. Here, this embodiment of the present disclosure does not limit this.

For example, if the display panel is a Full High Definition (FHD) panel, that is, the number of grid lines (that is, the number of rows) included in the display panel can be 1080, then, according to the number of grid lines included in the display panel When the uniform division method is adopted, the display area of the display panel can be divided into 2 display areas. At this time, the number of grid lines included in each display area can be 540, or the display area of the display panel can be divided into 3 display areas. In this case, the number of gate lines included in each display area may be 360. For another example, the number of grid lines (ie, the number of rows) included in the display panel can be 1440 as an example, then, when the uniform division method is adopted according to the number of grid lines included in the display panel, the display area of the display panel can be divided into 2 display areas, at this time, the number of grid lines included in each display area can be 720, or the display area of the display panel can be divided into 4 display areas, at this time, the grid lines included in each display area can be The number can both be 360.

In an exemplary embodiment, taking a display panel that can be divided into two display areas as an example, as shown in FIG. 2 , the display panel may include: a first display area 101 (the upper display area 101 is arranged in sequence along the first direction DR1 area) and the second display area 102 (lower display area). Wherein, both the first display area 101 and the second display area 102 may include: a plurality of gate lines (also referred to as scan signal lines). For example, the first display area 101 may include multiple gate lines (S11 to S1m), the second display area 102 may include multiple gate lines (S21 to S2n), m may be a natural number, and n may be a natural number. For example, the display panel may further include: a first gate driver, a second gate driver located in the non-display area, and a driving controller connected to the first gate driver and the second gate driver, wherein the first display area A plurality of gate lines (S11 to S1m) of 101 may be connected with the first gate driver, a plurality of gate lines (S21 to S2n) of the second display area 102 may be connected with the second gate driver, and the driving controller may be configured The scan signal is applied for controlling the first gate driver and for applying the scan signal for controlling the second gate driver. The plurality of gate lines (S11 to S1m) of the first display area 101 and the plurality of gate lines (S21 to S2n) of the second display area 102 may extend along the second direction DR2, which intersects the first direction DR1. For example, the second direction DR2 may be perpendicular to the first direction DR1. Here, the number and positional relationship of the display areas in FIG. 2 are merely illustrative, and do not represent the actual number and positional relationship. In addition, the number and positional relationship of the signal lines in the display panel in FIG. 2 is only an exemplary illustration, and the actual number and arrangement position can be designed according to application scenarios.

In an exemplary embodiment, taking the display panel including: a first display area and a second display area as an example, the first display area and the second display area may be divided uniformly or non-uniformly. Here, this embodiment of the present disclosure does not limit this.

In an exemplary embodiment, taking a display panel including a first display area and a second display area as an example, the number of grid lines in the first display area and the number of grid lines in the second display area may be equal.

In an exemplary embodiment, taking a display panel including a first display area and a second display area as an example, the grid lines included in the first display area and the grid lines included in the second display area may not overlap.

FIG. 3 is a schematic flowchart of a driving method according to an exemplary embodiment of the present disclosure. As shown in FIG. 3 , the driving method may include: when driving the display panel in one or more of the above-mentioned embodiments, display for each frame The duration T0 can do the following:

Step 31: During the first display period T1, provide the first scan start signal GSTV1 and the enable initial signal ESTV to the first gate driver, and control the first gate driver to perform multiple operations on the first display area during the first driving period T11. The gate lines (S11 to S1m) are scanned row by row, and work is suspended in the first holding period T12 after the first driving period T11;

Step 32: In the second display period T2, provide the second scan start signal GSTV2 and the enable initial signal ESTV to the second gate driver, and control the second gate driver to perform multiple operations on the second display area during the second driving period T21. The gate lines (S21 to S2n) are scanned row by row, and the operation is suspended during the second holding period T22 after the second driving period T21.

In an exemplary embodiment, step 31 may include: during the first display period T1, providing the first scan start signal GSTV1 and the enable initial signal ESTV to the first gate driver; during the first scan start signal GSTV1 And under the control of the enable initial signal ESTV, the first gate driver sequentially turns on the pixel driving circuits respectively connected to the plurality of gate lines (S11 to S1m) included in the first display area. Next, after the pixel driving circuits connected to the plurality of gate lines (S11 to S1m) are sequentially turned on, the first gate driver is in a suspended operation state, and stops driving the pixels connected to the plurality of gate lines (S11 to S1m) respectively. The circuit outputs a scan signal or an invalid signal, and stops charging the pixel drive circuit.

In an exemplary embodiment, step 32 may include: in the second display period T2, providing a second scan start signal GSTV2 and an enable initial signal ESTV to the second gate driver; the second scan start signal GSTV2 and Under the control of the enabling initial signal ESTV, the second gate driver sequentially turns on the pixel driving circuits respectively connected to the plurality of gate lines (S21 to S2n) included in the second display area. Next, after the pixel driving circuits respectively connected to the plurality of gate lines (S21 to S2n) included in the second display area are turned on in sequence, the second gate driver is in a suspended working state, and stops sending signals to the gate lines (S21 to S2n) included in the second display area. The pixel driving circuits to which the plurality of gate lines ( S21 to S2n ) are connected respectively output a scan signal or an invalid signal, and stop charging the pixel driving circuit.

In an exemplary embodiment, the display area of the display panel may be divided into a plurality of display areas, then, the display duration of one frame may include: a plurality of display periods, each of which includes a drive period and a hold period, that is, a The frame display duration may include a plurality of driving periods and a plurality of holding periods which are alternately arranged. Wherein, multiple may include, but not be limited to, two, three, or four, and the like. Here, this embodiment of the present disclosure does not limit this.

For example, taking the display area of the display panel divided into two display areas, including: a first display area and a second display area, for example, the display duration of one frame may include: a first display period T1 (corresponding to the first display area) , may include: a first driving period T11 and a first holding period T12) and a second display period T2 (corresponding to the second display area, may include: a second driving period T21 and a second holding period T22), that is, a frame of display The duration may include: a first driving period T11 , a first holding period T12 , a second driving period T21 and a second holding period T22 , which are sequentially set.

For example, taking the display area of the display panel divided into three display areas, including: the first display area, the second display area and the third display area as an example, then the display duration of one frame may include: the first display period T1 (with the Corresponding to the first display area, it may include: a first driving period T11 and a first holding period T12), a second display period T2 (corresponding to the second display area, and may include: a second driving period T21 and a second holding period T22) and a third display period T3 (corresponding to the third display area, which may include: a third driving period T31 and a fourth holding period T32).

In an exemplary embodiment, the display duration T0 of one frame may refer to the time taken to actually display one frame of image. Here, this embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the display duration T0 of one frame is related to the driving frequency f, where T0=1/f (second). For example, taking the driving frequency as 60 Hz (Hertz) as an example, the display duration of one frame may be about 16.67 ms (milliseconds).

In an exemplary embodiment, according to the difference in the number of grid lines in the first display area and the number of grid lines in the second display area, the duration of the first display period T1 (ie, the display duration corresponding to the first display area) and the The durations of the two display periods T2 (ie, the display durations corresponding to the second display area) may be equal, or may be unequal. Here, this embodiment of the present disclosure does not limit this.

For example, taking the same number of grid lines in the first display area as the number of grid lines in the second display area, the display duration T0 of one frame can be evenly divided into the first display period T1 and the second display period T2, that is, the first display period T1 and the second display period T2. The duration of a display period T1 (ie, the display duration corresponding to the first display area) and the duration of the second display period T2 (ie, the display duration corresponding to the second display area) may be equal. For example, taking the driving frequency of 60 Hz (Hertz) as an example, the display duration T0 of one frame can be about 16.67 ms (milliseconds). Since the durations of the display periods of multiple display areas can be equal, then, one display period of one display area The duration = one frame display duration T0 / the number of display areas, that is, the duration of the first display period T1 and the second display period T2 may both be approximately 8.33ms.

In an exemplary embodiment, for at least one display period (including the driving period and the holding period) among the plurality of display periods in the display period of one frame, the ratio between the duration of the driving period and the duration of the holding period may be is a preset integer value, where the preset integer value may include, but is not limited to, 2 or 3, etc. For example, taking the display area of the display panel divided into two display areas, including the first display area and the second display area, as an example, the ratio between the duration of the first driving period T11 and the duration of the first holding period T12 is the The ratio between the duration of the second driving period T21 and the duration of the second holding period T22 may include, but is not limited to, 2 or 3, and the like. In this way, not only low power consumption can be ensured, but also flicker can be improved more effectively. Here, this embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the enable initial signal ESTV may be a pulse width modulated PWM signal, and the display duration T0 of one frame may include, but is not limited to, K times the period T of the PWM signal, that is, the display duration T0 of one frame includes The number of cycles of the PWM signal is K, T0=K*T. For example, K may include, but is not limited to, any one of 6, 8, and 12. In this way, not only low power consumption can be ensured, but also flicker can be improved more effectively. Here, this embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the time interval between the trigger time t_g2 of the second scan start signal GSTV2 and the trigger time t_g1 of the first scan start signal GSTV1 may include, but is not limited to, two times the display duration T0 for one frame. One-half (1/2) times, that is, t_g2-t_g1=0.5*T0. For example, the time interval between the trigger time t_g2 of the second scan start signal GSTV2 and the trigger time t_g1 of the first scan start signal GSTV1 may include, but is not limited to, one-half of the display duration T0 of one frame. Here, this embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the same signal line may be used to provide the first scan start signal GSTV1 to the first gate driver and the second scan start signal GSTV2 to the second gate driver, that is, to provide the second scan The initial input signal provided by the signal line of the start signal GSTV2 can share the initial input signal of the signal line of the first scan start signal GSTV1, but the second scan start signal GSTV2 is 1/2 frame later than GSTV1 at the trigger time. can be achieved. Here, this embodiment of the present disclosure does not limit this.

In the description of the embodiments of the present disclosure, the symbol GSTV1 may represent both the first scan start signal and the signal line that provides the first scan start signal. The symbol GSTV2 may represent both the second scan start signal and the signal line that supplies the second scan start signal. The symbol ESTV can represent both the enable initial signal and the signal line that provides the enable initial signal.

Below, the display area of the display panel is divided into two display areas, including: a first display area and a second display area, and the number of grid lines included in the first display area and the number of grid lines included in the second display area are equal to For example, the driving method provided by the exemplary embodiment of the present disclosure will be described.

FIG. 4 is a schematic diagram of signal timing in a driving method in an exemplary embodiment of the present disclosure, wherein One frame shows the waveform graph over the duration.

In an exemplary embodiment, as shown in FIG. 4 , the duty cycle of the enable initial signal ESTV may include, but is not limited to, 50%. Wherein, the duty cycle of the enabling initial signal ESTV may refer to the ratio between the pulse width (also called pulse width) ton of the enabling initial signal ESTV and the period T of enabling the initial signal ESTV, and the enabling initial signal ESTV The pulse width ton may refer to the duration of a pulse having an on level (eg, a low level). Wherein, the duty cycle of the enable initial signal ESTV in FIG. 4 is only an exemplary illustration, and the actual duty cycle of the enable initial signal ESTV can be designed according to the requirements of the application scenario (eg, brightness requirements). Here, this embodiment of the present disclosure does not limit this.

In an exemplary embodiment, as shown in FIG. 4 , the initial enable signal ESTV may be a PWM signal, and the number of cycles of the PWM signal included in the display duration T0 of one frame may include, but is not limited to, 6. The number of cycles of the PWM signal included in the one-frame display duration T0 in FIG. 4 is merely an exemplary illustration, and the actual number of cycles of the PWM signal included in the one-frame display duration T0 can be designed according to the needs of the application scenario . Here, this embodiment of the present disclosure does not limit this.

In an exemplary embodiment, as shown in FIG. 4 , the duration of the first display period T1 (ie the display duration corresponding to the first display area) and the duration of the second display period T2 (ie the display duration corresponding to the second display area) duration) are equal, wherein the number of cycles of the PWM signal included in the duration of the first display period T1 may be 3, and the number of cycles of the PWM signal included in the duration of the second display period T2 may be 3. In the first display period T1 The number of cycles of the PWM signal included in the duration of the first driving period T11 may be 2, the number of cycles of the PWM signal included in the duration of the first holding period T12 in the first display period T1 may be 1, and the number of cycles of the PWM signal included in the second display period The number of cycles of the PWM signal included in the duration of the second driving period T21 in T2 may be 2, and the number of cycles of the PWM signal included in the duration of the second holding period T22 in the second display period T2 may be 1, that is, the first The ratio between the duration of the first driving period T11 and the duration of the first maintaining period T12 may be 2, and the ratio between the duration of the second driving period T21 and the duration of the second maintaining period T22 may be 2.

For example, taking the driving frequency as 60 Hz (Hertz) as an example, the display duration T0 of one frame may be 16.67 ms (milliseconds). And the display duration T0 of one frame = the duration of the first display period T1 + the duration of the second display period T2, then, when the duration of the first display period T1 is equal to the duration of the second display period T2, the duration of the first display period T1 Both the duration and the duration of the second display period T2 may be about 8.33 ms.

For example, taking the duration of the first display period T1 as about 8.33 ms as an example, the duration of the first display period T1 = the duration of the first driving period T11 + the duration of the first holding period T12, then, when the first driving period T11 When the ratio between the duration of the first driving period T11 and the duration of the first holding period T12 is 2, the duration of the first driving period T11 may be about 5.55ms, and the duration of the first holding period T12 may be about 2.78ms. For example, taking the number of gate lines included in the first display area as an example of 540, then, the scanning time of one row in the first display area is 1H Time = the duration of the first driving period T11 / the number of gate lines included in the first display area = 5.55ms/540=10.27μs (microseconds).

For example, taking the duration of the second display period T2 as an example of about 8.33 ms, the duration of the second display period T2 = the duration of the second driving period T21 + the duration of the second holding period T22, then, when the second driving period T21 When the ratio between the duration of the second driving period T21 and the duration of the second holding period T22 is 2, the duration of the second driving period T21 may be about 5.55ms, and the duration of the second holding period T22 may be about 2.78ms. For example, taking the number of gate lines included in the second display area as an example of 540, then the scanning time of one row in the second display area is 1H Time = the duration of the second driving period T21 / the number of gate lines included in the second display area = 5.55ms/540=10.27μs.

It has been verified by the inventor of the present disclosure that: under the gray255 (white) screen, the flicker result (JEITA value) of the display panel is verified on a Field Programmable Gate Array (FPGA), and the test result is: using When the driving method shown in FIG. 1 drives the LTPS display panel, the result of flickering of the LTPS display panel (JEITA value) is -26.34db. The result of panel flashing (JEITA value) is -37.69db. It can be seen from the experimental results that the driving method provided by the exemplary embodiment of the present disclosure can not only effectively reduce the power consumption of the display panel, but also effectively improve the flicker problem of the display panel.

An embodiment of the present disclosure provides a driving device, which can be applied to driving a display panel. For example, it can be applied to a display device, and the driving device can be connected with a display panel in the display device.

Embodiments of the present disclosure also provide a display device. The display device may include: a display panel in one or more exemplary embodiments and a driving device in one or more exemplary embodiments, the driving device being connected to the display panel.

FIG. 5 is a schematic structural diagram of a driving device in an exemplary embodiment of the present disclosure. FIG. 6 is a schematic structural diagram of a display device in an exemplary embodiment of the present disclosure. Wherein, in FIG. 6 , the display panel includes two display areas as an example for illustration. The driving device and the display device provided by the embodiments of the present disclosure will be described below with reference to FIG. 5 and FIG. 6 .

In an exemplary embodiment, as shown in FIG. 5 and FIG. 6 , the display panel may include: a first display area 101 and a second display area 102, and the first display area 101 may include a plurality of gate lines (S11 to S1m ), the second display area 102 may include: a plurality of gate lines (S21 to S2n), m may be a natural number, and n may be a natural number. The driving device may include a driving controller 50 , and a first gate driver 51 and a second gate driver 52 connected to the driving controller 50 . The first gate driver 51 is connected to a plurality of gate lines (S11 to S1m) of the first display area 101, and the second gate driver 52 is connected to a plurality of gate lines (S21 to S2n) of the second display area 102; wherein, The driving controller 50 is configured to provide the first scan start signal GSTV1 and the enable initial signal ESTV to the first gate driver 51 during the first display period T1, and control the first gate driver 51 during the first driving period T11 The plurality of gate lines (S11 to S1m) of the first display area 101 are scanned line by line, and the operation is suspended in the first holding period T12 after the first driving period T11; The driver 52 provides the second scan start signal GSTV2 and the enable initial signal ESTV, and controls the second gate driver 52 to scan the plurality of gate lines (S21 to S2n) of the second display area row by row during the second driving period T21, And the second holding period T22 after the second driving period T21 suspends the work; the first gate driver 51 is configured to be based on the first scan start signal GSTV1 and the enable initial signal ESTV, during the first driving period T11 to the first gate driver 51 A plurality of gate lines (S11 to S1m) of a display area 101 are scanned row by row, and the operation is suspended in the first holding period T12 after the first driving period T11; the second gate driver 52 is configured to be based on the second scanning The start signal GSTV2 and the enable initial signal ESTV perform progressive scanning on a plurality of gate lines (S21 to S2n) of the second display area during the second driving period T21, and a second holding period after the second driving period T21 T22 suspended work.

In an exemplary embodiment, as shown in FIGS. 5 and 6 , the driving controller 50 , configured for the first display period T1 , provides the first gate driver 51 with the first scan start signal GSTV1 and the enable The initial signal ESTV controls the first gate driver 51 to sequentially turn on the pixel driving circuits respectively connected to the plurality of gate lines ( S11 to S1 m ) included in the first display area 101 . Next, after the pixel driving circuits connected to the plurality of gate lines (S11 to S1m) are sequentially turned on, the first gate driver 51 is in a suspended operation state, and stops the pixels connected to the plurality of gate lines (S11 to S1m) respectively. The drive circuit outputs a scan signal or an invalid signal, and stops charging the pixel drive circuit.

In an exemplary embodiment, as shown in FIGS. 5 and 6 , the driving controller 50 is configured to provide the second gate driver 52 with the second scan start signal GSTV2 and enable the second gate driver 52 during the second display period T2 The initial signal ESTV can be used to control the second gate driver 52 to sequentially turn on the pixel driving circuits respectively connected to the plurality of gate lines ( S21 to S2n ) included in the second display area 102 . Next, after the pixel driving circuits respectively connected to the plurality of gate lines ( S21 to S2n ) included in the second display area 102 are turned on in sequence, the second gate driver 52 is in a suspended working state, and stops driving to the second display area 102 The pixel driving circuits to which the plurality of gate lines (S21 to S2n) are connected respectively output the scan signal or output the invalid signal, and stop charging the pixel driving circuit.

In an exemplary embodiment, the implementation form of the drive controller may take various forms. For example, the drive controller may be a timing control circuit (T-con). For example, the drive controller may be a Micro Controller Unit (Micro Controller Unit, MCU). For example, the drive controller may include a processor and a memory, and the memory includes executable code, and the processor executes the executable code to execute the above-described driving method. Here, this embodiment of the present disclosure does not limit this.

For example, the processor may be a central processing unit (Central Processing Unit, CPU) or other form of processing device with data processing capability and/or instruction execution capability, for example, may include other general-purpose processors, digital signal processors (Digital Signal Processors) , DSP), programmable logic controller (PLC), field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, application specific integrated circuits, etc. The general-purpose processor may be a microprocessor (MicroProcessor Unit, MPU) or the processor may also be any conventional processor or the like. For example, the memory may include non-persistent memory in a computer-readable storage medium, random access memory (RAM) and/or non-volatile memory, etc., such as read only memory (ROM) or flash memory (Flash RAM), the memory includes at least one memory chip. One or more computer program instructions may be stored on a computer-readable storage medium, and a processor may execute the functions desired by the program instructions. Various application programs and various data can also be stored in the computer-readable storage medium. Here, this embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the first gate driver may be configured to generate gate lines S11 , S12 , S13 to be supplied to the first display area 101 by receiving a first scan start signal GSTV1 and the like from the driving controller , . . . and S1m scan signals, so as to perform progressive scan on the gate lines of the first display area 101 . For example, the first gate driver may be configured to sequentially supply scan signals having on-level pulses to the gate lines S11 , S12 , S13 , . . . and S1m of the first display area 101 . For example, the first gate driver may be an array substrate gate driver (Gate Driver on Array, GOA) circuit, and the GOA circuit may be constructed in the form of a shift register, including: a plurality of cascaded shift registers, which may be configured The scan signal is generated in such a manner that the first scan start signal GSTV1 supplied in the form of an on-level pulse is sequentially transmitted to the circuit of the next stage.

In an exemplary embodiment, the second gate driver may be configured to generate the gate lines S21 , S22 , S23 to be provided to the second display area 102 by receiving the second scan start signal GSTV2 and the like from the driving controller , . . . and S2n scan signals, so as to perform progressive scan on the gate lines of the second display area 102 . For example, the second gate driver may be configured to sequentially supply scan signals having on-level pulses to the gate lines S21 , S22 , S23 , . . . and S2n of the second display area 102 . For example, the second gate driver may be a GOA circuit, the GOA circuit may be configured in the form of a shift register, including: a plurality of cascaded shift registers, and may be configured to sequentially turn on-level pulses in the form of The scan signal is generated in a manner that the provided second scan start signal GSTV2 is transmitted to the next stage circuit.

In an exemplary embodiment, taking the gate driver as a GOA circuit as an example, the first gate driver includes: a first shift register group, and the first shift register group includes: a plurality of cascaded first shift registers register; the second gate driver includes: a second shift register group, the second shift register group includes: a plurality of cascaded second shift registers; the driving controller is configured to The first-stage shift register in the plurality of cascaded first shift registers provides the first scan start signal GSTV1 and the enable initial signal ESTV; in the second display period T2, shift to the plurality of cascaded second shift registers The first stage shift register in the register provides the second scan start signal GSTV2 and the enable initial signal ESTV.

For example, as shown in FIG. 6 , the signal line supplying the first scan start signal, the signal line supplying the second scan start signal, and the signal line supplying the enable initial signal may extend in the first direction DR1.

In an exemplary embodiment, as shown in FIG. 6 , the first gate driver 51 may be disposed in the frame area corresponding to the first display area 101 . For example, the first gate driver may be located in the frame area on the opposite side (left side) of the second direction DR2 of the first display area 101 , or may be located on the side (right side) of the first display area 101 in the second direction DR2 border area. Here, this embodiment of the present disclosure does not limit this.

In an exemplary embodiment, as shown in FIG. 6 , the second gate driver 52 may be disposed in the frame area corresponding to the second display area 102 . For example, the second gate driver may be located in the frame area on the opposite side (left side) of the second direction DR2 of the second display area 102 , or may be located on the side (right side) of the second display area 102 in the second direction DR2 border area. Here, this embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the display area may include: a plurality of pixel units arranged in a matrix, at least one of the plurality of pixel units may include: a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel The pixel Pxij may include: a pixel driving circuit and a light emitting device. Wherein, the pixel driving circuits in the sub-pixels are respectively connected with signal lines such as gate lines and data signal lines, the light-emitting devices in the sub-pixels are respectively connected with the pixel driving circuits of the sub-pixels where they are located, and the pixel driving circuits are configured to connect signals such as gate lines and the like. Under the control of the line, the data voltage transmitted by the data signal line is received, and the corresponding current is output to the light-emitting device. The light-emitting device is configured to emit light with corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

In an exemplary embodiment, as shown in FIG. 6 , the display panel may further include: a plurality of data signal lines (D1 to Dk), and the driving device may further include: a data signal driver, the data signal driver and the plurality of data signal lines Lines (D1 to Dk) are connected, and k can be a natural number.

In an exemplary embodiment, a plurality of data signal lines ( D1 to Dk ) and a plurality of gate lines ( S11 to S1 m ) included in the first display area 101 cross each other to define an array distribution in the first display area 101 A plurality of pixel units, a plurality of data signal lines (D1 to Dk) and a plurality of gate lines (S21 to S2n) included in the second display area 102 cross each other to define a plurality of array distributions in the second display area 102 In the pixel unit, at this time, the pixel driving circuits respectively connected to the plurality of gate lines (S11 to S1m) included in the first display area 101 are connected to the plurality of gate lines (S21 to S2n) included in the second display area 102. The pixel drive circuits can share the same data signal lines (D1 to Dk), and it can be guaranteed that there will be no mischarging.

In an exemplary embodiment, the drive controller may be configured to provide grayscale values and control signals suitable for the specifications of the data signal driver to the data signal driver. The data signal driver is configured to generate data voltages to be supplied to the data signal lines D1 , D2 , D3 , . . . and Dk using the grayscale values and control signals received from the driving controller. For example, the data signal driver is configured to sample grayscale values and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dk in pixel row units, where k may be a natural number.

In an exemplary embodiment, a plurality of sub-pixels in a pixel unit may be arranged in a horizontal parallel, a vertical parallel, an X-shape, a cross-shape or a fringe shape. For example, taking the pixel unit including three sub-pixels as an example, the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or a fret-shaped manner. For example, taking the pixel unit including four sub-pixels as an example, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel or square manner. Here, this embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the shape of the sub-pixels may be any one or more of triangles, squares, rectangles, diamonds, trapezoids, parallelograms, pentagons, hexagons, and other polygons. Here, this embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the pixel driving circuit may include, but is not limited to, pTqC such as 2T1C (ie, two transistors and one storage capacitor), 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C (p, q are positive integers) ) pixel drive circuit. Here, this embodiment of the present disclosure does not limit this.

In one exemplary embodiment, the light emitting device may be an organic electroluminescent diode (OLED) including a stacked first electrode (eg, serving as an anode), an organic light-emitting layer, and a second electrode (eg, serving as a cathode). Here, this embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the display panel may include, but is not limited to, an OLED display panel and the like.

In an exemplary embodiment, the display panel may include, but is not limited to, an LTPO display panel. For example, the first display area and the second display area may respectively include: pixel driving circuits. For example, the pixel driving circuit may include: an oxide transistor (Oxide TFT) and a low temperature poly-silicon thin film transistor (Low Temperature Poly-silicon TFT, LTPS TFT). In this way, during the holding period, the good TFT characteristics of LTPO can maintain enough power to maintain the brightness of the pixels, and compared with the LTPS display panel, black bars and flicker will not appear.

In addition, the display device in the embodiment of the present disclosure may include other necessary components and structures in addition to the above-mentioned structures such as the display panel and the driving device, for example, a source driver (Source Driver) circuit, etc. Those skilled in the art Corresponding designs and supplements can be made according to the type of the display device, which will not be repeated here.

In an exemplary embodiment, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, or a navigator. Here, the embodiment of the present disclosure does not limit the type of the display device. Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present disclosure.

The descriptions of the above apparatus embodiments are similar to the descriptions of the above method embodiments, and have similar beneficial effects to the method embodiments. For the technical details not disclosed in the embodiments of the display device of the present disclosure, those skilled in the art should refer to the descriptions in the description of the embodiments of the driving methods of the present disclosure to understand, and will not be repeated here.

Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, functional modules/units in the systems, and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components Components execute cooperatively. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those of ordinary skill in the art, the term computer storage media includes both volatile and nonvolatile implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules or other data flexible, removable and non-removable media. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or may Any other medium used to store desired information and which can be accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery media, as is well known to those of ordinary skill in the art .

Although the embodiments disclosed in the present disclosure are as above, the above-mentioned contents are only the embodiments adopted to facilitate the understanding of the present disclosure, and are not intended to limit the present disclosure. Any person skilled in the art to which this disclosure pertains, without departing from the spirit and scope disclosed in this disclosure, can make any modifications and changes in the form and details of implementation, but the scope of patent protection of this disclosure still needs to be The scope defined by the appended claims shall prevail.

Claims (13)

1. A driving method applied to a display panel, the display panel comprising: the display panel comprises a first display area and a second display area, wherein a plurality of grid lines of the first display area are connected with a first grid driver, and a plurality of grid lines of the second display area are connected with a second grid driver;

the driving method includes: when the display panel is driven, the following operations are executed for each frame of display duration:

in a first display period, providing a first scanning start signal and an enabling initial signal to the first gate driver, controlling the first gate driver to scan a plurality of gate lines of the first display area line by line in a first driving period, and suspending the operation in a first holding period after the first driving period;

and in a second display period, providing a second scanning starting signal and the enabling initial signal to the second gate driver, controlling the second gate driver to scan the plurality of gate lines of the second display area line by line in a second driving period, and suspending the operation in a second holding period after the second driving period.

2. The driving method according to claim 1, wherein the enable initialization signal is a Pulse Width Modulation (PWM) signal, one frame display duration is K times a period of the PWM signal, and K is any one of 6, 8, and 12.

3. The driving method according to claim 1, wherein a duration of the first display period and a duration of the second display period are equal.

4. A driving method according to any one of claims 1 to 3, wherein the ratio between the duration of the first driving period and the duration of the first holding period and the ratio between the duration of the second driving period and the duration of the second holding period are both preset integer values, the preset integer values being 2 or 3.

5. The driving method according to claim 1, wherein a time interval between a trigger timing of the second scan start signal and a trigger timing of the first scan start signal is one-half of a display time period of one frame.

6. A driving apparatus, applied to a display panel, the display panel comprising: a first display area and a second display area, the first display area and the second display area respectively comprising: a plurality of gate lines;

the driving device includes: the display device comprises a driving controller, a first grid driver and a second grid driver, wherein the first grid driver and the second grid driver are connected with the driving controller; wherein,

the driving controller is configured to provide a first scanning start signal and an enable initial signal to the first gate driver in a first display period, control the first gate driver to scan a plurality of gate lines of the first display region line by line in the first driving period, and suspend operation in a first retention period after the first driving period; in a second display period, providing a second scanning start signal and the enable initial signal to the second gate driver, controlling the second gate driver to scan the plurality of gate lines of the second display region line by line in a second driving period, and suspending operation in a second holding period after the second driving period;

the first gate driver is configured to scan a plurality of gate lines of the first display region line by line in a first driving period and suspend operation in a first holding period based on the first scan start signal and an enable initial signal;

the second gate driver is configured to scan a plurality of gate lines of the second display region line by line in a second driving period and pause operation in a second holding period based on the second scan start signal and the enable initial signal.

7. The drive device according to claim 6,

the first gate driver includes: a first shift register set, the first shift register set comprising: a plurality of cascaded first shift registers;

the second gate driver includes: a second shift register set, the second shift register set comprising: a plurality of cascaded second shift registers;

the driving controller configured to supply the first scan start signal and the enable start signal to a first stage shift register of the plurality of cascaded first shift registers in a first display period; and providing the second scan start signal and the enable initialization signal to a first stage shift register of the plurality of cascaded second shift registers in a second display period.

8. The driving apparatus according to claim 6, wherein the enable initialization signal is a Pulse Width Modulation (PWM) signal, a frame display duration is K times a period of the PWM signal, and K is any one of 6, 8, and 12.

9. The driving apparatus according to claim 6, wherein the duration of the first display period and the duration of the second display period are equal.

10. The drive device according to claim 6, wherein a ratio between a time length of the first drive period and a time length of the first holding period and a ratio between a time length of the second drive period and a time length of the second holding period are both preset integer values, and the preset integer value is 2 or 3.

11. The driving apparatus according to claim 6, wherein a time interval between a trigger timing of the second scan start signal and a trigger timing of the first scan start signal is one-half of a display time period of one frame.

12. A display device, comprising: a display panel and a driving device according to any one of claims 6 to 11, wherein the display panel includes: a first display area and a second display area, the first display area and the second display area respectively including: a plurality of gate lines.

13. The display device according to claim 12, wherein the first display region and the second display region respectively include: a pixel drive circuit, the pixel drive circuit comprising: oxide thin film transistors and low temperature polysilicon thin film transistors.

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