CN113315368A - High-speed LVDS interface circuit and chip - Google Patents

High-speed LVDS interface circuit and chip Download PDF

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CN113315368A
CN113315368A CN202110689664.3A CN202110689664A CN113315368A CN 113315368 A CN113315368 A CN 113315368A CN 202110689664 A CN202110689664 A CN 202110689664A CN 113315368 A CN113315368 A CN 113315368A
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CN113315368B (en
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王尧
杨格亮
吴迪
王楠
刘鹏
孙宇凯
廖春连
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CETC 54 Research Institute
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

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Abstract

本发明公开了一种高速LVDS接口电路及芯片，属于模拟集成电路技术领域。该芯片中的接口电路包括第一电荷泵电路、第二电荷泵电路、四象开关电路和共模反馈电路，此外，该芯片还采用了补偿结构。该电路采用共模反馈电路电路稳定输出共模电压，电荷泵电路在时钟信号跳变沿进行充放电来减小山升/下降时间，通过高频补偿电路来提升高速接口电路的性能。

Figure 202110689664

The invention discloses a high-speed LVDS interface circuit and a chip, which belong to the technical field of analog integrated circuits. The interface circuit in the chip includes a first charge pump circuit, a second charge pump circuit, a four-phase switch circuit and a common mode feedback circuit, in addition, the chip also adopts a compensation structure. The circuit uses the common mode feedback circuit to stabilize the output common mode voltage, the charge pump circuit charges and discharges at the transition edge of the clock signal to reduce the rise/fall time, and uses the high frequency compensation circuit to improve the performance of the high-speed interface circuit.

Figure 202110689664

Description

High-speed LVDS interface circuit and chip
Technical Field
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a high-speed LVDS interface circuit and a chip.
Background
LVDS (Low-Voltage Differential Signaling) interface circuits are widely used in clock circuits and high-speed digital signal systems. The specific application of the method is mainly embodied in the following two aspects:
first, a high-speed analog-to-digital converter requires a high-speed interface chip to output data. With the continuous improvement of the working frequency of the communication system and the continuous increase of the bandwidth, the requirement on the speed of the interface chip is higher and higher. Meanwhile, with the continuous breakthrough of digital signal processing technology, high-speed digital systems have come into operation. It is particularly important to design high speed interface circuits.
Second, in large-scale high-speed digital systems, a variety of abundant logic voltages are required to implement complex functions. Parasitic capacitance inevitably poses a serious problem for high-speed and high-signal-quality interface circuits. Therefore, the design of a high-speed and high-quality LVDS interface circuit has important significance.
Disclosure of Invention
In view of the above, the present invention provides a high-speed LVDS interface circuit and a chip, which can improve the working speed of the interface circuit by using a charge pump technology and a high-frequency compensation technology.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a high-speed LVDS interface circuit comprises a first charge pump circuit, a second charge pump circuit, a four-quadrant switch circuit and a common-mode feedback circuit; the four-quadrant switching circuit includes first to fourth transistors M1-M4The first charge pump circuit comprises a fifth transistor M and a sixth transistor M5、M6And a first capacitor C1The second charge pump circuit comprises a seventh transistor M and an eighth transistor M7、M8And a second capacitor C2The common mode feedback circuit comprises a first resistor R1A second resistor R2A third capacitor C3An operational amplifier OPA, a first current source I1And a second current source I2；
A first current source I1One end of the first, second, fifth and seventh crystals is connected with a voltage source, and the other end is connected with the first, second, fifth and seventh crystalsBody tube M1、M2、M5、M7Is connected to the source of (a); first transistor M1And the third transistor M3Is connected to the drain of the second transistor M2And the fourth transistor M4Is connected to the drain of the first transistor M1Source of and second transistor M2Is connected to the source of the third transistor M3And the fourth transistor M4Is connected to the source of (a); third transistor M3Is connected to the clock signal CLK, a fourth transistor M4The gate of (2) is connected with a reverse clock signal NCLK; first and third transistors M1、M3The nodes between the drains are connected to the first resistor R1And a first capacitor C1Is connected to one end of a second and a fourth transistor M2、M4The nodes between the drains are respectively connected with the second resistors R2And a second capacitor C2Is connected with one end of the connecting rod; a first resistor R1And the other end of the second resistor R2The other end of the voltage-sharing circuit is connected with a common-mode voltage VcmConnected, the forward input port of the operational amplifier OPA and the common-mode voltage VcmConnected to a negative input port and a third capacitor C3Is connected to a third capacitor C3Is connected to the output of the operational amplifier OPA and controls a second current source I2The magnitude of the current of (c); fifth and sixth transistors M5、M6Are connected to a clock signal CLK, a seventh and an eighth transistor M7、M8The grid of the grid is connected with and connected with a reverse clock signal; fifth and sixth transistors M5、M6And the drain electrodes of the first and second capacitors C1Is connected to the other end of the sixth transistor M6Is grounded, the fifth transistor M5Gate of and the first transistor M1The gate of (1) is connected; seventh and eighth transistors M7、M8And the drain electrodes of the first and second capacitors C2Is connected to the other end of the eighth transistor M8Is grounded, a seventh transistor M7And the second transistor M2The gate of (1) is connected; a first resistor R1Near the first capacitor C1One end of the positive voltage output port VOUTPTwo resistors R2Near the second capacitance C2Is a reverse voltage output port VOUTN.
A high-speed LVDS interface chip comprises the high-speed LVDS interface circuit and a packaging structure, wherein a forward voltage port corresponding to a forward voltage output port VOUTP and a reverse voltage port corresponding to a reverse voltage output port VOUTN are arranged outside the packaging structure, adjusting inductors Ind _ tune are arranged among the forward voltage output port and the forward voltage port and among the reverse voltage output port and the reverse voltage port, adjusting capacitors Ctune are arranged outside the forward voltage port and the reverse voltage port, and the adjusting inductors and the adjusting capacitors are used for performing high-frequency resonance compensation on a parasitic circuit generated by the packaging structure.
Compared with the prior art, the invention has the advantages that:
1) the traditional pre-emphasis technology needs an extra always-on current source to inject current so as to improve the interface speed. The invention adopts the charge pump technology, only charges and discharges the capacitor, and saves the power consumption.
2) The conventional interface circuit adopts miller compensation technology, and a capacitor exists in a current source path (actually, the current source is an alternating current path because the common-mode bandwidth of the circuit is low). The chip of the invention has a compensation structure, and the compensation structure has no parasitic capacitance in a signal/current source, and can improve the interface speed.
3) The compensation structure of the invention is a Q value compensation circuit, which can reduce the parasitic influence of a high-frequency chip and ensure the high-frequency performance of the interface.
4) Under the SMIC180nm process, the working speed of the chip can be improved to 2.2 GHz.
Drawings
Fig. 1 is a circuit schematic of an interface circuit of the present invention.
Fig. 2 is a circuit schematic diagram of a LVDS interface parasitic circuit.
Fig. 3 is a circuit schematic of the compensation structure in the chip of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, a high-speed LVDS interface circuit includes a first charge pump circuit, a second charge pump circuit, a four-quadrant switch circuit, and a common-mode feedback circuit; the four-quadrant switching circuit includes first to fourth transistors M1-M4The first charge pump circuit comprises a fifth transistor M and a sixth transistor M5、M6And a first capacitor C1The second charge pump circuit comprises a seventh transistor M and an eighth transistor M7、M8And a second capacitor C2The common mode feedback circuit comprises a first resistor R1A second resistor R2A third capacitor C3An operational amplifier OPA, a first current source I1And a second current source I2；
A first current source I1One end of the first transistor M is connected with a voltage source, and the other end is connected with the first, second, fifth and seventh transistors M1、M2、M5、M7Is connected to the source of (a); first transistor M1And the third transistor M3Is connected to the drain of the second transistor M2And the fourth transistor M4Is connected to the drain of the first transistor M1Source of and second transistor M2Is connected to the source of the third transistor M3And the fourth transistor M4Is connected to the source of (a); third transistor M3Is connected to the clock signal CLK, a fourth transistor M4The gate of (2) is connected with a reverse clock signal NCLK; first and third transistors M1、M3The nodes between the drains are connected to the first resistor R1And a first capacitor C1Is connected to one end of a second and a fourth transistor M2、M4The nodes between the drains are respectively connected with the second resistors R2And a second capacitor C2Is connected with one end of the connecting rod; a first resistor R1And the other end of the second resistor R2The other end of the voltage-sharing circuit is connected with a common-mode voltage VcmConnected, the forward input port of the operational amplifier OPA and the common-mode voltage VcmConnected to a negative input port and a third capacitor C3Is connected to a third capacitor C3Is connected to the output of the operational amplifier OPA and controlsA second current source I2The magnitude of the current of (c); fifth and sixth transistors M5、M6Are connected to a clock signal CLK, a seventh and an eighth transistor M7、M8The grid of the grid is connected with and connected with a reverse clock signal; fifth and sixth transistors M5、M6And the drain electrodes of the first and second capacitors C1Is connected to the other end of the sixth transistor M6Is grounded, the fifth transistor M5Gate of and the first transistor M1The gate of (1) is connected; seventh and eighth transistors M7、M8And the drain electrodes of the first and second capacitors C2Is connected to the other end of the eighth transistor M8Is grounded, a seventh transistor M7And the second transistor M2The gate of (1) is connected; a first resistor R1Near the first capacitor C1One end of the positive voltage output port VOUTP and a second resistor R2Near the second capacitance C2Is a reverse voltage output port VOUTN.
The circuit employs charge pump technology. When CLK is low, current passes through transistor M1To node VOUTP and thus through resistor R1(ii) a At this time M5Opening, C1The upper plate stores positive charges, the lower plate stores negative charges, and the positive charges of the lower plate flow to the resistor R1Increasing the flow through R1Instantaneous current, the rise/fall time of the output clock can be reduced.
Specifically, when the circuit starts to operate, V from the resistorCMPort to input port of amplifier, output port of amplifier through current source and transistor M3To the resistance VCMPorts, forming a common-mode negative feedback loop, the operational amplifier being virtually short, hence VCMThe voltage is equal to 1.25V.
When CLK is low, NCLK is high, M5On, M6C to1Upper pole plate passes through M5Charging, the lower polar plate is charged with equal amount of negative charges, and the positive charges flowing out of the lower polar plate are:
Q1(+)＝C1×U (1)
the positive charge flows through a resistor R1At the time from CLK low to CLK high, the charge is released as alpha Q1. α is a process-dependent coefficient.
M1、M4On, M2、M3Cut off, NCLK is high, C2The positive charge of the upper plate begins to pass through M8Relief, C2The lower plate starts to absorb positive charges (negative charges decrease). The following relationships are generally satisfied in the design:
C1＝C2 (2)
so that the absorbed charge is α Q during the period from CLK low to CLK high1. Assuming parasitic capacitance C exists at VOUTP nodegThe node voltage is from U1Jump to U2The jump time satisfies the following formula:
ΔT＝Cg(U1-U2)/I (3)
i is the current flowing into node VOUTP, and when no charge pump circuit is present, I is generally I1350 mA; when a charge pump circuit is present:
I＝0.35+2αQ1/T (4)
in the above equation, T is the period of the clock. As is apparent from this equation, with the charge pump technique, the current flowing into the load capacitance increases, and therefore, the output clock rise/fall Δ T decrease can be obtained from equation (3).
In addition, the common mode feedback circuit in the circuit adopts a single-stage capacitance compensation technology, only the dominant pole is pushed leftwards, and the compensation mode can reduce the load capacitance on the current source path, so that the working speed is improved.
A high-speed LVDS interface chip comprises the high-speed LVDS interface circuit and a packaging structure, wherein a forward voltage port corresponding to a forward voltage output port VOUTP and a reverse voltage port corresponding to a reverse voltage output port VOUTN are arranged outside the packaging structure.
The general chip needs to connect the PAD and the chip pin, bo, through the bonding wireThe bonding wire is equivalent to an inductor, and the chip pins and the pads are equivalent to capacitors. As shown in fig. 2, the signal flows out of the VOUTP interface, CgIs parasitic capacitance of PAD and metal line, Ind1 is parasitic inductance of bonding line, CloadIs the load capacitance and R is the load impedance. When the output clock signal jumps, the inductor and the capacitor are used as energy storage elements and can be charged and discharged to a certain degree, backflow is generated, the change of the clock signal is blocked, and the quality of the output signal is reduced. The parasitic circuit deteriorates signal rise and fall time at high frequency, and causes a series of problems such as signal overshoot.
Therefore, adjusting inductors Ind _ tune can be arranged between the forward voltage output port and the forward voltage port and between the reverse voltage output port and the reverse voltage port, adjusting capacitors Ctune can be arranged outside the forward voltage port and the reverse voltage port, and the parasitic circuit generated by the packaging structure is subjected to high-frequency resonance compensation by using the adjusting inductors and the adjusting capacitors.
As shown in fig. 3, the inductance L ═ C of Ind _ tune is obtained by the above compensation structuregAnd in the circuit:
C＝Cload+Cg (5)
from VOUTP, the output equivalent load is:
Figure BDA0003125717640000051
in the above formula L1Is the inductance value of Ind1, W represents the signal corner frequency, and j represents the imaginary number.
When R is relatively small, the above formula is equivalent to:
Figure BDA0003125717640000052
the resonant frequency and the Q value satisfy the following formula:
Figure BDA0003125717640000053
when the time domain signal is passed through the impedance represented by equation (7), there are:
Figure BDA0003125717640000054
in the above formula, T is 1/(W)0/2/pi)。
Usually, the Q value is 0.5, and the signal overshoot and rise/fall time are well balanced. Thus Q is 1/(W)0RC) is 0.5, when inductance value L of Ind _ tune is Cg，
The capacitance value of Ctune satisfies the following formula:
Figure BDA0003125717640000061
the circuit can obtain good high-frequency performance.

Claims (2)

1.一种高速LVDS接口电路，其特征在于，包括第一电荷泵电路、第二电荷泵电路、四象开关电路和共模反馈电路；所述四象开关电路包括第一至第四晶体管(M1-M4)，所述第一电荷泵电路包括第五、第六晶体管(M5、M6)以及第一电容(C1)，所述第二电荷泵电路包括第七、第八晶体管(M7、M8)以及第二电容(C2)，所述共模反馈电路包括第一电阻(R1)、第二电阻(R2)、第三电容(C3)、运算放大器(OPA)、第一电流源(I1)以及第二电流源(I2)；1. a high-speed LVDS interface circuit, is characterized in that, comprises the first charge pump circuit, the second charge pump circuit, the four-phase switch circuit and the common mode feedback circuit; Described four-phase switch circuit comprises the first to the fourth transistor ( M 1 -M 4 ), the first charge pump circuit includes fifth and sixth transistors (M 5 , M 6 ) and a first capacitor (C 1 ), and the second charge pump circuit includes seventh and eighth transistors transistors (M 7 , M 8 ) and a second capacitor (C 2 ), the common-mode feedback circuit includes a first resistor (R 1 ), a second resistor (R 2 ), a third capacitor (C 3 ), and an operational amplifier (OPA), a first current source (I 1 ), and a second current source (I 2 ); 第一电流源(I1)的一端与电压源连接，另一端与第一、第二、第五、第七晶体管(M1、M2、M5、M7)的源极连接；第一晶体管(M1)的漏极与第三晶体管(M3)的漏极连接，第二晶体管(M2)的漏极与第四晶体管(M4)的漏极连接，第一晶体管(M1)的源极与第二晶体管(M2)的源极连接，第三晶体管(M3)的源极与第四晶体管(M4)的源极连接；第三晶体管(M3)的栅极连接时钟信号(CLK)，第四晶体管(M4)的栅极连接反向时钟信号(NCLK)；第一、第三晶体管(M1、M3)漏极之间的节点分别与第一电阻(R1)和第一电容(C1)的一端连接，第二、第四晶体管(M2、M4)漏极之间的节点分别与第二电阻(R2)和第二电容(C2)的一端连接；第一电阻(R1)的另一端和第二电阻(R2)的另一端均与共模电压(Vcm)连接，运算放大器(OPA)的正向输入端口与共模电压(Vcm)连接，负向输入端口与第三电容(C3)的一端连接，第三电容(C3)的另一端与运算放大器(OPA)的输出端连接，并控制第二电流源(I2)的电流大小；第五、第六晶体管(M5、M6)的栅极相连并连接时钟信号(CLK)，第七、第八晶体管(M7、M8)的栅极相连并连接反向时钟信号；第五、第六晶体管(M5、M6)的漏极均与第一电容(C1)的另一端连接，第六晶体管(M6)的源极接地，第五晶体管(M5)的栅极与第一晶体管(M1)的栅极连接；第七、第八晶体管(M7、M8)的漏极均与第二电容(C2)的另一端连接，第八晶体管(M8)的源极接地，第七晶体管(M7)的栅极与第二晶体管(M2)的栅极连接；第一电阻(R1)的靠近第一电容(C1)的一端为正向电压输出端口(VOUTP)，第二电阻(R2)的靠近第二电容(C2)的一端为反向电压输出端口(VOUTN)。One end of the first current source (I 1 ) is connected to the voltage source, and the other end is connected to the sources of the first, second, fifth and seventh transistors (M 1 , M 2 , M 5 , M 7 ); the first The drain of the transistor (M1) is connected to the drain of the third transistor (M3), the drain of the second transistor ( M2 ) is connected to the drain of the fourth transistor (M4), the drain of the first transistor (M1 ) ) is connected to the source of the second transistor (M 2 ), the source of the third transistor (M 3 ) is connected to the source of the fourth transistor (M 4 ); the gate of the third transistor (M 3 ) The clock signal (CLK) is connected, and the gate of the fourth transistor (M 4 ) is connected to the reverse clock signal (NCLK); the nodes between the drains of the first and third transistors (M 1 , M 3 ) are respectively connected to the first resistor (R 1 ) is connected to one end of the first capacitor (C 1 ), and the nodes between the drains of the second and fourth transistors (M 2 , M 4 ) are respectively connected to the second resistor (R 2 ) and the second capacitor (C 2 ) is connected to one end; the other end of the first resistor (R 1 ) and the other end of the second resistor (R 2 ) are both connected to the common mode voltage (V cm ), and the forward input port of the operational amplifier (OPA) is connected to the common mode voltage (V cm ) is connected, the negative input port is connected to one end of the third capacitor (C 3 ), the other end of the third capacitor (C 3 ) is connected to the output end of the operational amplifier (OPA), and controls the second current source ( I 2 ) current size; the gates of the fifth and sixth transistors (M 5 , M 6 ) are connected and connected to the clock signal (CLK), and the gates of the seventh and eighth transistors (M 7 , M 8 ) are connected and connected Connect the reverse clock signal; the drains of the fifth and sixth transistors (M 5 , M 6 ) are both connected to the other end of the first capacitor (C 1 ), the source of the sixth transistor (M 6 ) is grounded, the fifth The gate of the transistor (M 5 ) is connected to the gate of the first transistor (M 1 ); the drains of the seventh and eighth transistors (M 7 , M 8 ) are connected to the other end of the second capacitor (C 2 ) , the source of the eighth transistor (M 8 ) is grounded, the gate of the seventh transistor (M 7 ) is connected to the gate of the second transistor (M 2 ); the first resistor (R 1 ) is close to the first capacitor (C One end of 1 ) is the forward voltage output port (VOUTP), and the end of the second resistor (R 2 ) close to the second capacitor (C 2 ) is the reverse voltage output port (VOUTN). 2.一种高速LVDS接口芯片，其特征在于，包括如权利要求1所述的高速LVDS接口电路以及封装结构，所述封装结构外设有对应于正向电压输出端口(VOUTP)的正向电压端口以及对应于反向电压输出端口(VOUTN)的反向电压端口，正向电压输出端口、正向电压端口之间以及反向电压输出端口、反向电压端口之间均设有调节电感(Ind_tune)，正向电压端口和反向电压端口外均设有调节电容(Ctune)，调节电感和调节电容用于对由封装结构所产生的寄生电路进行高频谐振补偿。2. A high-speed LVDS interface chip, characterized in that it comprises a high-speed LVDS interface circuit as claimed in claim 1 and a package structure, wherein the package structure is provided with a forward voltage corresponding to a forward voltage output port (VOUTP) outside the package structure. The port and the reverse voltage port corresponding to the reverse voltage output port (VOUTN), the forward voltage output port, between the forward voltage port and between the reverse voltage output port and the reverse voltage port are provided with adjustment inductance (Ind_tune ), an adjustment capacitor (Ctune) is provided outside the forward voltage port and the reverse voltage port, and the adjustment inductance and the adjustment capacitor are used to perform high-frequency resonance compensation for the parasitic circuit generated by the package structure.
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US7012450B1 (en) * 2003-12-15 2006-03-14 Decicon, Inc. Transmitter for low voltage differential signaling
CN106026757A (en) * 2016-05-17 2016-10-12 中国电子科技集团公司第二十四研究所 Differential charge pump
CN112968683A (en) * 2021-03-18 2021-06-15 中国电子科技集团公司第五十四研究所 High-speed multi-mode multi-channel LVCMOS interface circuit
CN215072151U (en) * 2021-06-22 2021-12-07 中国电子科技集团公司第五十四研究所 High-speed LVDS interface circuit and chip

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7012450B1 (en) * 2003-12-15 2006-03-14 Decicon, Inc. Transmitter for low voltage differential signaling
CN106026757A (en) * 2016-05-17 2016-10-12 中国电子科技集团公司第二十四研究所 Differential charge pump
CN112968683A (en) * 2021-03-18 2021-06-15 中国电子科技集团公司第五十四研究所 High-speed multi-mode multi-channel LVCMOS interface circuit
CN215072151U (en) * 2021-06-22 2021-12-07 中国电子科技集团公司第五十四研究所 High-speed LVDS interface circuit and chip

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