CN113178489B - Z is provided 2 -FET device, method for manufacturing the same, and semiconductor device - Google Patents

Z is provided 2 -FET device, method for manufacturing the same, and semiconductor device Download PDF

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Publication number
CN113178489B
CN113178489B CN202110232817.1A CN202110232817A CN113178489B CN 113178489 B CN113178489 B CN 113178489B CN 202110232817 A CN202110232817 A CN 202110232817A CN 113178489 B CN113178489 B CN 113178489B
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semiconductor
nano
fet device
device characterized
drain electrode
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CN113178489A (en
Inventor
张青竹
殷华湘
曹磊
张兆浩
田佳佳
顾杰
李俊杰
姚佳欣
李永亮
张永奎
吴振华
赵鸿滨
罗军
王文武
屠海令
叶甜春
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates

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Abstract

The invention relates to a Z 2 -FET device, method for manufacturing the same, semiconductor device, Z 2 -the FET device comprises: an SOI substrate; a nano-sheet stack portion provided on the SOI substrate to form a plurality of conductive channels; a surrounding grid surrounding the nano stack part; the nano-sheet stack portion includes; a stack of nanoplates and a support structure between adjacent nanoplates, the support structure being formed of a first semiconductor and the nanoplates being formed of a second semiconductor; the width of the second semiconductor nano-sheet is larger than that of the supporting structure; the two ends of the nano sheet stack part are provided with a source electrode and a drain electrode which are opposite in doping type; a non-gate region is disposed between the source and the surrounding gate. Will Z 2 The FET device working mechanism is combined with the novel Fishbone FET structure, so that the gate control range of the device can be improved, and meanwhile, the switching characteristic of the device is increased, and meanwhile, the working current is increased.

Description

Z is provided 2 -FET device, method for manufacturing the same, and semiconductor device
Technical Field
The invention relates to the field of semiconductors, in particular to a Z 2 -FET device, method of manufacturing the same, and a semiconductor device.
Background
With the continuous miniaturization of the feature size of the transistor, the chip integration level is improved, the short channel effect of the device is more obvious, and the research on the transistor with steep switching characteristics is beneficial to overcoming the switching limit of a standard MOSFET and realizing low Subthreshold Swing (SS). Currently, field Effect Diodes (FEDs) with two front gates exhibit significant switching and hysteresis, which can be used for electrostatic discharge (ESD) protection. Whereas a feedback field effect transistor (FB-FET) consisting of an injection barrier caused by the interaction between electrons and hole source-drain currents and by the trapping of surface charges in the gate dielectric layer has a smaller Subthreshold Slope (SS) and a higher on-current (I ON ). These transistor designs tend to improve the switching characteristics of the device. At the same time, this is Z 2 The design of the FET provides thought, Z, through long-term research and development 2 -FETs have application prospects in the ESD and memory fields.
Z 2 Forward and reverse sides of FET (Zero subthreshold swing and Zero impact ionization FET) devices analogous to FEDs and FB-FETsFeed, but does not require capture of surface charges and only one front gate is required, simplifying the device structure and its fabrication process. Z is Z 2 The FET layout is similar to an asymmetric Tunnel FET (TFET), with one injection barrier directly formed by the front gate (V G ) Controlled by a back gate (V) BG ) And (5) controlling. The device exhibits steep switching characteristics at low operating voltages and exhibits high switching characteristics at drain current-voltage (I D –V D ) Has larger controllable hysteresis. The injection barriers (Vn and Vp) for electrons and holes are controlled by the gate. Z is Z 2 The FET is not involved in impact ionization and channel doping.
As shown in FIG. 1, reference 1 (Wan J, royer C L, zassavsky A, et al A systematic study of the sharp-switching Z (2) -FET device From mechanism to modeling and compact memory applications [ J)]Solid State Electronics,2013,90 (dec.): 2-11.)) 2 -FET devices are fabricated on FD-SOI substrates, the devices having a silicon (Si) active layer and a Buried Oxide (BOX) layer. At L G In the region shown, the channel is undoped and partially covered by the gate, there being a remaining non-gated region L between the gate and the source IN 。Z 2 -FET source (S) and drain (D) having opposite doping types, the p-i-n junction of the device being forward biased. Wherein electron and hole barriers are formed by the front gate and the back gate, without requiring channel doping or surface charge.
Meanwhile, research progress of GAA stacked nanosheet FET has received extensive attention from academia and industry. The continuously updated preparation flow and key process, and the optimized device structure are the popular research direction of the novel CMOS device. The novel Fishbone FET can greatly increase the driving current under the condition of not affecting the subthreshold characteristic of the device basically by adding a supporting structure to the stacked nano-sheet device; the source drain stress can be maintained, and the mobility of the device is improved; complex inner side wall technology can be omitted, and the preparation complexity and the electric characteristic fluctuation of the device are reduced; meanwhile, the heat dissipation of the conducting channel can be increased through the connection with the substrate, so that the self-heating effect is improved; the threshold value of the device can be adjusted by adjusting the width and the height of the supporting structure, so that the filling requirements of the high-K dielectric layer and the metal grid electrode are reduced in the process, and the multi-threshold value adjustment and control can be realized.
Will Z 2 The FET device working mechanism is combined with the novel Fishbone FET structure, so that the barrier of electrons can be effectively controlled by utilizing the front grid structure controlled by multiple grids, the grid control range of the device is improved, meanwhile, the working current of the device can be continuously improved while the switching characteristic of the device is increased, and on the other hand, the driving performance of the device is improved through the GeSi/Si heterojunction and the laminated structure. Therefore, the novel Fishbone device structure is combined with Z 2 The characteristics of the FET structure combine to be a design direction with challenges and development advantages. Next, a device structure and process flow combining the two designs is presented.
Disclosure of Invention
Aiming at the technical problems, the invention provides a Z 2 -FET device, method of manufacturing the same, and a semiconductor device.
The invention adopts the following technical scheme:
z 2 -FET device characterized by: comprising the following steps:
an SOI substrate;
a nano-sheet stack portion provided on the SOI substrate to form a plurality of conductive channels;
a surrounding grid surrounding the nano stack part;
the nano-sheet stack portion includes;
a stack of nanoplates and a support structure between adjacent nanoplates, the support structure being formed of a first semiconductor and the nanoplates being formed of a second semiconductor;
the width of the second semiconductor nano-sheet is larger than that of the supporting structure;
the two ends of the nano sheet stack part are provided with a source electrode and a drain electrode which are opposite in doping type;
a non-gate region is disposed between the source and the surrounding gate.
At the same time, the invention also discloses a Z 2 -a method of manufacturing a FET device characterized by: the method comprises the following steps:
providing an SOI substrate;
epitaxially growing a superlattice laminate of a first semiconductor and a second semiconductor on a substrate;
etching the superlattice laminate to form a plurality of fins;
forming a dummy gate (dummy gate) on the fin;
respectively arranging second side walls on two sides of the dummy gate along the fin line direction, wherein the thickness of the second side wall of the source electrode end is larger than that of the second side wall of the drain electrode end;
epitaxially growing a source electrode and a drain electrode with opposite doping types at two ends of the fin;
selectively removing superlattice laminates of the first semiconductor and the second semiconductor on the fins to form nano stack parts of a plurality of conducting channels, so that the nano stack parts comprise nano sheets formed by the second semiconductor and supporting structures formed by the first semiconductor, and the width of each nano sheet is larger than that of each supporting structure, thereby realizing the release of the channels of the nano sheets;
a surrounding grid is formed around the nano stack part.
Compared with the prior art, the invention has the following beneficial technical effects:
the preparation method based on the novel structure Fishbone FET designs the device structure of source-drain doping type opposite to that of source-end underlap as Z 2 -FET, P-Z 2 -FETs employ SiGe nanoplates and Si support structures as conductive channels; n-type Z 2 The FET employs Si nanoplates and SiGe support structures as the conductive channels, which are designed to facilitate an increase in Z 2 -a drive current of the FET; the design of the combination of the nano-sheet and the supporting structure is beneficial to increasing the control of the front grid electrode on the injection barrier, and meanwhile, the design of the ring grid structure is beneficial to promoting the size reduction of the device, improving the grid control capability and the large-opening-ratio characteristic, so that the device structure has better electrical characteristics in nano-size.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures.
FIG. 1 is a prior art Z 2 -a schematic diagram of a FET device.
Fig. 2 is a schematic diagram of the growth of a superlattice on a substrate in accordance with the invention.
Fig. 3 is a schematic view of the formation of a first sidewall on a superlattice in accordance with the invention.
Fig. 4 is a schematic diagram of a fin formed by etching a superlattice structure in accordance with the invention.
Fig. 5 is a schematic diagram of a fin with a first sidewall removed according to the present invention.
Fig. 6 is a schematic diagram of forming a dummy gate over a fin in accordance with the present invention.
Fig. 7 is a schematic top view of the present invention, in which second side walls are disposed on two sides of a dummy gate.
Figure 8 is a schematic cross-sectional view of the second sidewall formed in accordance with the present invention along the X-direction.
Fig. 9 is a schematic cross-sectional view of the source drain etching along the X direction according to the present invention.
Fig. 10 is a schematic cross-sectional view of an epitaxially grown source/drain and an deposited spacer along the X-direction according to the present invention.
Fig. 11 is a schematic cross-sectional view along the X-direction of the dummy gate removal process according to the present invention.
Fig. 12 is a schematic longitudinal cross-sectional view of the P-type device nanochannel release of the present invention along the Y-direction.
Fig. 13 is a schematic longitudinal cross-sectional view of the N-type device nanochannel release of the present invention along the Y-direction.
Fig. 14 and A, B are schematic cross-sectional views of the P, N device of the present invention along the Y-direction and fig. 14C is a schematic cross-sectional view along the X-direction, respectively.
FIG. 15 and A, B are respectively the P type Z of the invention 2 -FET device cross-section schematic along Y, X direction.
Fig. 16 and A, B are respectively the N type Z of the invention 2 -FET device cross-section schematic along Y, X direction.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood that the description is only illustrative and is not intended to limit the scope of the invention. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present invention.
Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present invention, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
In this embodiment, a method for manufacturing Z is provided 2 -a method of FET devices. In combination with FIGS. 1-16, Z of the present invention 2 -schematic process for manufacturing FET device, Z 2 The FET device 100 process includes:
as depicted in fig. 1, a substrate 101 is provided, the substrate 101 being part of a semiconductor wafer suitable for forming one or more IC devices, the substrate 101 in one embodiment employing silicon-on-insulator (silicon on insulator). The SOI structure includes a Si semiconductor layer 101a made of silicon, the Si semiconductor layer 101a being located on an insulating layer called a buried oxide layer (BOX) 101b, the buried oxide layer 101b being located on a Si semiconductor support layer 101c made of silicon.
Silicon dioxide (SiO) on the surface of the Si semiconductor layer 101a is removed 2 ) Thereafter, a stack of superlattice structures of the first semiconductor 201 '/the second semiconductor 202' is epitaxially grown for a plurality of cycles; each layer of semiconductor in the superlattice structure has a thickness of less than 30nm, and the thickness of the final semiconductor layer is directly determinedThe height of the nanoplate channels and the electrostatic properties.
In one embodiment, for P-type Z 2 The FET device, the first semiconductor 201 '/second semiconductor 202' superlattice is a Si/SiGe stack, and thus the Si/SiGe stack continues to be grown on the upper surface of the Si semiconductor layer 101a, as depicted in fig. 2. In another embodiment, for N-type Z 2 The FET device, the first semiconductor 201 '/second semiconductor 202' superlattice is a SiGe/Si stack, and thus the SiGe/Si stack continues to be grown on the upper surface of the Si semiconductor layer 101a, as shown in fig. 2.
As shown in fig. 3, a self-aligned sidewall transfer (SIT) process is used to form an array of nano-scale first sidewalls 301, the first sidewalls 301 being silicon nitride (SiN) X ) The specific forming process is as follows: a sacrificial layer 302, which may be polysilicon (PolySi, p-si) or amorphous silicon (a-si) 302, is covered on the superlattice laminate, and a portion of the sacrificial layer 302 is etched to form silicon nitride (SiN) x ) The layers are then anisotropically etched to etch away the remaining sacrificial layer 302, leaving it only on the superlattice laminate for a plurality of periodic silicon nitride (SiN) x ) A first side wall (spacers) 301, the silicon nitride (SiN x ) The first sidewall 301 functions as a Hard Mask (Hard Mask) in photolithography.
Fig. 4 is a diagram of an epitaxially produced superlattice laminate formed into a plurality of periodically distributed fins by an etching process. And etching by taking the first side wall 301 as a mask to form the fin with the superlattice laminated structure. The upper part of the fin is a conductive channel region formed by superlattice lamination, the lower part of the fin is connected with the buried oxide layer 101b, and then the first side wall 301 is removed to form the fin as shown in fig. 4. The etching process is a dry etching or a wet etching, and in one embodiment, reactive ion etching may be used. The fins will be used to form one or more n-type field effect transistors and/or horizontal nanoplates of p-type field effect transistors. Although one fin is shown in fig. 4, it should be understood that any suitable number and configuration of fins may be used. The fin has a height of about 200nm and a width of about 30nm. The direction is defined herein, the X direction is the fin line direction, and the Y direction is the method of perpendicular fin line.
Fig. 5 illustrates the removal of the fins of the first sidewall 301 using an etching process.
As shown in fig. 6-7, a dummy gate 106 is formed on the exposed fin in a direction perpendicular to the fin line (i.e., Y direction), and may be formed by thermal oxidation, chemical vapor deposition, sputtering (sputtering), or the like. The dummy gate spans the superlattice stack above the fin, and the plurality of dummy gates are periodically distributed along the fin line. The material used for the dummy gate may be polysilicon (PolySi, p-si) or amorphous silicon (a-si).
As shown in fig. 8, silicon nitride (SiN) is respectively provided on both sides of the dummy gate in the fin line direction (i.e., X direction) x ) The thickness of the second sidewall 107a near the source electrode in the X direction is greater than the thickness of the second sidewall 107b near the drain electrode.
As shown in fig. 9-10, the second side walls 107a, 107b and the dummy gate 106 are used as masks to perform source-drain etching on the superlattice stack, and the cleaned space is used for epitaxially growing the source electrode 108a and the drain electrode 108b. The source/drain regions may be formed using suitable methods such as metal organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth (selective epitaxial growth, SEG), the like, or combinations of the foregoing. For the P-type Z of the Si/SiGe stack grown on the upper surface of the Si semiconductor layer 101a 2 The FET device, source 108a and drain 108B, respectively, employ SiGe heavily doped boron (B) (SiGe: B), siGe heavily doped phosphorus (P) (SiGe: P). For N-type Z of the SiGe/Si stack grown on the upper surface of the Si semiconductor layer 101a 2 The FET device, source 108a and drain 108B, employs Si heavily doped boron (B) (Si: B), si heavily doped phosphorus (P) (Si: P), respectively. The height of the source 108a and drain 108b is level with the height of the superlattice stack.
Next, as shown in fig. 10, spacers 109 are deposited on the source and drain electrodes 108a and 108b, respectively, to prevent the gate electrode 105 from being shorted to the source and drain electrodes 108a and 108b in the subsequent step, and the spacers 109 are subjected to chemical mechanical polishing to planarize them.
As shown in fig. 11, the dummy gate 106 formed of the foregoing polysilicon (PolySi, p-si) or amorphous silicon (a-si) is etched away, that is, the dummy gate 106 is removed, by an etching process.
As shown in fig. 12-13, selective etchingThe sacrificial layer in the superlattice stack is etched to perform a nano-sheet (nanosheet) channel release. The exposed conductive channel region of the fin is treated to remove most of each first semiconductor layer 201', wherein the first semiconductor layer 201' is a sacrificial layer, and the remaining first semiconductor layer 201' forms a supporting structure 201 to connect the adjacent second semiconductor formed nano-sheets 202. Width W of nanosheet 202 NS In the range of 5-50nm, thickness T NS In the range of 3-20nm, the height H of the support structure 201 SC In the range of 5-30nm, width W SC In the range of 3-40nm.
Referring to FIG. 12, for a PMOS embodiment in which a Si/SiGe superlattice stack is grown on the upper surface of Si semiconductor layer 101a, the sacrificial layer is a Si layer, a selective removal of a substantial portion of the Si layer is performed, the SiGe layer is retained, the remaining Si layer is a support structure for an adjacent SiGe layer, and is located at an intermediate position between adjacent SiGe layers to form a stacked device in which the SiGe horizontal stack+Si support structure is periodic, the width W of the nanoplatelets SiGe NS Width W greater than support structure Si SC The fish bone shaped device is seen in the X direction. An etchant that selectively etches Si at a faster rate relative to SiGe may be used in the selective removal process. In one embodiment, a conventional wet process isotropically etching the sacrificial layer effects nanochannel release, thereby forming a conducting channel in which the nanoplatelets and support structure are combined. The Si semiconductor 101a is etched with the underlying Si layer 201' in the superlattice stack to connect the support structure 201 with the buried oxide layer 101 b.
Referring to FIG. 13, for an NMOS embodiment in which a SiGe/Si superlattice stack is grown on the top surface of Si semiconductor layer 101a, the sacrificial layer is a SiGe layer, a selectively removed portion of the SiGe layer remains, the remaining SiGe layer is a support structure for an adjacent Si layer, and is located at an intermediate position between the adjacent Si layers to form a device in which the Si horizontal stack +SiGe support structure is a periodic stack, the width W of the nanoplatelets Si NS Greater than the width W of the support structure SiGe SC The fish bone shaped device is seen in the X direction. An etchant that selectively etches SiGe at a faster rate relative to Si may be used in the selective removal process. In one embodiment, a conventional wet process, all directionalThe sacrificial layer is etched to release the nano-channel, thereby forming a conductive channel in which the nano-sheet and the support structure are combined. The Si semiconductor 101a is formed such that the nano-sheet 202 is connected to the buried oxide layer 101b,
in one embodiment, the nanochannel release is achieved using an Atomic Layer Etching (ALE) process for precise control of the width of the support structure.
As shown in fig. 12-13, a portion of the support structure 201 formed by the first semiconductor layer and the nanolayer formed by the second semiconductor layer 202 are selectively removed to form a nanostack 102.
Next, as shown in fig. 14, a high-K dielectric layer 104 is deposited such that the high-K dielectric layer 104 surrounds the surface of the nano-stack 102 and covers the isolation layer and the silicon nitride (SiN) x ) Sidewall surface 107. The high-K dielectric layer may have a dielectric constant above about 7.0, and may be HfO 2 Or Al 2 O 3 。
Next, as shown in fig. 15-16, a metal gate 105 is deposited outside the space cleaned by the dummy gate 106 and the high K dielectric layer 104, and chemical mechanical polishing is performed on the metal gate 105 to planarize the metal gate. The metal gate 105 may have a multi-layered structure, and the metal gate 105 may employ metal aluminum (Al) or tungsten (W). The metal-containing gate is formed by chemical vapor deposition, physical vapor deposition, and the like. As shown in fig. 15-16, the metal gate fills the space after the dummy gate 106 is cleaned.
In one embodiment, the high-K dielectric layer 104 and the metal gate 105 are deposited layer by layer using an Atomic Layer Deposition (ALD) process, including an interfacial oxide layer (IL), a gate dielectric HfO 2 Barrier layer TiN/TaN, and gate metal (NMOS: tiAlC; PMOS: tiN), forming a vertical stack of horizontal multilayer nanoplatelets 202 and support structure 201.
The above is to prepare the complete Z 2 Process flow of FET forming Z as shown in fig. 13 2 -FET devices. It follows that the presence of the support structure simplifies the process of filling the high K dielectric and gate metal between the nanoplates and that the formation of bottom parasitic channels can be suppressed by the support structure portion.
To this end, a Z is provided 2 FET device structure, e.gAs described in FIGS. 12-13, 15-16, Z 2 The FET device 100 comprises: which includes a substrate 101 that is a silicon-on-insulator (SOI), and a stack 102 formed by stacking a support structure 201 formed of a first semiconductor and a nano-sheet 202 formed of a second semiconductor on a Si semiconductor upper layer 101 on the substrate 101. Width W of nanosheet 202 NS In the range of 5-50nm, thickness T NS In the range of 3-20nm, the height H of the support structure 201 SC In the range of 5-30nm, width W SC In the range of 3-40nm.
For P-type Z 2 FET device, the supporting structure of adjacent SiGe nano-sheets is a Si layer, si is positioned at the middle position between adjacent SiGe nano-sheets, a device is formed, the SiGe horizontal nano-sheets and the Si supporting structure are stacked periodically, and the width W of the supporting structure Si SC Less than the width W of the nanoplatelet SiGe NS The fish bone shaped device is seen in the direction along the fin line.
For N-type Z 2 FET device, the supporting structure of adjacent Si nano-sheets is a SiGe layer, siGe is positioned at the middle position between the adjacent Si nano-sheets, the Si horizontal nano-sheets and SiGe supporting structure are formed into a periodical stacked device, and the width W of the supporting structure SiGe SC Width W smaller than the nanoplatelets Si NS The fish bone shaped device is seen in the direction along the fin line.
A surrounding gate surrounding the nano-stack 102; the surrounding gate comprises, from inside to outside, a high-K dielectric layer 104 and a metal gate 105. A high K dielectric layer surrounding the surface of the nano-stack 102 may have a dielectric constant above about 7.0, and may be HfO 2 Or Al 2 O 3 。
The metal gate 105 is located outside the high-K dielectric layer 204, the metal gate 105 may have a multi-layer structure, and the metal gate 105 may be made of aluminum (Al) or tungsten (W).
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
the preparation method based on the novel structure Fishbone FET designs the device structure of source-drain doping type opposite to that of source-end underlap as Z 2 -FET, P-Z 2 -FETs employ SiGe nanoplates and Si support structures as conductive channels; n-type Z 2 -FET useSi nanoplatelets and SiGe support structure as conductive channels, facilitating Z increase 2 -a drive current of the FET; the combined design of the nano-sheets and the supporting structure is beneficial to increasing the control of the front grid electrode on the injection barrier, and the invention discloses a Z combined with the vertically stacked multilayer horizontal nano-sheets and the supporting structure 2 -FET new device structure.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present invention are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.

Claims (25)

1. Z is provided 2 -FET device characterized by: comprising the following steps:
an SOI substrate;
a nano-sheet stack portion provided on the SOI substrate to form a plurality of conductive channels;
a surrounding grid surrounding the nano stack part;
the nano-sheet stack portion includes;
a stack of nanoplates and a support structure between adjacent nanoplates, the support structure being formed of a first semiconductor and the nanoplates being formed of a second semiconductor;
the width of the second semiconductor nano-sheet is larger than that of the supporting structure;
the two ends of the nano sheet stack part are provided with a source electrode and a drain electrode which are opposite in doping type;
a non-gate region is disposed between the source and the surrounding gate.
2. Z according to claim 1 2 -FET device characterized by: the first semiconductor is Si and the second semiconductor is SiGe.
3. Z according to claim 1 2 -FET device characterized by: the first semiconductor is SiGe and the second semiconductor is Si.
4. Z according to claim 2 2 -FET device characterized by: the source electrode material is SiGe, the drain electrode material is SiGe and the drain electrode material is P.
5. A Z according to claim 3 2 -FET device characterized by: the source electrode material is Si and the drain electrode material is Si and P.
6. Z according to claim 1 2 -FET device characterized by: the grid electrode sequentially comprises a high-K dielectric layer and a metal grid from inside to outside.
7. Z according to claim 1 2 -FET device characterized by: the width of the nano-sheet is 5-50nm, and the thickness is 3-20nm.
8. Z according to claim 1 2 -FET device characterized by: the height of the supporting structure is 5-30nm, and the width is 3-40nm.
9. Z according to claim 1 2 -FET device characterized by: and isolation layers are respectively arranged on the source electrode and the drain electrode.
10. Z according to claim 1 2 -FET device characterized by: the conductive channel length ranges from 10-200nm.
11. Z according to claim 1 2 -FET device characterized by: the length of the non-gate control region ranges from 10 nm to 200nm.
12. Z according to claim 6 2 -FET device characterized by: the high-k dielectric layer is HfO 2 Or Al 2 O 3 。
13. Z according to claim 6 2 -FET device characterized by: the metal gate NMOS is a TiN/TiAlC/TiN/W lamination, and the PMOS is a TiN/TaN/TiN/W lamination.
14. Z is provided 2 -a method of manufacturing a FET device characterized by: the method comprises the following steps:
providing an SOI substrate;
epitaxially growing a superlattice laminate of a first semiconductor and a second semiconductor on a substrate;
etching the superlattice laminate to form a plurality of fins;
forming a dummy gate on the fin;
respectively arranging second side walls on two sides of the dummy gate along the fin line direction, wherein the thickness of the second side wall of the source electrode end is larger than that of the second side wall of the drain electrode end;
epitaxially growing a source electrode and a drain electrode with opposite doping types at two ends of the fin;
selectively removing superlattice laminates of the first semiconductor and the second semiconductor on the fins to form nano stack parts of a plurality of conducting channels, so that the nano stack parts comprise nano sheets formed by the second semiconductor and supporting structures formed by the first semiconductor, and the width of each nano sheet is larger than that of each supporting structure, thereby realizing the release of the channels of the nano sheets;
a surrounding grid is formed around the nano stack part.
15. The method according to claim 14, wherein: the step of forming the plurality of fins is specifically: a first side wall is arranged on the superlattice lamination; and etching the superlattice laminate by taking the first side wall as a mask to form a plurality of fins.
16. The method according to claim 15, wherein: the source electrode and the drain electrode with opposite doping types are epitaxially grown at the two ends of the fin, specifically: etching the superlattice laminate by taking the second side wall and the dummy gate as masks to form a source electrode and drain electrode growth space; and epitaxially growing a source electrode and a drain electrode with opposite doping types in the growth space, and respectively depositing isolation layers on the source electrode and the drain electrode.
17. The method according to claim 16, wherein: the step of forming the surrounding grid electrode specifically comprises the following steps: after the isolation layer is deposited, the dummy gate is etched and cleaned, and after the release of the nano sheet channel is realized, the gate is deposited at the original dummy gate position.
18. The method according to claim 14, wherein: the first semiconductor is Si and the second semiconductor is SiGe.
19. The method according to claim 14, wherein: the first semiconductor is SiGe and the second semiconductor is Si.
20. The method according to claim 18, wherein: the source electrode material is SiGe, the drain electrode material is SiGe and the drain electrode material is P.
21. The method according to claim 19, wherein: the source electrode material is Si and the drain electrode material is Si and P.
22. The method according to claim 17, wherein: the grid electrode sequentially comprises a high-K dielectric layer and a metal grid from inside to outside.
23. The method according to claim 14, wherein: the width of the nano-sheet is 5-50nm, and the thickness is 3-20nm.
24. The method according to claim 14, wherein: the height of the supporting structure is 5-30nm, and the width is 3-40nm.
25. A semiconductor device comprising a Z as claimed in any one of claims 1 to 13 2 -FET devices.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110504325A (en) * 2019-08-29 2019-11-26 上海华力微电子有限公司 A new gate-controlled P-i-N diode ESD device and its realization method
CN110634955A (en) * 2019-08-21 2019-12-31 复旦大学 Novel Semiconductor Field Effect Positive Feedback Transistor and Method Based on Bulk Silicon Substrate

Family Cites Families (3)

* Cited by examiner, † Cited by third party
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US10297586B2 (en) * 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
FR3080950B1 (en) * 2018-05-04 2023-04-14 St Microelectronics Sa Z2-FET TYPE STRUCTURE
US10832907B2 (en) * 2019-02-15 2020-11-10 International Business Machines Corporation Gate-all-around field-effect transistor devices having source/drain extension contacts to channel layers for reduced parasitic resistance

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110634955A (en) * 2019-08-21 2019-12-31 复旦大学 Novel Semiconductor Field Effect Positive Feedback Transistor and Method Based on Bulk Silicon Substrate
CN110504325A (en) * 2019-08-29 2019-11-26 上海华力微电子有限公司 A new gate-controlled P-i-N diode ESD device and its realization method

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