CN113066422B - Scanning and lighting driving circuit, scanning and lighting driving system, display panel - Google Patents

Abstract

The present application provides a scanning and light-emitting driving circuit, a scanning and light-emitting driving circuit, and a scanning and light-emitting driving circuit with a small volume and low cost, and the display panel provided by the present application including the foregoing scanning and light-emitting driving circuit satisfies the design of narrow frame and high screen ratio need. The scanning and light-emitting driving circuit includes a first control circuit, a second control circuit, a scanning driving output circuit and a light-emitting driving output circuit. The first control circuit is electrically connected to the scan drive output circuit and the light emitting drive output circuit, and is used for controlling the scan drive output circuit to output a scan signal during a data writing period in one scan cycle. The second control circuit is electrically connected to the light-emitting driving output circuit, and is used for controlling the light-emitting driving output circuit to output a light-emitting signal during the light-emitting period in the scanning period.

Description

Scanning and lighting driving circuit, scanning and lighting driving system, display panel

technical field

The present application relates to the technical field of image display, and in particular, to the technical field of scanning and light-emitting driving circuits, scanning and light-emitting driving systems, and display panels.

Background technique

During the image display process of the self-luminous display panel, the scan driver circuit provided in the non-display area needs to provide scan signals and light-emitting signals in conjunction with the data driver circuit to provide image data signals to drive the pixel array provided in the image display area to perform image display. In recent years, in order to improve the integration of display panels, gate scanning driving circuits, light-emitting scanning driving circuits and pixel arrays have been fabricated on an array substrate, also known as a gate driving array substrate (GOA, Gateon Array) and a light-emitting array ( EOA, Emissionon Array) circuit.

Each scan driving circuit includes a plurality of scanning and light-emitting driving circuits, which are usually designed in a cascaded form to sequentially output the shifted scan signals to the pixel array. Wherein, each scan driving circuit includes a GOA circuit and an EOA circuit that are independent of each other. As a result, the existing scan driving circuit has many electronic components and a large volume, so that the area of the non-display area cannot be reduced, resulting in a small screen-to-body ratio of the display panel and unable to meet the requirement of a narrow frame.

SUMMARY OF THE INVENTION

In the embodiments of the present application, a scanning and lighting driving circuit and a scanning and lighting driving system with fewer electronic components and a smaller volume are provided, so that the display panel including the aforementioned lighting driving circuit can meet the requirements of narrow frame and high screen ratio. design requirements.

In the first aspect, in a possible implementation manner, the scanning and lighting driving circuit includes a first control circuit, a second control circuit, a scanning driving output circuit and a lighting driving output circuit. The first control circuit is electrically connected to the scan drive output circuit and the light-emitting drive output circuit, and is used for controlling the scan drive output circuit to output a scan signal during the data writing time period in one scan cycle, and the scan signal uses The image data is received in the control pixel unit. The second control circuit is electrically connected to the light-emitting drive output circuit, and is used for controlling the light-emitting drive output circuit to output a light-emitting signal during the light-emitting period in the scan period, and the light-emitting signal is used to control the pixel unit The time to display the image data.

The scanning and light-emitting driving circuit cooperates with the second control circuit through the first control circuit, and controls the scanning driving circuit to output the scanning signal and the light-emitting driving circuit to output the light-emitting signal in different time periods. That is to say, in the scanning and light-emitting driving circuit, by sharing the first control circuit and the second control circuit, the same circuit is used to output the scanning signal and the light-emitting signal in a time-sharing manner, thereby effectively reducing the electronic components in the scanning and light-emitting driving circuit. The number, volume, and occupied area provide a greater possibility of reducing the area of the area where the scanning and light-emitting driving circuits are provided.

In a possible implementation manner, the first control circuit is electrically connected to the scan driver output circuit through a pull-down node; during the data writing period, the first control circuit receives a first clock signal, and The potential of the pull-down node is adjusted according to the first clock signal. The scan driver output circuit receives a pre-start scan signal and a second clock signal under the control of the potential of the pull-down node, and outputs the scan signal according to the pre-start scan signal and the second clock signal. The second control circuit is electrically connected to the light-emitting driving output circuit through the pull-up node, and during the light-emitting period, the second control circuit receives a third clock signal, and according to the third clock signal Adjust the potential of the pull-up node. During the light-emitting period, the light-emitting drive output circuit outputs a first reference voltage in the light-emitting signal under the control of the potential of the pull-up node, and the first reference voltage is used to control the display of the pixel unit the time of the image data.

Specifically, the first control circuit is also electrically connected to the light-emitting driving output circuit through a pull-up node; during the data writing period, the first control circuit receives a first clock signal, and according to the The first clock signal adjusts the potential of the pull-up node. During the data writing period, the light-emitting drive output circuit receives a second clock signal under the control of the potential of the pull-up node, and outputs a second reference voltage in the light-emitting signal according to the second clock signal , the second reference voltage is used to control the pixel unit to stop displaying the image data.

Specifically, the second control circuit is also electrically connected to the scan driver output circuit through the pull-down node; during the light-emitting period, the second control circuit receives the third clock signal and generates a clock signal according to the The third clock signal adjusts the potential of the pull-down node. During the light-emitting period, the scan drive output circuit stops outputting the scan signal under the control of the potential of the pull-down node.

In the foregoing implementation manner, the first control circuit and the second control circuit control the voltages of the pull-up node and the pull-down node, so that the scan driver circuit input and the light-emitting driver circuit accurately output the scan signal light-emitting signal in different time periods.

In a possible implementation manner, when the voltage of the pull-up node is the second potential, the first control circuit controls the voltage of the pull-down node to be the first potential. When the voltage of the pull-up node is at the first potential, the pull-down node is controlled to be at the second potential by a first inverting circuit connected between the pull-up node and the pull-down node. Through the setting of the first inverting circuit, the pull-down node can be accurately controlled to be at the first potential when the pull-up node is at the first potential, thereby ensuring that the pull-down node can be accurately maintained at the second potential without the first control circuit during the period when the pull-up node is at the first potential, so that the pull-down node can be accurately maintained at the second potential. The control for the first control circuit is simpler.

In a possible implementation manner, the light-emitting drive output circuit includes a light-emitting pull-up output circuit and a light-emitting pull-down output circuit. The control terminal of the light-emitting pull-up output circuit is electrically connected to the pull-up node, the input terminal is electrically connected to the first reference voltage terminal, and the first reference voltage terminal is used for providing the first reference voltage, The output end of the light-emitting pull-up output circuit is used for outputting the light-emitting signal. During the light-emitting period, under the control of the potential of the pull-up node, the output terminal of the light-emitting pull-up output circuit outputs the first reference voltage. The control terminal of the light-emitting pull-down output circuit is electrically connected to the pull-down node, and the input terminal is electrically connected to a second reference voltage terminal, and the second reference voltage terminal is used for providing the second reference voltage. During the data writing period, under the control of the potential of the pull-down node, the output end of the light-emitting pull-down output circuit outputs the second reference voltage, and the light-emitting signal includes the first reference voltage and the the second reference voltage.

In the light-emitting drive output circuit, the light-emitting pull-up output circuit and the light-emitting pull-down output circuit respectively output different reference voltages in different time periods under the control of the voltage of the pull-up node and the pull-down node, so that the light-emitting signal can be accurately output in the data writing time period. The pixel unit is controlled to receive the voltage of the image data, and the pixel unit is controlled to stop receiving the voltage of the image data in the output of the light-emitting signal during the light-emitting period.

In a possible implementation manner, the scan driver output circuit includes a scan pull-up output circuit and a scan pull-down output circuit. Wherein, the control terminal of the scan pull-up output circuit is electrically connected to the pull-up node, and the input terminal is electrically connected to the second reference voltage terminal. During the light-emitting period, under the control of the potential of the pull-up node, the output terminal of the scan pull-up output circuit outputs a fourth reference voltage, and the fourth reference voltage is used to control the pixel unit to stop receiving the image data. The control terminal of the scan pull-down output circuit is electrically connected to the pull-down node, the input terminal is electrically connected to the second clock terminal for receiving the second clock signal, and the output terminal is electrically connected to the scan signal output terminal. During the data writing period, under the control of the potential of the pull-down node, the output terminal of the scan pull-up output circuit outputs the third reference voltage, and the third reference voltage is used to control the pixel The unit receives the image data, and the scan signal includes the third reference voltage and the fourth reference voltage.

In the scan drive output circuit, the scan pull-up output circuit and the scan pull-down output circuit output different reference voltages in different time periods under the control of the voltage of the pull-up node and the pull-down node respectively, so as to accurately output the scan signal in the data writing time period The pixel unit is controlled to receive the voltage of the image data, and the pixel unit is controlled to stop receiving the voltage of the image data in the output scan signal during the light-emitting period.

In a possible implementation manner, the scanning and light-emitting driving circuit further includes a pulse width control circuit, and the pulse width control circuit is electrically connected to the light-emitting driving output circuit for controlling the light-emitting in the light-emitting signal. The pull-up output unit outputs the frequency of the first reference voltage and controls the light-emitting pull-down output unit to output the frequency of the second reference voltage, and the first reference voltage and the second reference voltage output the same frequency and The number of times the first reference voltage is output in the light-emitting period is greater than one.

During the light-emitting period, the duty cycle of the light-emitting signal can be flexibly adjusted at any time, instead of continuously driving the pixel unit for display at the same voltage (duty cycle is 100%), then, during the light-emitting display period of the pixel unit , the brightness of the pixel unit can be adjusted by adjusting the output frequency of the first reference voltage that controls the pixel unit to perform image display in the light-emitting signal, thereby effectively preventing the stroboscopic flicker caused by the fact that the display frequency of the pixel unit cannot match the current image refresh frequency. Phenomenon.

In a possible implementation manner, the pulse width control circuit includes a first pulse width control circuit and a second pulse width control circuit. The control terminal of the first pulse width control circuit receives a first pulse width signal with a first duty cycle, the input terminal is electrically connected to the first reference voltage terminal, and the output terminal is electrically connected to the light-emitting pull-up output circuit; The first pulse width control circuit is turned on under the control of a first pulse width signal, and in the light-emitting period, when the first pulse width control circuit is turned on, the first reference voltage passes through the first pulse wide control circuit and output from the output end of the light-emitting pull-up output circuit. The control terminal of the second pulse width control circuit receives a second pulse width signal with a second duty cycle, the input terminal is electrically connected to the second reference voltage terminal, and the output terminal is electrically connected to the light-emitting pull-down output circuit. The second pulse width control circuit is turned on under the control of the second pulse width signal. During the data writing period, when the second pulse width control circuit is turned on, the second reference voltage is passed through the second reference voltage. The pulse width control circuit is output from the output end of the light-emitting pull-down output circuit; the sum of the first duty cycle and the second duty cycle is 1, and the first pulse width signal and the second pulse The phase of the wide signal is opposite.

During the light-emitting period, the duty cycle of the light-emitting signal can be flexibly adjusted at any time with the first pulse signal and the second pulse signal. Then, during the light-emitting display period of the pixel unit, the first pulse signal and the second pulse signal can be adjusted. The duty ratio of the pulse signal can be accurately adjusted to the duty ratio of the light-emitting signal, thereby effectively preventing the stroboscopic phenomenon caused by the fact that the display frequency of the pixel unit cannot match the current image refresh frequency.

In a possible implementation manner, the first pulse width control circuit includes a first pulse transistor, the gate of the first pulse transistor receives the first pulse control signal, and the source of the first pulse transistor is electrically connected. is electrically connected to the first reference voltage terminal, and the drain of the first pulse transistor is electrically connected to the input terminal of the light-emitting pull-up output circuit. The second pulse width control circuit includes a second pulse transistor, the gate of the second pulse tube receives the second pulse control signal, and the source of the second pulse transistor is electrically connected to the second reference The voltage terminal, the drain of the second pulse tube is electrically connected to the output terminal of the light-emitting pull-down output circuit. The first pulse width control circuit and the second pulse width control circuit respectively use a transistor as a switching element to perform the output control of the first reference voltage and the second reference voltage, so that the circuit structure of the pulse width control circuit is simple, and it is used for scanning and light-emitting driving. Component simplification and reduced size of the circuit offer more possibilities.

In a possible implementation manner, the scanning and light-emitting driving circuit further includes a reset circuit, the reset circuit is electrically connected between the pull-up node and the pull-down node, and is used to control the Pulling up the potential of the node, so that the light-emitting drive output circuit stops the light-emitting signal, and controlling the potential of the pull-down node, so that the scan drive output circuit stops outputting the scan signal. By resetting the pull-up node and the pull-down node during the reset period, the potentials of the pull-up node and the pull-down node are in the initial state, so that they can be accurately at the corresponding potential during the data writing period and the light-emitting period, preventing residual The residual charge of the pull-down node and the pull-down node affects the work of the light-emitting drive output circuit and the scan drive output circuit.

In a possible implementation manner, the first control circuit includes a first transistor, a third transistor and a first capacitor. The gate of the first transistor is used for receiving the first clock signal, and the drain of the first transistor is electrically connected to the pull-down node. The source of the third transistor is electrically connected to the second reference voltage terminal to receive the second reference voltage, and the drain of the third transistor is electrically connected to the pull-up node. The first capacitor is electrically connected between the first clock signal terminal and the pull-up node.

In a possible implementation manner, the second control circuit includes a double-gate transistor, wherein both gates of the double-gate transistor are electrically connected to a third clock terminal to receive the third clock signal, The source of the dual-gate transistor is electrically connected to the first reference voltage terminal, and the drain of the dual-gate transistor is electrically connected to the pull-up node.

The first control circuit uses two transistors as switching elements and a capacitor respectively, and the second control circuit uses a double-gate transistor as a switching element to control the voltage of the pull-up node and the pull-down node in different time periods, so that the first control circuit The circuit structure of the circuit and the second control circuit is simple, which provides more possibilities for simplifying the components of the scanning and light-emitting driving circuit and reducing the volume.

In a possible implementation manner, the light-emitting pull-up output circuit includes a fourth transistor, and the light-emitting pull-down output circuit includes a fifth transistor and a second capacitor. The gate of the fourth transistor is electrically connected to the control terminal of the light-emitting pull-up output circuit, the source of the fourth transistor is electrically connected to the input terminal of the light-emitting pull-up output circuit, and the fourth transistor The drain is electrically connected to the output end of the light-emitting pull-up output circuit. The gate of the fifth transistor is electrically connected to the control terminal of the light-emitting pull-down output circuit, the source of the fourth transistor is electrically connected to the input terminal of the light-emitting pull-down output circuit, and the drain of the fifth transistor is electrically connected to the input terminal of the light-emitting pull-down output circuit. The pole is electrically connected to the output end of the light-emitting pull-down output circuit. The second capacitor is electrically connected between the pull-down node and the second reference voltage terminal.

The light-emitting pull-up output circuit and the light-emitting pull-down output circuit use two transistors as switching elements and a capacitor, respectively, to output two different reference voltages in the light-emitting signal at different time periods, so that the circuit structure of the light-emitting drive output circuit is simple, which is for scanning The simplification of components and the reduced size of the light-emitting driver circuit provide more possibilities.

In a possible implementation manner, the first inverter circuit includes a sixth transistor, the gate of the sixth transistor is electrically connected to the pull-up node, and the source of the sixth transistor is electrically connected to the pull-up node. The second reference voltage terminal and the drain of the sixth transistor are electrically connected to the pull-down node. When the sixth transistor is turned on under the control of the pull-up node, the sixth transistor controls the voltage of the pull-down node to be the same second potential as the second reference voltage. The first inverting circuit uses one transistor to realize that the voltage of the pull-down node is different from that of the pull-up node, and the circuit structure is simple, which provides more possibilities for simplification of components and volume reduction of the scanning and light-emitting driving circuit.

In a possible implementation manner, the scan pull-up output circuit includes a seventh transistor, and the scan pull-down output circuit includes an eighth transistor. The gate of the seventh transistor is the control end of the scan pull-up output circuit, the source of the seventh transistor is the input end of the scan pull-up output circuit, and the drain of the seventh transistor is the scan-up output circuit. Pull the output of the output circuit. The gate of the eighth transistor is the control end of the scan pull-down output circuit, the source of the eighth transistor is the input end of the scan pull-down output circuit, and the drain of the eighth transistor is the scan pull-down output circuit 's output.

The scan pull-up output circuit and the scan pull-down output circuit use two transistors as switching elements and a capacitor, respectively, to output two different reference voltages in the scan signal in different time periods, so that the circuit structure of the light-emitting drive output circuit is simple, and it is a scanning method. The simplification of components and the reduced size of the light-emitting driver circuit provide more possibilities.

In a possible implementation manner, the reset circuit includes a tenth transistor and an eleventh transistor. The gate of the tenth transistor is electrically connected to the reset terminal to receive a reset signal, the source of the tenth transistor is electrically connected to the first reference voltage terminal, and the drain of the tenth transistor is electrically connected to the pull-up node. The gate of the eleventh transistor is electrically connected to the reset terminal to receive the reset signal, the source of the eleventh transistor is electrically connected to the second reference voltage terminal, and the eleventh transistor The drain of is electrically connected to the pull-down node. The reset circuit can realize the reset of the voltage of the pull-down node and the voltage of the pull-up node by using two transistors, and the circuit structure is simple, which provides more possibilities for simplifying the components of the scanning and light-emitting driving circuit and reducing the volume.

In a second aspect, the present application provides a scanning and lighting driving circuit. The scanning and lighting driving system includes the aforementioned scanning and lighting driving circuits cascaded in multiple stages, wherein the scanning signal of the scanning and lighting driving circuit of the n-1st stage The output terminal is electrically connected to the first control circuit of the scanning and lighting driving circuit of the nth stage, and the scanning signal output by the scanning and lighting driving circuit of the n-1st stage is used as the pre-start scanning signal, and the n is greater than an integer of 1; the first control circuit includes a first transistor, a third transistor and a first capacitor. The gate of the first transistor is used to receive the first clock signal, and the source of the first transistor is electrically connected to the scan signal output end of the scan and light-emitting drive circuit of the n-1th stage, so The drain of the first transistor is electrically connected to the pull-down node. The gate of the third transistor is electrically connected to the scan signal output terminal of the scan and light-emitting driving circuit of the n-1th stage, and the source of the third transistor is electrically connected to the second reference voltage terminal to receive the the second reference voltage, and the drain of the third transistor is electrically connected to the pull-up node. The first capacitor is electrically connected between the first clock signal terminal and the pull-up node.

In the scanning and light-emitting driving system, the scanning and light-emitting driving circuits are cascaded with each other, so that part of the working time of the cascaded scanning and light-emitting driving circuits overlaps, thereby effectively improving the refresh rate of the pixel unit and meeting the requirements of high-frequency image display. need.

In a third aspect, in a possible implementation manner, a display panel is provided, and a non-display area of the display panel includes the aforementioned scanning and light-emitting driving circuits. Since the scanning and light-emitting driving circuits use fewer electronic components and are smaller in size, the non-display area of the display panel can be further reduced, providing a larger design space for narrowing the frame and increasing the screen ratio.

In a fourth aspect, in a possible implementation manner, a scanning and light-emitting driving circuit is provided, including a light-emitting driving circuit and a pulse width control circuit, the light-emitting driving circuit is used to output a light-emitting signal, and the light-emitting signal is used to control The time when the pixel unit displays the image data, and the pulse width control circuit is electrically connected to the light-emitting driving circuit for controlling the frequency at which the light-emitting driving circuit outputs the light-emitting signal.

During the light-emitting period, the duty cycle of the light-emitting signal can be flexibly adjusted at any time, instead of continuously driving the pixel unit for display at the same voltage (duty cycle is 100%), then, during the light-emitting display period of the pixel unit , the brightness of the pixel unit can be adjusted by adjusting the output frequency of the first reference voltage that controls the pixel unit to perform image display in the light-emitting signal, thereby effectively preventing the stroboscopic flicker caused by the fact that the display frequency of the pixel unit cannot match the current image refresh frequency. Phenomenon.

In a possible implementation manner, the light-emitting driving circuit includes a first control circuit, a second control circuit, a pull-up output circuit and a pull-down output circuit. The first control circuit electrically connects the pull-up output circuit and the pull-down output circuit through the pull-up node, and controls the voltage of the pull-up node according to the received first clock signal during the data writing period in one scan cycle, so that all The pull-up output circuit outputs a first reference voltage, and the first reference voltage controls the pixel unit to stop displaying image data. The second control circuit is electrically connected to the pull-up output circuit through the pull-up node, the light-emitting segment in the scan period outputs a second reference voltage according to the second clock signal received, and the second reference voltage is used to control the pixel The unit displays image data, and the lighting signal includes the first reference voltage and the second reference voltage. The pulse width control circuit is electrically connected to the light-emitting driving circuit, and is used for controlling the frequency at which the pull-up output circuit outputs the first reference voltage and the frequency at which the pull-down output circuit outputs the second reference voltage, In addition, the output frequency of the first reference voltage and the second reference voltage is the same, and the number of times of outputting the first reference voltage in the light-emitting period is greater than 1.

Specifically, the light-emitting driving circuit includes a first pulse width control circuit and a second pulse width control circuit. The control terminal of the first pulse width control circuit receives a first pulse width signal with a first duty ratio, the input terminal is electrically connected to the first reference voltage terminal, and the output terminal is electrically connected to the light-emitting pull-up output circuit, so The first pulse width control circuit is turned on according to the first frequency under the control of the first pulse width signal, and when the first pulse width control circuit is turned on during the light-emitting period, the first reference voltage passes through the The input end, the output end, the output end and the light-emitting pull-up output end circuit of the pulse width control circuit are outputted to the light-emitting signal output end. The control terminal of the second pulse width control circuit receives a second pulse width signal with a second duty cycle, the input terminal is electrically connected to the second reference voltage terminal, the output terminal is electrically connected to the light-emitting signal output terminal, and the output terminal is electrically connected to the light-emitting signal output terminal. The second pulse width control circuit is turned on according to the second frequency under the control of the second pulse width signal. The input end and the output end of the wide control circuit are outputted to the light-emitting signal output end. The sum of the first duty cycle and the second duty cycle is 1, and the phases of the first pulse width signal and the second pulse width signal are opposite.

During the light-emitting period, the duty cycle of the light-emitting signal can be flexibly adjusted at any time with the first pulse signal and the second pulse signal. Then, during the light-emitting display period of the pixel unit, the first pulse signal and the second pulse signal can be adjusted. The duty ratio of the pulse signal can be accurately adjusted to the duty ratio of the light-emitting signal, thereby effectively preventing the stroboscopic phenomenon caused by the fact that the display frequency of the pixel unit cannot match the current image refresh frequency.

In a possible implementation manner, the pull-up output circuit includes a fourth transistor, the gate of the fourth transistor is electrically connected to the pull-up node, and the source of the fourth transistor is electrically connected to the pull-up node In the first pulse width control circuit, the drain of the fourth transistor is electrically connected to the light-emitting signal output terminal. The pull-down output circuit includes a twelfth transistor and a third capacitor, the third capacitor is electrically connected between the pull-down node and the first reference voltage terminal, and the first reference voltage terminal provides the first reference voltage terminal. a reference voltage. The gate of the twelfth transistor is electrically connected to the pull-down node, the source of the twelfth transistor is electrically connected to the first reference voltage terminal, the second reference voltage terminal provides the second reference voltage, and the The drain of the twelfth transistor is electrically connected to the light-emitting signal output terminal.

The light-emitting pull-up output circuit and the light-emitting pull-down output circuit use two transistors as switching elements and a capacitor, respectively, to output two different reference voltages in the light-emitting signal at different time periods, so that the circuit structure of the light-emitting drive output circuit is simple, which is for scanning The simplification of components and the reduced size of the light-emitting driver circuit provide more possibilities.

In a possible implementation manner, the first pulse width control circuit includes a first pulse transistor, and the gate of the first pulse transistor is electrically connected to the first pulse signal output terminal to receive the first pulse control signal, the The source of the first pulse transistor is electrically connected to the second reference voltage terminal, and the drain of the first pulse transistor is electrically connected to the drain of the fourth transistor. The second pulse width control circuit includes a second pulse transistor, the gate of the second pulse transistor is electrically connected to the second pulse signal output terminal to receive the second pulse control signal, and the source of the second pulse transistor is electrically connected. is electrically connected to the first reference voltage terminal, and the drain of the second pulse transistor is electrically connected to the light-emitting signal output terminal.

The first pulse width control circuit and the second pulse width control circuit respectively use a transistor as a switching element to perform the output control of the first reference voltage and the second reference voltage, so that the circuit structure of the pulse width control circuit is simple, and it is used for scanning and light-emitting driving. Component simplification and reduced size of the circuit offer more possibilities.

In a fifth aspect, in a possible implementation manner, a display panel is provided, and the scanning and light-emitting driving circuit is provided in a non-display area of the display panel. Since the scanning and light-emitting driving circuits use fewer electronic components and are smaller in size, the non-display area of the display panel can be further reduced, providing a larger design space for narrowing the frame and increasing the screen ratio.

Description of drawings

In order to illustrate the structural features and effects of the present application more clearly, the following detailed description will be given in conjunction with the accompanying drawings and specific embodiments.

FIG. 1 is a schematic plan view of a display panel according to an embodiment of the present application;

FIG. 2 is a schematic view of a side structure of the display panel shown in FIG. 1;

FIG. 3 is a schematic plan view of an array substrate in the display panel shown in FIG. 2;

FIG. 4 is a functional block diagram of a scanning and lighting driving system according to an embodiment of the present application;

FIG. 5 is a functional block diagram of a scanning and light-emitting driving system commonly used at present;

FIG. 6 is a schematic diagram of a specific circuit structure of any one of the scan driving units shown in FIG. 5;

FIG. 7 is a schematic diagram of a specific circuit structure of any one of the scan driving units shown in FIG. 5;

8 is a schematic diagram of the circuit structure of any pixel unit in the pixel matrix shown in FIG. 3 or FIG. 4;

Fig. 9 is the working timing diagram of the pixel unit shown in Fig. 8;

FIG. 10 is a circuit block diagram of any scanning and light-emitting driving circuit shown in FIG. 4 in the first embodiment of the application;

FIG. 11 is a schematic diagram of a specific circuit structure of the scanning and light-emitting driving circuit shown in FIG. 10;

FIG. 12 is a timing chart when the scanning and light-emitting driving circuit shown in FIG. 11 is in operation;

13 is a specific circuit structure diagram of any one of the scanning and light-emitting driving circuits shown in FIG. 4 in the second embodiment of the application;

FIG. 14 is a working timing diagram of the scanning and light-emitting driving circuit shown in FIG. 13;

FIG. 15 is a specific circuit structure diagram of any scanning and light-emitting driving circuit shown in FIG. 4 in the third embodiment of the application;

FIG. 16 is a timing chart when the scanning and light-emitting driving circuit shown in FIG. 15 is in operation;

17 is a specific circuit structure diagram of any one of the scanning and light-emitting driving circuits shown in FIG. 4 in the fourth embodiment of the present application;

FIG. 18 is a timing chart of the operation of the scanning and light-emitting driving circuit shown in FIG. 17 .

19 is a circuit block diagram of a light-emitting driving circuit in any one of the scanning and light-emitting driving circuits shown in FIG. 4 in the fifth embodiment of the application;

FIG. 20 is a schematic diagram of a specific circuit structure of the light-emitting driving circuit shown in FIG. 19;

FIG. 21 is a timing chart when the light-emitting driving circuit shown in FIG. 20 is in operation;

22 is a specific circuit structure diagram of a light-emitting driving circuit in any one of the scanning and light-emitting driving circuits shown in FIG. 4 in the sixth embodiment of the application;

FIG. 23 is a timing chart of the operation of the light-emitting driving circuit shown in FIG. 22 .

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.

Please refer to FIG. 1 , which is a schematic plan view of a display panel DP (Display Panel) according to an embodiment of the present application. The display panel DP is applied to the display device 10 to perform image display. In this embodiment, the display device 10 can be, for example, a mobile communication terminal, a display, a TV, etc. Of course, the display device needs to perform image display, and other components need to be set (Fig. (not shown), such as a power module, a signal processor module, a signal sensing module, and the like.

The display panel DP includes a display area AA (Active Area) and a non-display area NA (Non active Area), wherein the display area AA is used to perform image display. The non-display area NA is arranged around the display area AA, and does not perform image display, but is used for arranging driving, control circuits and conductive traces.

Please refer to FIG. 2 , which is a schematic side view of the display panel DP shown in FIG. 1 . As shown in FIG. 2 , the display panel DP includes an array substrate 11c, an opposite substrate 11d, and a display medium layer 11e sandwiched between the array substrate 11c and the opposite substrate 11d. In this embodiment, the display medium in the display medium layer 11e is an organic light-emitting semiconductor material (Organic Electroluminescence Diode, OLED). LED) or light-emitting diode (Light EmittingDiode, LED).

Please refer to FIG. 3 , which is a schematic plan view of the array substrate 11 c in the display panel DP shown in FIG. 2 . As shown in FIG. 3 , the corresponding image display area 11a in the array substrate 11c includes a plurality of m*n pixel units (Pixel) P, m data lines 120, and 2n scan driving lines (Scan Lines) arranged in a matrix. ) 130 and 2n emission lines (EmissionLine) 140, where m and n are natural numbers greater than 1.

The plurality of data lines 120 are arranged along the X direction with a first predetermined distance, and the plurality of data lines 120 are insulated from each other and arranged in parallel. Each of the data lines 120 extends along the Y direction Y. It is worth noting that the X direction and the Y direction are perpendicular to each other.

The plurality of scan driving lines 130 are also arranged at a second predetermined distance along the Y direction, and the plurality of scan driving lines 130 are insulated from each other and arranged in parallel. Each scan driving line 130 extends in the X direction.

The plurality of light-emitting driving lines 140 are also arranged at a second predetermined distance along the Y direction, and the plurality of light-emitting driving lines 140 are insulated from each other and arranged in parallel. Each light emitting driving line 140 extends along the X direction.

It should be noted that the plurality of scan driving lines 130 , the plurality of light emitting driving lines 140 and the plurality of data lines 120 are insulated from each other.

For the convenience of description, the m data lines 120 are respectively defined as D1, D2, . -1, Gn, Gn+1, . Each pixel unit P is electrically connected to a scan drive line 130 extending along the X direction, a light emitting drive line 140 extending along the X direction, and a data line 120 extending along the Y direction.

Corresponding to the non-display area NA of the display panel DP, a timing control circuit 101, a data driver circuit (Data Driver) 102 and a scan and light emission driver system (Scan and Emission Driver) 103 for driving the pixel units to perform image display are provided. These circuits can be set on the array substrate 11c. The timing control circuit 101 and the data driver circuit (Data Driver) 102 may also be disposed outside the non-display area NA of the display panel DP, for example, disposed on the backside of the array substrate 11c, wherein the array substrate 11c is provided with The surface of the pixel unit P is the front surface of the array substrate 11c.

The data driving circuit 102 is electrically connected to the plurality of data lines 120 for transmitting image data to be displayed to the plurality of pixel units P in the form of voltages through the plurality of data lines 120 .

The scanning and light-emitting driving system 103 is electrically connected to the plurality of scanning driving lines 130 and the plurality of light-emitting driving lines 140 respectively, and is used for outputting a scanning signal Sc through the plurality of scanning driving lines 130 for controlling when the pixel unit P receives an image data, and the light-emitting signal EM outputted through the plurality of light-emitting driving lines 140 is used to control when the pixel unit P emits light according to the received image data.

The scanning and light-emitting driving system 103 outputs scanning signals from the scanning driving lines G1 , . . . , Gn-1 , Gn, Gn+1 . Sc1,..., Scn-1, Scn, Scn+1..., Sc2n, and based on the positional arrangement of the plurality of light-emitting driving lines 140, the scanning and light-emitting driving system 103 sequentially selects the light-emitting driving lines E1, ..., En-1, En, En+1, ..., E2n output light-emitting signals E1, ..., EMn-1, EMn, EMn+1, ..., EM2n.

The timing control circuit 101 is electrically connected to the data driving circuit 102 and the scanning and lighting driving system 103 respectively, and is used to control the working timing of the data driving circuit 102 and the scanning and lighting driving system 103, that is, the timing control circuit 101 outputs the corresponding timing control signal to the data driving circuit 102 to control when the data driving circuit 102 outputs the image data data; and output the corresponding timing control signal to the scanning and lighting driving system 103 to control when the scanning and lighting driving system 103 outputs the corresponding scanning signal Gn and luminescence signal En.

In this embodiment, the circuit elements in the scanning and light-emitting driving system 103 and the pixel units P in the display panel 11 are fabricated in the display panel 11 in the same process. It can be understood that the display terminal 10 further includes other auxiliary circuits for jointly completing the display of images, such as an image receiving and processing circuit (Graphics Processing Unit, GPU) or a power supply circuit, which will not be repeated in this embodiment.

Please refer to FIG. 4 , which is a functional block diagram of the scanning and lighting driving system 103 according to an embodiment of the present application. As shown in FIG. 4 , the scanning and lighting driving system 103 includes 2n scanning and lighting driving circuits 103u that are cascaded with each other, and the plurality of scanning and lighting driving circuits 103u and 2n groups of scanning lines (not shown) are respectively cascaded. connect. When a plurality of scanning and light-emitting driving circuits 103u are cascaded with each other, the scanning signal in each scanning and light-emitting driving circuit 103u is output to the scanning line electrically connected to it, and also output to the next level of scanning and light-emitting driving. The circuit 103u is used as a work enable signal of the next-stage scanning and light-emitting driving circuit 103u. The work enable signal is used to control the activation and initialization of some electronic components in the scanning and lighting driving circuit 103u, and prepare for the scanning and lighting driving circuit 103u to output scanning signals and lighting signals.

For example, the 2n scanning and lighting driving circuits 103u are cascaded with each other as follows: the scanning output terminal of the scanning and lighting driving circuit of the n-1th stage is electrically connected to the scanning and lighting of the nth stage The initial enable terminal of the driving circuit 103u is Enable. Among them, the scan signal in the n-1st stage scanning and lighting driving circuit 103u is also output to the initial enable terminal Enable of the nth stage scanning and lighting driving circuit 103u, then, the n-1st stage scanning and lighting driving circuit 103u The scan signal in is also used as the pre-start scan signal of the n-th scan and light-emitting driving circuit 103u, that is to say, the work enable signal in this embodiment is the pre-start scan signal.

In this embodiment, each scanning and lighting driving circuit 103u uses the same circuit to output the scanning signal and the lighting signal, that is to say, the circuit for outputting the scanning signal and the circuit for outputting the lighting signal are the same, and there is no need for a separate scanning signal. A separate circuit is provided for the output of the light-emitting signal, which effectively saves the number of electronic components and simplifies the circuit.

As shown in FIG. 4 , for any adjacent three cascaded scanning and light-emitting driving circuits 103u, for example, the manners of the n-1 th, n-th and n+1 th scanning and light-emitting driving circuits 103u are as follows: :

The scanning and light-emitting driving circuit 103u of the n-1 th stage outputs the scanning signal Sc through the scanning signal output terminal Scan and the luminous signal EM to the n-1 th group of scanning lines through the luminous signal output terminal Eout. At the same time, the n-1 th stage The scanning and lighting driving circuit 103u also outputs the scanning signal Sc to the initial enable terminal Enable of the scanning and lighting driving circuit 103u of the nth stage, as a pre-start scanning signal to drive the scanning and lighting driving circuit 103u of the nth stage to start working .

The scanning and lighting driving circuit 103u of the nth stage outputs the scanning signal and the lighting signal to the scanning line of the nth group, and meanwhile, the scanning and lighting driving circuit 103u of the nth stage also outputs the scanning signal to the scanning and lighting of the n+1th stage The light-emitting driving circuit 103u starts to work by driving the scanning and light-emitting driving circuit 103u of the n+1 th stage.

By analogy, the scanning and light-emitting driving circuits 103u of other stages are cascaded according to the above-mentioned cascaded manner, which is not repeated in this embodiment.

Each set of scan lines includes a gate scan line Gk and a light-emitting driving line Ek, where k is any positive integer greater than 1 and less than 2n. The plurality of scanning and light-emitting driving circuits 103u sequentially provide scanning signals to the plurality of groups of scanning driving lines in the pixel array, and provide light-emitting signals to the plurality of groups of light-emitting driving lines.

In the driving display of one frame of image (1 Frame), each scanning and lighting driving circuit 103u outputs a scanning signal and lighting signal of one scanning period to a group of scanning lines connected to the scanning and lighting driving circuit 103u. It can be understood that for 2n groups of scanning lines, the driving display time of one frame of image (1Frame) includes 2n scanning periods, that is, the 2n scanning and light-emitting driving circuits 103u each output a scanning signal and a light-emitting period of one scanning period. signal to a corresponding set of scan lines.

Each scanning and lighting driving circuit 103u receives the clock signal CLK through the timing control circuit 101 electrically connected thereto, and simultaneously receives the reset signal Reset through the reset circuit (not shown) electrically connected thereto. In this embodiment, the reset circuit may be disposed in the non-display area NA of the array substrate 11c. Please continue to refer to FIG. 4 , each pixel unit P includes a pixel driving circuit (not shown) and a light-emitting device (not shown). The pixel driving circuit starts to receive image data data under the control of the scanning signal, and then emits light under the control of the light-emitting signal. The device starts to emit light according to the image data data. When all the pixel units P in the display area AA output light according to the image data data, the image display is completed. That is to say, the scan signal is used to selectively scan and turn on the pixel driving circuit in the pixel unit connected to one group of scan lines, so that the pixel driving circuit receives image data data because it is turned on by scanning. The light-emitting signal is used to control when the driving current corresponding to the image data data is supplied to the light-emitting device to perform image display, or in other words, the light-emitting signal is used to control the adjustment of the light-emitting time of the light-emitting device in the pixel unit P.

Please refer to FIG. 5 , which is a functional block diagram of the scanning and light-emitting driving circuit 103 commonly used at present. As shown in FIG. 5 , in this embodiment, each scanning and light-emitting driving circuit 103u includes an independent scanning driving circuit GU and a light-emitting driving circuit EU. The scan driving circuit GU is used for outputting scan signals, and the light-emitting driving circuit EU is used for outputting light-emitting signals.

Specifically, please refer to FIG. 6 to FIG. 7 , wherein FIG. 6 is a schematic diagram of the specific circuit structure of any one of the scan driving units GUn shown in FIG. 5 , and FIG. 7 is a schematic diagram of the specific circuit structure of any one of the scan driving units shown in FIG. 5 . .

As shown in FIG. 6 , the scanning driving circuit GU for outputting scanning signals includes 8 transistors M1 ˜ M8 and 2 capacitors C1 ˜ C2 , and as shown in FIG. 7 , the light emitting driving circuit EU for outputting light emitting signals includes 12 transistors M1-M12 and 3 capacitors C1-C3.

It can be seen from FIG. 5 to FIG. 7 that the scanning driving circuit GU and the light-emitting driving circuit EU do not share any electronic components. Then, each scanning and light-emitting driving circuit 103u including the scanning driving circuit GU and the light-emitting driving circuit EU which are independent of each other. , at least a total of 20 transistors and 5 capacitors are included. It can be seen that the number of electronic components in each scanning and light-emitting driving circuit 103u is relatively large, and the area occupied is relatively large, which cannot be miniaturized, thereby making it more difficult to reduce the area of the non-display area.

However, each scanning and lighting driving circuit 103u in this embodiment uses the same circuit to output the scanning signal and the lighting signal, that is, the scanning driving circuit that outputs the scanning signal and the lighting that outputs the lighting signal in the scanning and lighting driving circuit 103u The driving circuit can be realized by sharing the same circuit, thereby effectively reducing the number of electronic components in the scanning and lighting driving circuit 103u and the scanning and lighting driving circuit 103, and correspondingly reducing the volume and occupation of the scanning and lighting driving circuit 103. , which provides a greater possibility of reducing the area of the non-display area.

Specifically, please refer to FIG. 8 , which is a schematic diagram of the circuit structure of any pixel unit P in the pixel matrix shown in FIG. 3 or FIG. 4 . The pixel matrix includes a plurality of pixel units P distributed in an array and used to perform image display. As shown in FIG. 8 , it is an internal circuit structure diagram of any pixel unit P in the pixel matrix, for example, a pixel unit P located in the nth row and the jth column in the pixel matrix. The pixel unit P includes a 6T1C pixel driving circuit and a light-emitting device OLED. It is worth noting that k is an integer greater than or equal to 1 and less than or equal to 2n, and j is an integer greater than or equal to 1 and less than or equal to m.

Specifically, the 6T1C pixel driving circuit in the pixel unit P includes a first pixel transistor T1, a second pixel transistor T2, a third pixel transistor T3, a fourth pixel transistor T4, a fifth pixel transistor T5, a sixth pixel transistor T6 and Drive capacitor CP1.

For the pixel unit P located at the kth row and the jth column, the gate of the sixth pixel transistor T6 located in the pixel unit P is electrically connected to the scan driving line G(n-1) at the n-1th row, for receiving the scan signal Sc(n-1); the drain of the sixth pixel transistor T6 is electrically connected to the initialization terminal to receive the initialization voltage VINIT, and the source of the sixth pixel transistor T6 is electrically connected to the first pixel transistor T1 gate.

One end of the driving capacitor CP1 is connected to the light-emitting high voltage driving terminal ELVDD, and the other end is connected to the source of the sixth pixel transistor T6.

The gate of the fifth pixel transistor T5 is electrically connected to the light-emitting driving line E(n) in the k-th row for receiving the light-emitting signal EM(n); the drain of the fifth pixel transistor T5 is electrically connected to the light-emitting high-voltage driving terminal ELVDD receives the light-emitting driving voltage V _DD , and the source of the fifth pixel transistor T5 is electrically connected to the source of the second pixel transistor T2 .

The gate of the second pixel transistor T2 is electrically connected to the scan driving line G(n) in the k-1th row for receiving the scan signal Scan(n), and the drain of the second pixel transistor T2 is electrically connected to the jth row The column data line is used to receive the book voltage V _DATA of the image data data.

The drain of the first pixel transistor T1 is electrically connected to the source of the second pixel transistor T2, and the source of the first pixel transistor T1 is electrically connected to the drain of the fourth pixel transistor T4.

The gate of the third pixel transistor T3 is electrically connected to the scan driving line G(n) in the n-1th row for receiving the scan signal Sc(n), and the drain of the third pixel transistor T3 is electrically connected to the first The gate of the pixel transistor T1 and the source of the third pixel transistor T3 are electrically connected to the drain of the fourth pixel transistor T4.

The gate of the fourth pixel transistor T4 is electrically connected to the light-emitting driving line E(n) in the nth row for receiving the light-emitting signal EM(n), and the source of the fourth pixel transistor T4 is electrically connected to the light-emitting device OLED The anode end of Anode.

The cathode of the light-emitting device OLED is electrically connected to the low-voltage driving terminal ELVSS.

For any pixel unit P in the k-th row, the selection of the pixel unit needs to be performed by receiving the gate scan signal from the scan drive lines Gn and Gn-1, and the image data needs to be performed by receiving the light-emitting signal from the light-emitting drive line En. The voltage V _DATA of data is loaded. That is, each pixel unit P needs at least the cooperation of the light-emitting signal, the scanning signal, the image data, the clock signal and the reset signal to be able to accurately display the image data.

In this embodiment, the pixel transistors T1 to T6 are all P-type thin film transistors (Thin Film Transistor, TFT). The pixel transistors T1-T6 are controlled to be turned on when the level is low, and the pixel transistors T1-T6 are controlled to be turned off when the level is high. The on and off states of the pixel transistors T1 to T6 under the control of the light-emitting signal, scan signal, image data, clock signal and reset signal in different time periods can be specifically described with reference to FIG. 9 .

In other embodiments of the present application, the pixel transistors T1 to T6 may all be N-type thin film transistors (TFTs), and thus, in different time periods, the light-emitting signal, scan signal, image data, clock signal and reset signal The pixel transistors T1 ˜ T6 are controlled to be turned on when the high level is controlled, and the pixel transistors T1 ˜ T6 are controlled to be turned off when the low level is.

In addition, in other embodiments of the present application, the number of pixel transistors and the number of capacitors included in the pixel driving circuit can be adjusted according to actual needs, for example, a 2T1C pixel driving circuit composed of two pixel transistors and one capacitor; 4T1C pixel driver circuit composed of 4 pixel transistors and 1 capacitor; 4T2C pixel driver circuit composed of 4 pixel transistors and 2 capacitors; 5T1C pixel driver circuit composed of 5 pixel transistors and 1 capacitor; composed of 5 2T1C pixel driving circuit composed of pixel transistors and 2 capacitors; 7T1C pixel driving circuit composed of 7 pixel transistors and 1 capacitor; or 7T2C pixel driving circuit composed of 7 pixel transistors and 2 capacitors.

In this embodiment, a scan period during the display period of one frame of image includes a reset period (Reset) Tr, a data writing period (Data) Td and an emission period (Emission) Te arranged in chronological order, wherein , the three time periods are continuous and uninterrupted in time without interval. That is to say, the reset period Tr, the data writing period Td, and the light-emitting period Te are temporally continuous and uninterrupted, with no gaps and no overlap. Wherein, one scanning period of the pixel unit P is the working period of the pixel unit P in the process of displaying one frame of image.

Please refer to FIG. 9 , which is a timing chart of the operation of the pixel unit P shown in FIG. 8 . Now, the operation process of the pixel unit P will be described in detail with reference to FIG. 8 and FIG. 9 .

During the reset period Tr, the scan signal Sc(n-1) provided by the scan drive line Gn-1 is at a low level, and the initialization voltage VINIT is provided to the gate of the first pixel transistor T1, for the gate where the gate of the first pixel transistor T1 is located. The node is initialized, and the drive capacitor CP1 is initialized at the same time, so as to ensure that the electrical signals in the pixel unit P remaining in the previous scanning period are released cleanly.

During the data writing period Td, the scan signal Sc(n) provided by the scan drive line Gn is at a low level, the first pixel transistor T1, the second pixel transistor T2, and the third pixel transistor T3 are turned on, and the voltage corresponding to the image data data V _DATA is loaded to the anode terminal (Anode) of the light-emitting element OLED.

During the light-emitting period Te, the light-emitting signal EM(n) provided by the light-emitting driving line En is at a low level, the fourth pixel transistor T4 and the fifth pixel transistor T5 are turned on, and the light-emitting driving voltage V _DD passes through the fifth pixel transistor T5, The driving path formed by the first pixel transistor T1 and the fourth pixel transistor T4 cooperates with the voltage V _DATA of the image data Data to output a driving current to the light emitting device OLED, thereby driving the light emitting device OLED to emit light according to the image data data to perform image display.

Please refer to FIG. 10 , which is a circuit block diagram of the scanning and lighting driving circuit 100 as any one of the scanning and lighting driving circuits 103u in FIG. 4 according to the first embodiment of the present application.

As shown in FIG. 8 , the scanning and lighting driving circuit 100 includes a first control circuit 11 , a second control circuit 12 , a lighting driving output circuit 13 , a scanning driving output circuit 14 , a first inverter circuit 15 , a buffer circuit 16 and a reset circuit 18.

The first control circuit 11 and the second control circuit 12 are both electrically connected to the light-emitting output circuit 13 through the pull-up node B. Meanwhile, the first control circuit 11 and the second control circuit 12 are both electrically connected to the scan output circuit through the pull-up node B. 14. The light-emitting output circuit 13 is also electrically connected to the light-emitting signal output terminal Eout, and the scan output circuit 14 is also electrically connected to the scan signal output terminal Scan.

The first control circuit 11 is configured to control the voltage of the pull-up node B to be a second potential (the second potential is a low potential) according to the first clock signal CLK1 received from the first clock terminal CK1 during the data writing period Td, and at the same time The voltage of the pull-down node C is controlled to be a first potential (the first potential is a high potential).

During the data writing period Td, when the voltage of the pull-down node C is the first potential, the light-emitting driving circuit 13 is controlled to output the second reference voltage (VSS) as the light-emitting signal EM under the control of the voltage of the pull-down node C being the first potential. to the light-emitting signal output terminal Eout, wherein when the light-emitting signal EM is the second reference voltage (VSS), the pixel unit P cannot be driven to display an image; when the voltage of the pull-down node C is the first potential, the scan output circuit 14 is controlled according to the second reference voltage (VSS). The second clock signal CLK2 received by the two clock terminals CK2 outputs a third reference voltage (high voltage) as the scan signal Sc and is output from the scan signal output terminal Scan, and the third reference voltage in the scan signal Sc is loaded to the corresponding scan drive line to In the pixel unit P, the pixel unit P is controlled to receive image data data.

During the data writing period Td, when the voltage of the pull-up node B is the second potential, the light-emitting driving output circuit 13 is controlled to output the first reference voltage (VDD) as the light-emitting signal EM, wherein the light-emitting signal EM is the first reference The voltage (VDD) can drive the pixel unit to perform image display; at the same time, the scan driving circuit 14 is controlled to stop outputting the fourth reference voltage (VSS) as the scan signal Sc, wherein the fourth reference voltage (VSS) of the scan signal Sc can drive the pixel unit to stop receiving image data.

In this embodiment, the first reference voltage and the third reference voltage are both high-level voltages, and the second reference voltage and the fourth reference voltage are low-level voltages.

The second control circuit 12 is configured to control the voltage of the pull-up node B to be the first potential (high) according to the third clock signal CLK3 received from the third clock terminal CK3 during the light-emitting period Te, and simultaneously pull up the first voltage of the node B. The potential is controlled by the first inverting circuit 15 to control the voltage of the pull-down node C to be the second potential (low). The first inverter circuit 15 is electrically connected between the pull-up node B and the pull-down node C, and is used to control the voltage of the pull-down node C to be the second potential when the pull-up node B is at the first potential.

During the light-emitting period Te, when the voltage of the pull-up node B is the first potential, the light-emitting driving output circuit 13 is controlled to output a first reference voltage (VDD), wherein the first reference voltage (VDD) is used to control the pixel unit P The middle pixel driving circuit loads a driving current into the light emitting device OLED to drive the light emitting device OLED to emit light and cause the pixel unit P to perform image display. When the voltage of the pull-up node B is the first potential, the scan driving circuit 14 is controlled to output the fourth reference voltage (VSS) as the scan signal Sc.

During the lighting period Te, when the voltage of the pull-down node C is at the second potential, the lighting driving output circuit 13 is controlled to stop outputting the second reference voltage (VSS), and the scanning driving output circuit 14 is controlled to output the second reference voltage (low) as The scan signal is output from the scan signal output terminal Scan. At this time, the scan drive line Scan(n) loaded with the scan signal will not perform effective scanning, that is to say, the pixel circuits P of the scan drive line loaded with the scan signal Sc cannot be turned on. , then the image data data cannot be loaded into the corresponding pixel circuit P at this time.

The buffer circuit 16 is electrically connected to the pull-down node C and the second control circuit 12 for obtaining a second reference voltage (VSS from the second control unit 12 under the control of the first potential of the pull-down node C during the data writing period Td) ) and output to the light-emitting signal output terminal Eout, so as to accurately control the light-emitting signal output terminal Eout to maintain the second reference voltage (VSS).

The reset circuit 18 is electrically connected to the pull-up node B and the pull-down node C respectively, and is used for controlling the voltage of the pull-up node B to be the first potential according to the reset signal Reset provided at the reset terminal Re during the reset period Tr, and simultaneously controlling the pull-down node The voltage of C is the second potential. In this embodiment, the reset terminal Re is electrically connected to the reset circuit ( FIG. 4 ) to receive the reset signal Reset.

In this embodiment, the first control circuit 11 , the second control circuit 12 cooperate with the light-emitting output circuit 13 , the first inverter circuit 15 , the buffer circuit 16 and the reset circuit 18 to form a light-emitting driving circuit, and the first control circuit 11 , the first control circuit 11 , the first control circuit 11 The second control circuit 12 cooperates with the scan output circuit 14 , the first inverter circuit 15 , the buffer circuit 16 and the reset circuit 18 to form a scan drive circuit. That is, the light-emitting driving circuit and the scanning driving circuit share the first control circuit 11, the second control circuit 12, the first inverting circuit 15, the buffer circuit 16 and the reset circuit 18, thereby effectively reducing the scanning and light-emitting driving circuit 103u. The electronic components and volume improve the integration degree of the scanning and light-emitting driving circuit 103u.

Please refer to FIG. 11 , which is a schematic diagram of a specific circuit structure of the scanning and lighting driving circuit 100 shown in FIG. 10 . As shown in FIG. 11 , the first control circuit 11 includes a first transistor M1 , a third transistor M3 and a first capacitor C1 .

The gate of the first transistor M1 is electrically connected to the first clock signal terminal CK1 for receiving the first clock signal CK1, and the source of the first transistor M1 is electrically connected to the scanning of the n-1 stage and the scanning of the light-emitting driving circuit 103u The signal output terminal Scan(n-1), the drain of the first transistor M1 is electrically connected to the pull-down node B.

The gate of the third transistor M3 is electrically connected to the scan signal output terminal Scan(n-1) of the scan and light-emitting driving circuit 103u of the n-1 stage, and the source of the third transistor M3 is electrically connected to the second reference voltage terminal VSS, the drain of the third transistor M3 is electrically connected to the pull-up node B.

The first cache capacitor C1 is electrically connected between the first clock signal terminal CK1 and the pull-up node B.

The second control circuit 12 includes a double-gate transistor M2, wherein the double-gate transistor M2 is composed of two sub-transistors in series, and the two series-connected sub-transistors can be a transistor M2a and a transistor M2b.

The gate of the transistor M2a is electrically connected to the third clock terminal CK3, the source of the transistor M2a is electrically connected to the first reference voltage terminal VDD, and the drain of the transistor M2a is electrically connected to the source of the transistor M2b.

The gate of the transistor M2b is electrically connected to the third clock terminal CK3, and the drain of the transistor M2a is electrically connected to the pull-up node B.

The light-emitting output circuit 13 further includes a light-emitting pull-up output circuit 131 and a light-emitting pull-down output circuit 132 . The light-emitting pull-up output circuit 131 is electrically connected to the pull-up node B and the light-emitting signal output terminal Eout, and outputs the first reference voltage VDD when the pull-up node B is at the second potential.

The light-emitting pull-down output circuit 132 is electrically connected to the pull-down node C and the light-emitting signal output terminal Eout. When the voltage of the pull-down node C is at the second potential, it outputs a second reference voltage (VSS), the first reference voltage (VDD) and all The second reference voltage (VSS) constitutes the light-emitting signal, wherein when the light-emitting signal is the first reference voltage (VDD), the pixel unit P is driven to perform image display.

In this embodiment, the light-emitting pull-up output circuit 131 includes a fourth transistor M4, and the light-emitting pull-down output circuit 132 includes a fifth transistor M5 and a second capacitor C2.

The gate of the fourth transistor M4 is electrically connected to the pull-up node B, the source of the fourth transistor M4 is electrically connected to the first reference voltage terminal VDD, and the drain of the fourth transistor M4 is electrically connected to the light-emitting signal output terminal Eout.

The gate of the fifth transistor M5 is electrically connected to the pull-down node C, the source of the fourth transistor M5 is electrically connected to the second reference voltage terminal VSS, and the drain of the fifth transistor M5 is electrically connected to the light-emitting signal output terminal Eout.

The second capacitor C2 is electrically connected between the pull-down node B and the second reference voltage terminal VSS.

The first inverting circuit 15 includes a sixth transistor M6, the gate of the sixth transistor M6 is electrically connected to the pull-up node B, the source of the sixth transistor M6 is electrically connected to the second reference voltage terminal VSS, and the The drain is electrically connected to the pull-down node C.

When the sixth transistor M6 is turned on under the control of the pull-up node B, the voltage of the pull-down node C is controlled to be the second potential that is the same as the second reference voltage. That is to say, when the pull-up node B is at a first potential capable of controlling the sixth transistor M6 to be in an on state, the pull-down node C can be controlled to be at a second potential opposite to that of the pull-up node B, so that the pull-up The voltages at node B and the pull-down node C are in opposite phase.

The scan output circuit 14 is electrically connected to the pull-up node B and the pull-down node C for outputting the scan signal Sc during the data writing period Td, and includes a scan pull-up output circuit 141 and a scan pull-down output circuit 142 .

The scan pull-up output circuit 141 is electrically connected to the pull-up node B and the scan signal output end Scan, and controls the scan pull-up output circuit 141 to output a second reference voltage (VSS) when the pull-up node B is at the first potential. The scan pull-down output circuit 142 is electrically connected to the pull-down node C and the scan signal output terminal Scan, and controls the scan pull-up output circuit 141 to output the first reference voltage (the high level of CLK) to the scan signal output terminal when the pull-down node C is at the first potential Scan, the first reference voltage is used as the scan signal Sc.

In this embodiment, the scan pull-up output circuit 141 includes a seventh transistor M7, and the scan pull-down output circuit 142 includes an eighth transistor M8.

The gate of the seventh transistor M7 is electrically connected to the pull-up node B, the source of the seventh transistor M7 is electrically connected to the second reference voltage terminal VSS, and the drain of the seventh transistor M7 is electrically connected to the scan signal output terminal Scan.

The gate of the eighth transistor M8 is electrically connected to the pull-down node C, the source of the eighth transistor M8 is electrically connected to the second clock terminal CK2 for receiving the second clock signal CLK2, and the drain of the eighth transistor M8 is electrically connected at the scan signal output terminal Scan.

The buffer circuit 16 includes a ninth transistor M9, the gate of the ninth transistor M9 is electrically connected to the pull-down node C, the source of the ninth transistor M9 is electrically connected to the double-gate diode M2, and the drain of the ninth transistor M9 is electrically connected at the light-emitting signal output terminal Eout.

The ninth transistor M9 loads the first reference voltage to the light-emitting signal output terminal Eout during the data writing period Td when the pull-down node C is at the first potential, ensuring that the voltage of the lighting signal output terminal Eout is the first voltage during the data writing period Td The reference voltage is used to ensure that the data signal is accurately written into the pixel unit P.

The reset circuit 18 includes a tenth transistor M10 and an eleventh transistor M11.

The gate of the tenth transistor M10 is electrically connected to the reset terminal Re for receiving the reset signal Reset, the source of the tenth transistor M10 is electrically connected to the first reference voltage terminal VDD, and the drain of the tenth transistor M10 is electrically connected to the first reference voltage terminal VDD. Pull up Node B. In this embodiment, the reset terminal Re may be a signal terminal used by the reset circuit to output the reset signal Reset.

The gate of the eleventh transistor M11 is electrically connected to the reset terminal Re for receiving the reset signal Reset, the source of the eleventh transistor M11 is electrically connected to the second reference voltage terminal VSS, and the drain of the eleventh transistor M11 is electrically connected connected to the drop-down node C.

In this embodiment, the first transistor M1 to the eleventh transistor M11 are all N-type thin film transistors (TFTs), so the first potential is a high potential, the second potential is a low potential, and the first reference voltage is a high voltage, The second reference voltage is a low level.

It should be noted that, since the first reference voltage VDD is a high voltage and the second reference voltage VSS is a low potential, the scan signal Sc having the second reference voltage is used as the scan-on voltage of the pixel unit P, so that the pixel The pixel transistor in the unit P that receives the scan signal Sc should be an N-type TFT that is turned on at a high potential. When the light-emitting signal EM has a second reference voltage, it is used as the light-emitting turn-on voltage of the pixel unit P. Therefore, the pixel unit P receives the light-emitting signal. The pixel transistor of Sc should be an N-type TFT that is turned on at a high potential.

Please refer to FIG. 12 , which is a timing diagram of the scanning and light-emitting driving circuit 100 shown in FIG. 11 when working. The symbols in FIG. 12 are specifically: Sc(n-1) is the voltage waveform of the scan signal output by the scan signal output end Scan of the scan and light-emitting drive circuit 100 of the n-1th stage. CLK1 represents the voltage waveform of the first clock signal, CLK2 represents the voltage waveform of the second clock signal, CLK3 represents the voltage waveform of the third clock signal, Reset represents the voltage waveform of the reset signal output by the reset terminal Re, and VB represents the upper The voltage waveform of the pull-down node B, VC represents the voltage waveform of the pull-down node C, EM(n) represents the voltage waveform of the light-emitting signal EM output from the light-emitting scanning output terminal Eout by the scanning and light-emitting driving circuit 100 of the nth stage, Sc (n) represents the voltage waveform diagram of the scan signal Scan output by the scan signal output terminal Scan of the scan and light-emitting driving circuit 100d of the nth stage.

11-12, the working process of the light-emitting scanning driving circuit when the scanning period of one frame of image is 1st Frame will be described in detail.

During the reset period Tr shown in FIG. 12 , the reset signal Reset output from the reset terminal Re is at a high level, so that the tenth transistor M10 and the eleventh transistor M11 are turned on.

The first reference voltage provided by the first reference voltage terminal VDD is loaded to the pull-up node B through the tenth transistor M10, so that the pull-up node B is at the first potential. The second reference voltage provided by the second reference voltage terminal VSS is loaded to the pull-down node C through the eleventh transistor M11, so that the pull-down node C is at the second potential. Thus, the reset operations of the pull-up node B and the pull-down node C are completed.

During the adjustment period Td1 in the data writing period Td,

The first clock terminal CK1 outputs the first clock signal CLK1, and at the same time the scan signal output terminal Scan of the n-1 stage scan and light-emitting driving circuit 103u outputs the scan signal Sc, thus, the first transistors M1, The third transistors M3 are all turned on.

The second reference voltage provided by the second reference voltage terminal VSS is loaded to the pull-up node B through the turned-on first transistor M3, so that the voltage of the pull-up node B is the second potential. The second reference voltage in the scan signal is loaded to the pull-down node C through the turned-on first transistor M1, so that the voltage of the pull-down node C is the first potential.

Since the pull-up node B is at the second potential, the third transistor M4 and the seventh transistor M7 are turned off, the pull-down node C is at the first potential, the fifth crystal M5 is turned on, and the second reference voltage provided by the second reference voltage terminal VSS is loaded to The light-emitting signal is output Eout; the eighth transistor M8 is turned on, but since the second clock signal terminal CK2 does not output the second clock signal at this time, the second clock signal terminal CK2 loads the first reference voltage to the scan signal output terminal Sc.

In the data writing period Td, the period Td2 is written,

Due to the energy storage effect of the first capacitor C1, the voltage of the pull-up node B is further reduced on the basis of the second potential; the voltage of the pull-down node C is further increased on the basis of the first potential due to the energy storage effect of the second capacitor C2.

The second clock terminal CK2 outputs the second clock signal CLK2, the eighth transistor M8 is turned on, and the second clock signal terminal CK2 loads the second clock signal CLK2 of the second potential to the scan signal output terminal Scan, so that the first scan signal is output The terminal Scan outputs the scan signal Sc of the first reference voltage.

In this embodiment, all pixel units on the scan driving line to which the scan signal Sc of the first reference voltage is loaded are turned on, so that image data is loaded and written into the pixel unit P.

During the light-emitting period Tr, the third clock terminal outputs the third clock signal CLK3, the dual-gate transistor M2 is turned on, and the first reference voltage terminal VDD loads the first reference voltage VDD to the pull-up node B, so that the voltage of the pull-up node B is pulled up When it jumps to the first potential and the voltage of the pull-up node B is the first potential, the sixth transistor M6 is turned on, so that the voltage of the pull-down node C is the second potential.

When the voltage of the pull-up node B is the first potential, and the voltage of the pull-down node C is the second potential, the fourth transistor M4 and the seventh transistor M7 are turned on, and the fifth transistor M5 and the eighth transistor are turned off.

The first reference voltage provided by the first reference voltage terminal VDD is transmitted to the light-emitting signal output terminal Eout through the fourth transistor M4, and the second reference voltage provided by the second reference voltage terminal VSS is transmitted to the scan signal output terminal Scan through the seventh transistor M7.

Since the scan signal output terminal Scan stops outputting the scan signal Sc, the pixel unit P corresponding to the scan driving line does not receive the image data data, and the light-emitting signal output terminal Eout outputs the light-emitting signal EM with the first reference voltage to control the pixels The unit P starts to emit light for the received image data data to perform image display, that is to say, the light-emitting signal has a first reference voltage for controlling the light-emitting time of the pixel unit P. Therefore, the light-emitting signal is controlled by the first reference voltage. The duration and frequency of the reference voltage can be adjusted for the light-emitting time of the pixel unit P, and the pixel unit P can be prevented from being affected by other image data during the light-emitting period Tr, ensuring that the pixel unit P performs image display correctly.

In this embodiment, the scanning and light-emitting driving circuit 100 can output the light-emitting output signal and the scanning signal in the scanning display period during the display period of one frame of image, thereby effectively improving the integration degree of the scanning and light-emitting driving circuit 100 and reducing the number of transistors , while reducing the cost, the volume of the scanning and light-emitting driving circuit 100 can also be reduced, which provides a greater possibility for the narrow frame requirement of the display panel.

Please refer to FIG. 13 , which is a specific circuit structure diagram of any one of the scanning and lighting driving circuits 200 shown in FIG. 4 in the second embodiment of the present application. In this embodiment, the scanning and lighting driving circuit 200 is the same as the one shown in FIG. 11 . The circuit structure of the scanning and lighting driving circuit 100 is basically the same, and the only difference is that the scanning and lighting driving circuit 200 further includes the pulse width control circuit 17 .

The pulse width control circuit 17 is electrically connected to the pull-up output circuit 13 , the pull-down output circuit 14 and the light-emitting signal output terminal Eout, and is used for controlling the pull-up output circuit 13 to output the first reference voltage and the frequency and the output of the pull-down output circuit 14 the frequency of the second reference voltage.

The pulse width control circuit 17 includes a first pulse width control circuit 171 and a second pulse width control circuit 172 .

The first pulse width control circuit 171 and the light-emitting pull-up output circuit 131 are connected in series with the second reference voltage terminal VSS and the light-emitting signal output terminal Eout, and the first pulse width control circuit 171 is controlled by the first pulse width signal P1 according to the first frequency. is in the conducting state.

When the pull-up output circuit 13 is in a conducting state under the control of the pull-up node B, the first pulse width control circuit 171 outputs the first reference voltage to the light-emitting signal output terminal Eout according to a first frequency.

The second pulse width control circuit 172 and the light-emitting pull-down output circuit 132 are connected in parallel with the second reference voltage terminal VDD and the light-emitting signal output terminal Eout, and the second pulse width control circuit 172 is in conduction according to the second frequency under the control of the second pulse width signal P2. pass status.

When the pull-down output circuit 14 is in a non-conducting state under the control of the pull-down node B, the second pulse width control circuit 172 outputs the second reference voltage to the light-emitting signal output terminal Eout according to the first frequency.

The sum of the duty ratio of the first pulse width signal P1 and the second pulse width signal P2 and the second duty ratio is 1, and the phases of the first pulse width signal and the second pulse width signal are opposite.

The first pulse width control circuit 171 includes a thirteenth transistor M13. The gate of the thirteenth transistor M13 is electrically connected to the first pulse signal output terminal P1 for receiving the first pulse control signal P1 from the first pulse signal output terminal P1. , the source of the thirteenth transistor M13 is electrically connected to the first reference voltage terminal VDD, and the drain of the thirteenth transistor M13 is electrically connected to the drain of the fourth transistor M4.

The second pulse width control circuit 172 includes a fourteenth transistor M14. The gate of the fourteenth transistor M15 is electrically connected to the second pulse signal output terminal P2 for receiving the second pulse control signal P2 from the second pulse signal output terminal P2. , the source of the fourteenth transistor M14 is electrically connected to the second reference voltage terminal VSS, and the drain of the fourteenth transistor M14 is electrically connected to the light-emitting scan output terminal Eout.

Please refer to FIG. 14 , which is an operation timing diagram of the scanning and light-emitting driving circuit 200 shown in FIG. 13 . In FIG. 14 , Sc(n-1) represents the voltage waveform diagram of the scan signal output by the scan signal output terminal Scan of the n-1 th scan and light-emitting driving circuit 200 , CLK1 represents the voltage waveform diagram of the first clock signal, CLK2 represent the voltage waveform of the second clock signal, CLK3 represents the voltage waveform of the third clock signal, Reset represents the voltage waveform of the reset signal output by the reset terminal Re, VB represents the voltage waveform of the pull-up node B, and VC represents the pull-down node The voltage waveform of C, P1 represents the voltage waveform of the first pulse width control signal, P2 represents the voltage waveform of the second pulse width control signal, and EM(n) represents the voltage waveform of the light-emitting signal output from the light-emitting scanning output terminal Eout In FIG. 2 , Sc(n) represents the waveform of the scan signal voltage output by the scan signal output terminal Scan of the n-th scan and light-emitting driving circuit 200 .

13-14, the working process of the light-emitting scanning driving circuit 200 when a frame of image scanning period is 1 Frame will be described in detail.

During the reset period Tr as shown in FIG. 14 , the reset signal Reset output from the reset terminal Re is at a high level, so that the tenth transistor M10 and the eleventh transistor M11 are turned on.

The first reference voltage provided by the first reference voltage terminal VDD is loaded to the pull-up node B through the tenth transistor M10, so that the pull-up node B is at the first potential. The second reference voltage provided by the second reference voltage terminal VSS is loaded to the pull-down node C through the eleventh transistor M11, so that the pull-down node C is at the second potential. Thus, the reset operations of the pull-up node B and the pull-down node C are completed.

During the adjustment period Td1 in the data writing period Td,

The first clock terminal CK1 outputs the first clock signal CLK1, and at the same time the scan signal output terminal Scan of the n-1 stage scan and light-emitting driving circuit outputs the scan signal. The transistors M3 are all turned on.

The second reference voltage provided by the second reference voltage terminal VSS is loaded to the pull-up node B through the turned-on first transistor M3, so that the voltage of the pull-up node B is the second potential. The second reference voltage in the scan signal is loaded to the pull-down node C through the turned-on first transistor M1, so that the voltage of the pull-down node C is the first potential.

Since the pull-up node B is at the second potential, the third transistor M4 and the seventh transistor M7 are turned off, the pull-down node C is at the first potential, the fifth crystal M5 is turned on, and the second reference voltage provided by the second reference voltage terminal VSS is loaded to The light-emitting signal is output Eout; the eighth transistor M8 is turned on, but since the second clock signal terminal CK2 does not output the second clock signal at this time, the second clock signal terminal CK2 loads the first reference voltage to the scan signal output end Scan.

In the data writing period Td, the period Td2 is written,

Due to the energy storage effect of the first capacitor C1, the voltage of the pull-up node B is further reduced on the basis of the second potential; the voltage of the pull-down node C is further increased on the basis of the first potential due to the energy storage effect of the second capacitor C2.

The second clock terminal CK2 outputs the second clock signal CLK2, the eighth transistor M8 is turned on, and the second clock signal terminal CK2 loads the second clock signal CLK2 of the second reference voltage to the scan signal output terminal Scan, so that the scan signal output terminal Scan outputs the scan signal Sc of the first reference voltage.

In this embodiment, all pixel units on the scan driving line to which the scan signal Sc of the first reference voltage is loaded are turned on, so that image data is loaded and written into the pixel unit P.

In the data writing period Td, since the voltage of the pull-down node B is maintained at the first potential, that is to say, the fifth crystal M5 is always in the conducting state, so that the light-emitting signal output terminal Eout is also always maintained at the second reference voltage Therefore, the voltage of the light-emitting signal output terminal Eout will not be affected by the pulse width control circuit 17 .

During the light-emitting period Tr, the third clock terminal outputs the third clock signal CLK3, the dual-gate transistor M2 is turned on, and the first reference voltage terminal VDD loads the first reference voltage VDD to the pull-up node B, so that the voltage of the pull-up node B is pulled up When it jumps to the first potential and the voltage of the pull-up node B is the first potential, the sixth transistor M6 is turned on, so that the voltage of the pull-down node C is the second potential.

When the voltage of the pull-up node B is the first potential, and the voltage of the pull-down node C is the second potential, the fourth transistor M4 and the seventh transistor M7 are turned on, and the fifth transistor M5 and the eighth transistor are turned off.

The thirteenth transistor M13 outputs the first reference voltage to the light-emitting scanning output terminal Eout according to the first frequency under the control of the first pulse signal P1, and the fourteenth transistor M14 outputs the first reference voltage according to the second frequency under the control of the second pulse signal P2. Two reference voltages are applied to the light-emitting scan output terminal Eout.

It can be seen that during the light-emitting period, the duty cycle of the light-emitting signal EM can be flexibly adjusted at any time along with the first pulse signal P1 and the second pulse signal P2. The duty ratio of the pulse signal P1 and the second pulse signal P2 can be used to accurately adjust the duty ratio of the light-emitting signal EM, thereby effectively preventing the stroboscopic phenomenon caused by the inability of the display frequency of the pixel unit P to match the current image refresh frequency.

Please refer to FIG. 15 , which is a specific circuit structure diagram of any one of the scanning and lighting driving circuits 300 shown in FIG. 4 in the third embodiment of the application. In this embodiment, the scanning and lighting driving circuit 300 is the same as the one shown in FIG. 11 . The circuit structure of the scanning and lighting driving circuit 100 is basically the same, the only difference is that all transistors (the first transistor M1 to the eleventh transistor M11 ) in the scanning and lighting driving circuit 300 in this embodiment are P-type thin film transistors.

In addition, in the reset circuit 18, the tenth transistor M10 and the eleventh transistor M11 are provided.

The gate of the tenth transistor M10 is electrically connected to the reset terminal Re for receiving the reset signal Reset, the source of the tenth transistor M10 is electrically connected to the second reference voltage terminal VSS, and the drain of the tenth transistor M10 is electrically connected to the second reference voltage terminal VSS. Pull up Node B.

The gate of the eleventh transistor M11 is electrically connected to the reset terminal Re for receiving the reset signal Reset, the source of the eleventh transistor M11 is electrically connected to the first reference voltage terminal VDD, and the drain of the eleventh transistor M11 is electrically connected connected to the drop-down node C.

In this embodiment, the first transistor M1 to the eleventh transistor M11 are all P-type thin film transistors (TFTs). Therefore, the first potential is a low potential, the second potential is a high potential, and the first reference voltage is a low voltage. The second reference voltage is a high potential.

It should be noted that, since the first reference voltage is a low voltage and the second reference voltage is a high potential, when the scan signal Sc has the first reference voltage, it is used as the scan turn-on voltage of the pixel unit P. Therefore, the pixel unit P The pixel transistor that receives the scan signal Sc should be a P-type TFT that is turned on at a low potential. When the light-emitting signal EM has the first reference voltage, it is used as the light-emitting turn-on voltage of the pixel unit P. Therefore, the pixel unit P receives the light-emitting signal Sc. The pixel transistor should be a P-type TFT that is turned on at a low potential.

Please refer to FIG. 16 , which is a timing diagram of the scanning and light-emitting driving circuit 300 shown in FIG. 15 when working. The symbols in FIG. 16 are specifically: Sc(n-1) is the voltage waveform of the scan signal output by the scan signal output end Scan of the scan and light-emitting drive circuit 100 of the n-1th stage. CLK1 represents the voltage waveform of the first clock signal, CLK2 represents the voltage waveform of the second clock signal, CLK3 represents the voltage waveform of the third clock signal, Reset represents the voltage waveform of the reset signal output by the reset terminal Re, and VB represents the upper The voltage waveform of the pull-down node B, VC represents the voltage waveform of the pull-down node C, EM(n) represents the voltage waveform of the light-emitting signal EM output from the light-emitting scanning output terminal Eout by the scanning and light-emitting driving circuit 100 of the nth stage, Sc (n) represents the voltage waveform diagram of the scan signal Scan output by the scan signal output terminal Scan of the scan and light-emitting driving circuit 100d of the nth stage.

The operation timing of the scanning and lighting driving circuit 300 is the same as that of the scanning and lighting driving circuit 100 shown in FIG. 12 , and details are not repeated in this embodiment.

Please refer to FIG. 17 , which is a specific circuit structure diagram of any scanning and lighting driving circuit 400 shown in FIG. 4 in the fourth embodiment of the present application. In this embodiment, the scanning and lighting driving circuit 400 is the same as the one shown in FIG. 13 . The circuit structure of the scanning and lighting driving circuit 200 is basically the same, the only difference is that all transistors (the first transistor M1 to the eleventh transistor M11 ) in the scanning and lighting driving circuit 400 are P-type thin film transistors.

In addition, in the reset circuit 18, the tenth transistor M10 and the eleventh transistor M11 are provided.

The gate of the tenth transistor M10 is electrically connected to the reset terminal Re for receiving the reset signal Reset, the source of the tenth transistor M10 is electrically connected to the second reference voltage terminal VSS, and the drain of the tenth transistor M10 is electrically connected to the second reference voltage terminal VSS. Pull up Node B.

The gate of the eleventh transistor M11 is electrically connected to the reset terminal Re for receiving the reset signal Reset, the source of the eleventh transistor M11 is electrically connected to the first reference voltage terminal VDD, and the drain of the eleventh transistor M11 is electrically connected connected to the drop-down node C.

In this embodiment, the first transistor M1 to the eleventh transistor M11 are all P-type thin film transistors (TFTs). Therefore, the first potential is a low potential, the second potential is a high potential, and the first reference voltage is a low voltage. The second reference voltage is a high potential.

It should be noted that, since the first reference voltage is a low voltage and the second reference voltage is a high potential, when the scan signal Sc has the first reference voltage, it is used as the scan turn-on voltage of the pixel unit P. Therefore, the pixel unit P The pixel transistor that receives the scan signal Sc should be a P-type TFT that is turned on at a low potential. When the light-emitting signal EM has the first reference voltage, it is used as the light-emitting turn-on voltage of the pixel unit P. Therefore, the pixel unit P receives the light-emitting signal Sc. The pixel transistor should be a P-type TFT that is turned on at a low potential.

Please refer to FIG. 18 , which is a timing diagram of the scanning and light-emitting driving circuit 400 shown in FIG. 17 when working. The operation timing of the scanning and lighting driving circuit 400 is the same as that of the scanning and lighting driving circuit 200 shown in FIG. 14 , and details are not repeated in this embodiment.

As shown in FIG. 19 , which is a circuit block diagram of the light-emitting driving circuit in any scanning and light-emitting driving circuit 500 shown in FIG. 4 in the fifth embodiment of the present application, in this embodiment, the light-emitting driving circuit includes the first control circuit 11 , a second control circuit 12 , a light-emitting output circuit 13 , a first inverter circuit 15 , a buffer circuit 16 and a pulse width control circuit 17 . The light-emitting output circuit 13 includes a light-emitting pull-up output circuit 13 and a light-emitting pull-down output circuit 14 , and the pulse width control circuit 171 includes a first pulse width control circuit 171 and a second pulse width control circuit 172 .

The first control circuit 11 is electrically connected to the second control circuit 12 through the first node A, and the pull-up output circuit 13 is electrically connected through the pull-up node B, and the second control circuit 12 is electrically connected to the pull-down output through the pull-down node C. The circuit 14 and the first inverting circuit 15 are electrically connected between the pull-up node B and the pull-down node C.

The first control circuit 11 is electrically connected to the first clock terminal CK1 , the first adjustment signal terminal Vin, the second reference voltage terminal VSS and the first node A.

The first clock signal terminal CK1 is used for outputting the first clock signal CLK1 according to the first preset frequency.

The first adjustment signal terminal Vin is used for outputting the first adjustment signal Vi.

The second reference voltage terminal VSS is used for outputting the second reference voltage VSS.

The first control circuit 11 receives the first clock signal CLK1 from the first clock signal terminal CK1, so that the data writing period Td in one scan period T changes the first potential (high) to the first potential (high) in different periods according to the first clock signal CLK1. And the second potential (low) is transmitted to the pull-up node B. In this embodiment, the data writing period Td in one scan period T receives the first clock signal CLK1 in two different periods, so that the first potential (high) and the second potential ( low) is transmitted to the pull-up Node B.

In this embodiment, the data writing period Td includes an adjustment period Td1 , a pull-up period Td2 and a pull-down period Td3 that are continuous and non-overlapping in time.

The first clock signal terminal CK1 outputs the first clock signal during the adjustment period Td1 and the pull-down period Td3 respectively, so that the first control circuit 11 adjusts the first potential (high) according to the first clock signal CLK1 during the adjustment period Td1 and the pull-down period Td3 respectively. ) and the second potential (low) is transmitted to the pull-up node B.

When the pull-up node B is at the second potential, the pull-down node C is controlled to be at the second potential by the first inverting circuit 15 connected between the pull-up node and the pull-down node.

The second control circuit 12 is electrically connected to the second clock terminal CK2 and the first reference voltage terminal VDD.

The second clock terminal CK2 is used for outputting the clock signal CLK2, and the first reference voltage terminal VDD is used for outputting the first reference voltage.

In this embodiment, the first reference voltage is higher than the second reference voltage. For example, the first reference voltage is a high reference voltage and the second reference voltage is a low reference voltage.

The second control circuit 12 receives the second clock signal CLK2 during the pull-up period Td2 within the data writing period Td, and transmits the first potential (high) to the pull-up node B under the control of the second clock signal CLK2, and, When the pull-up node B is at the first potential, the second potential is output to the pull-down node C.

The light-emitting pull-up output circuit 131 is electrically connected to the pull-up node B and the light-emitting signal output terminal Eout. When the pull-up node B is at the second potential, the light-emitting pull-up output circuit 131 is in a conducting state so as to output the second reference voltage .

The light-emitting pull-down output circuit 141 is electrically connected to the pull-down node C and the light-emitting signal output terminal Eout, and outputs a first reference voltage when the pull-down node C is at a first potential. In this embodiment, the first reference voltage and the second reference voltage cooperate with each other to form the light-emitting signal.

The buffer circuit 16 is electrically connected between the first control circuit 11 and the first node A, and is used for controlling the first node A to buffer a certain period of time to maintain the voltage conversion with the first clock signal CLK1 .

The pulse width control circuit 17 is electrically connected to the light-emitting pull-up output circuit 13, the light-emitting pull-down output circuit 14 and the light-emitting signal output terminal Eout, and is used to control the pull-up output circuit 13 to output the first reference voltage and the frequency and the pull-down output circuit 14 outputs the frequency of the second reference voltage.

The pulse width control circuit 17 includes a first pulse width control circuit 171 and a second pulse width control circuit 172 .

The first pulse width control circuit 171 and the pull-up output circuit 13 are connected in series with the second reference voltage terminal VSS and the light-emitting signal output terminal Eout, and the first pulse width control circuit 171 is controlled by the first pulse width signal P1 according to the first frequency. On state.

When the pull-up output circuit 13 is in a conducting state under the control of the pull-up node B, the first pulse width control circuit 171 outputs the first reference voltage to the light-emitting signal output terminal Eout according to a first frequency.

The second pulse width control circuit 172 and the pull-down output circuit 14 are connected in parallel with the second reference voltage terminal VDD and the light-emitting signal output terminal Eout. The second pulse width control circuit 172 is turned on according to the second frequency under the control of the second pulse width signal P2 state.

When the pull-down output circuit 14 is in a non-conducting state under the control of the pull-down node B, the second pulse width control circuit 172 outputs the second reference voltage to the light-emitting signal output terminal Eout according to the first frequency.

The sum of the duty ratio of the first pulse width signal P1 and the second pulse width signal P2 and the second duty ratio is 1, and the phases of the first pulse width signal and the second pulse width signal are opposite.

More specifically, please refer to FIG. 20 , which is a schematic diagram of a specific circuit structure of the light-emitting driving circuit shown in FIG. 19 . As shown in Figure 20,

The first control circuit 11 includes a first transistor M1, a second transistor M2 and a third transistor M3.

The gate of the first transistor M1 is electrically connected to the first clock signal terminal CK1 for receiving the first clock signal CK1, the source of the first transistor M1 is electrically connected to the first adjustment signal terminal Vin, and the drain of the first transistor M1 It is electrically connected to the buffer circuit 16 .

The gate of the second transistor M2 is electrically connected to the first clock signal terminal CK1 , the source of the second transistor M2 is electrically connected to the second reference voltage VSS, and the drain of the second transistor M2 is electrically connected to the first node A.

The gate of the third transistor M3 is electrically connected to the first clock signal terminal CK1 , the source of the third transistor M3 is electrically connected to the second reference voltage VSS, and the drain of the third transistor M3 is electrically connected to the pull-up node B.

The pull-up output circuit 13 includes a fourth transistor M4. The gate of the fourth transistor M4 is electrically connected to the pull-up node B, and the source of the fourth transistor M4 is electrically connected to the first pulse width control circuit 171. The drain is electrically connected to the light-emitting signal output terminal Eout.

The buffer circuit 16 includes a fourth transistor M5, a sixth transistor M6 and a fourth capacitor C4.

The gate of the fifth transistor M5 is electrically connected to the drain of the first transistor M1, the source of the fifth transistor M5 is electrically connected to the first clock signal terminal CK1, and the drain of the fifth transistor M5 is electrically connected to the sixth transistor M6.

The gate of the sixth transistor M6 is electrically connected to the drain of the first transistor M1, the source of the sixth transistor M6 is electrically connected to the drain of the fifth transistor M5, and the drain of the sixth transistor M6 is electrically connected to the first transistor M5. Node A.

The fourth capacitor C4 is electrically connected between the gate of the fifth transistor M5 and the first reference voltage terminal VDD.

The second control circuit 12 includes a sub-pull-up control circuit 121 and a sub-pull-down control circuit 122 . The sub-pull-up control circuit 121 is used to control the voltage of the pull-up node B to be at the first potential, and the sub-pull-down control circuit 122 is used to control the voltage of the pull-down node C to be at the second potential.

Specifically, the sub-pull-up control circuit 121 is electrically connected to the first node A, the second clock signal terminal CK2 , the first reference voltage terminal VDD and the pull-up node B.

When the first control circuit 12 outputs a signal of the first potential or the second potential to the pull-up node B without receiving the first clock signal CLK1, the sub-pull-up control circuit 121 at the first node A and the second clock signal Under the control of the terminal CK2, the second reference voltage terminal VDD is output to the pull-up node B, thereby controlling the voltage of the pull-up node B to be the first potential.

The sub-pull-down control circuit 122 is electrically connected to the first node A, the second clock signal terminal CK2 , the first reference voltage terminal VDD and the pull-down node C.

When the pull-up node B cannot control the voltage of the pull-down node C due to the first potential, the sub-pull-down control circuit 122 outputs the second potential to the pull-down node C under the control of the first node A and the second clock signal terminal CK2 , and then control the voltage of the pull-down node B to be the second potential.

More specifically, the sub-pull-up control circuit 121 includes a seventh transistor M7, an eighth transistor M8 and a first capacitor C1, and the sub-pull-down control circuit 122 includes a ninth transistor M9, a tenth transistor M10 and a second capacitor C2.

The gate of the seventh transistor M7 is electrically connected to the first node A, the source of the seventh transistor M7 is electrically connected to the first reference voltage terminal VDD, and the drain of the seventh transistor M7 is electrically connected to the eighth transistor M8.

The gate of the eighth transistor M8 is electrically connected to the second clock terminal CK2 for receiving the second clock signal CLK2, the source of the eighth transistor M8 is electrically connected to the drain of the seventh transistor M7, and the drain of the eighth transistor M8 The pole is electrically connected to the pull-up node B.

The first capacitor C1 is electrically connected between the CK2 of the second clock signal and the second node.

The second capacitor C2 is electrically connected between the first node A and the second node D.

The gate of the ninth transistor M9 is electrically connected to the first node A, the source of the ninth transistor M9 is electrically connected to the CK2 of the second clock signal, and the drain of the seventh transistor M7 is electrically connected to the second node D.

The gate of the tenth transistor M10 is electrically connected to the CK2 of the second clock signal for receiving the second clock signal CLK2, the source of the tenth transistor M10 is electrically connected to the second node D, and the drain of the tenth transistor M10 is electrically connected. Connected to drop-down node C.

The first inverting circuit 15 includes an eleventh transistor M11, the gate of the eleventh transistor M11 is electrically connected to the pull-up node B, the source of the eleventh transistor M11 is electrically connected to the first reference voltage terminal VDD, and the tenth transistor M11 is electrically connected to the first reference voltage terminal VDD. The drain of a transistor M11 is electrically connected to the pull-down node C.

The pull-down output circuit 132 includes a twelfth transistor M12 and a third capacitor C3. in,

The third capacitor C3 is electrically connected between the pull-down node C and the first reference voltage terminal VDD.

The gate of the twelfth transistor M12 is electrically connected to the pull-down node C, the source of the twelfth transistor M12 is electrically connected to the first reference voltage terminal VDD, and the drain of the twelfth transistor M12 is electrically connected to the light-emitting signal output terminal Eout .

The first pulse width control circuit 171 includes a thirteenth transistor M13. The gate of the thirteenth transistor M13 is electrically connected to the first pulse signal output terminal P1 for receiving the first pulse control signal P1 from the first pulse signal output terminal P1. , the source of the thirteenth transistor M13 is electrically connected to the second reference voltage terminal VSS, and the drain of the thirteenth transistor M13 is electrically connected to the drain of the fourth transistor M4.

The second pulse width control circuit 172 includes a fourteenth transistor M14. The gate of the fourteenth transistor M15 is electrically connected to the second pulse signal output terminal P2 for receiving the second pulse control signal P2 from the second pulse signal output terminal P2. , the source of the fourteenth transistor M14 is electrically connected to the first reference voltage terminal VDD, and the drain of the fourteenth transistor M14 is electrically connected to the light-emitting signal output terminal Eout.

In this embodiment, the first transistor M1 to the fourteenth transistor M14 are all P-type thin film transistors (TFTs). Therefore, the first potential is a high potential, the second potential is a low potential, and the first reference voltage is a high voltage. The second reference voltage is a low level. The first transistor M1 to the fourteenth transistor M14 are turned off under high voltage control, and turned on under low voltage control.

Please refer to FIG. 21 , which is a timing diagram of the light-emitting driving circuit shown in FIG. 20 when working. The symbols in FIG. 21 are specifically: Vi represents the voltage waveform of the first adjustment signal Vi, CLK1 represents the voltage waveform of the first clock signal, CLK2 represents the voltage waveform of the second clock signal, and VA represents the first node The voltage waveform of A, VB represents the voltage waveform of the pull-up node B, VC represents the voltage waveform of the pull-down node C, P1 represents the voltage waveform of the first pulse width control signal, P2 represents the voltage of the second pulse width control signal The waveform diagram, EM(n) represents the voltage waveform diagram of the light-emitting signal EM output from the light-emitting scanning output terminal Eout by the scanning and light-emitting driving circuit 500 .

20 to 21 together, the working process of the light-emitting scanning driving circuit during one frame of image scanning period 1Frame will be described in detail.

As shown in FIG. 21 , in the reset period Tr, the first clock terminal CK1 does not output the first clock signal CLK1, so that the first transistor M1 to the third transistor M3 in the first control circuit 11 are all in an off state, Therefore, the first node A and the pull-up node B are both at low potential.

Since the pull-up node B is at a low level, the fourth transistor M4 is turned on, and the thirteenth transistor M13 outputs the second reference voltage to the light-emitting scanning output terminal Eout according to the first frequency under the control of the first pulse signal P1.

The second clock terminal CK2 outputs the second clock signal CLK2 and then stops outputting the second clock signal CLK2. The first capacitor C1 releases the residual charge through the second clock terminal CK2 to further ensure that the voltage of the pull-up node B is low. When the output stops After the second clock signal CLK2, the eighth transistor M8 and the tenth transistor M10 are turned off, and the voltage of the pull-down node C is clamped to a high level by the first reference voltage terminal VDD through the third capacitor C3. Thus, the reset operations of the pull-up node B and the pull-down node C are completed.

Since the pull-down nodes C are all low, the twelfth transistor M12 is in an off state, and the fourteenth transistor M14 outputs the first reference voltage to the light-emitting scanning output terminal Eout according to the second frequency under the control of the second pulse signal P2.

During the adjustment period Td1 in the data writing period Td,

The first clock terminal CK1 outputs the first clock signal CLK1, and at the same time the first adjustment signal terminal Vin outputs the first adjustment signal, so that the first transistor M1 to the third transistor M3 in the first control circuit 11 are all in a conducting state. The first node A is at a low level by loading the first reference voltage through the third transistor M3, and the pull-up node B is at a high level due to the input of the first adjustment signal.

Since the voltage of the pull-up node B is high, the fourth transistor M4 and the eleventh transistor M11 are turned off, and the pull-up node B cannot control the voltage of the pull-down node B to be low through the eleventh transistor M11 in the first inverter circuit 15 potential.

The second clock terminal CK2 does not output the second clock signal CLK2, the eighth transistor M8 and the tenth transistor M10 are turned off, and the voltage of the pull-down node C is still maintained at a high level.

Since the pull-down nodes C are all low, the twelfth transistor M12 is in an off state, and the fourteenth transistor M14 outputs the first reference voltage to the light-emitting scanning output terminal Eout according to the second frequency under the control of the second pulse signal P2.

During the pull-up period Td2 in the data writing period Td, the first clock terminal CK1 stops outputting the first clock signal CLK1, and the first adjustment signal terminal Vin stops outputting the first adjustment signal. The first transistor M1 to the third transistor M3 are all in an off state.

The voltage of the first node A is maintained at a low level due to the action of the second capacitor C2, so that both the ninth transistor M9 and the seventh transistor M7 are turned on.

The second clock terminal CK2 outputs the second clock signal CLK2, the eighth transistor M8 and the tenth transistor M10 are turned on,

Therefore, the sub-pull-up control circuit 121 formed by the seventh transistor M7 and the eighth transistor M8 supplies the first reference voltage from the first reference voltage terminal VDD to the pull-up node B, and controls the voltage of the pull-up node B to keep at a high level. .

The sub-pull-down control circuit 122 composed of the ninth transistor M9 and the tenth transistor M10 transmits the low level of the second clock signal CLK2 to the pull-down node C, so that the voltage of the pull-down node C jumps from a high level to a low level.

When the voltage of the pull-down node C is at a low level, the twelfth transistor M12 is in an on state, whereby the first reference voltage terminal VDD provides the first reference voltage output to the optical scan output terminal Eout. At this time, the optical scan output terminal Eout is maintained at a high level and does not change with the second pulse signal P2.

During the pull-down period Td3 in the data writing period Td, the first clock terminal CK1 outputs the first clock signal CLK1, so that the first transistor M1 to the third transistor M3 in the first control circuit 11 are all turned off. The first node A is at a low level by loading the first reference voltage through the third transistor M3, and the pull-up node B is at a high level due to the input of the first adjustment signal.

When the voltage of the pull-up node B is at a low level, the voltage of the pull-down node C is controlled to jump to a high level through the eleventh transistor M11 that is turned on in the first inverting circuit 15, the twelfth transistor M12 is turned off, and the tenth transistor M12 is turned off. The four transistors M14 output the first reference voltage to the light-emitting scan output terminal Eout under the control of the second pulse signal P2.

It can be seen that in the data writing time period Td, the voltage of the light-emitting scan output terminal Eout is maintained at a high potential without opening the path of the driving current in the pixel unit P to make the light-emitting device emit light, thereby ensuring the correct writing of data.

During the light-emitting period Tr, the pull-up node B is kept at a low level under the control of the first clock signal CLK1 and the second clock signal CLK2.

The thirteenth transistor M13 outputs the second reference voltage to the light-emitting scan output terminal Eout according to the first frequency under the control of the first pulse signal P1, and the fourteenth transistor M14 outputs the second reference voltage according to the second frequency under the control of the second pulse signal P2. A reference voltage is applied to the light-emitting scan output terminal Eout.

It can be seen that during the light-emitting period, the duty cycle of the light-emitting signal EM can be flexibly adjusted at any time along with the first pulse signal P1 and the second pulse signal P2. The duty cycle of the pulse signal P1 and the second pulse signal P2 can accurately adjust the duty cycle of the light-emitting signal EM, that is, by adjusting the time of the low potential in the two pulse signals within one pulse period to accurately adjust the light-emitting signal EM. The low-potential time can effectively adjust the driving current time provided in the pixel unit P to the light-emitting device, thereby effectively preventing the stroboscopic phenomenon caused by the display frequency of the pixel unit P being unable to match the current image refresh frequency.

Please refer to FIG. 22 , which is a specific circuit structure diagram of the light-emitting driving circuit in any one of the scanning and lighting driving circuits 600 shown in FIG. 4 in the sixth embodiment of the present application. In this embodiment, the scanning and lighting driving circuit 600 is the same as that shown in FIG. The circuit structure of the scanning shown in 20 is basically the same as that of the light-emitting driving circuit 500 , the only difference being that all the transistors (the first transistor M1 to the fourteenth transistor M14 ) in the light-emitting circuit are N-type thin film transistors.

In this embodiment, the first transistor M1 to the eleventh transistor M11 are all N-type thin film transistors (TFTs), so the first potential is a high potential, the second potential is a low potential, and the first reference voltage is a high voltage, The second reference voltage is a low level. The first transistor M1 to the fourteenth transistor M14 are turned off under low voltage control, and turned on under high voltage control. It should be noted that, since the first reference voltage is a high voltage and the second reference voltage is a low potential, the scan signal Sc with the first reference voltage is used as the scan turn-on voltage of the pixel unit P, thus, the pixel unit P The pixel transistor that receives the scan signal Sc should be an N-type TFT that is turned on at a high potential. When the light-emitting signal EM has the first reference voltage, it is used as the light-emitting turn-on voltage of the pixel unit P. Therefore, the pixel unit P receives the light-emitting signal Sc. The pixel transistor should be an N-type TFT that is turned on at a high potential.

Please refer to FIG. 23 , which is a timing diagram of the light-emitting driving circuit shown in FIG. 22 when working. The operation sequence of the light-emitting driving circuit is exactly the same as that of the light-emitting driving circuit shown in FIG. 21 , which will not be repeated in this embodiment.

The above is the preferred embodiment of the application. It should be pointed out that for those skilled in the art, without departing from the principles of the application, several improvements and modifications can be made, and these improvements and modifications may also be regarded as The protection scope of this application.

Claims (23)

1. A scanning and light-emitting driving circuit, characterized in that, comprising a first control circuit, a second control circuit, a scanning driving output circuit and a light-emitting driving output circuit, The first control circuit is electrically connected to the scan drive output circuit and the light-emitting drive output circuit, and is used for controlling the scan drive output circuit to output a scan signal during the data writing time period in one scan cycle, and the scan signal uses receiving image data at the control pixel unit; The second control circuit is electrically connected to the light-emitting drive output circuit, and is used for controlling the light-emitting drive output circuit to output a light-emitting signal during the light-emitting period in the scan period, and the light-emitting signal is used to control the pixel unit the time at which the image data is displayed; the first control circuit is electrically connected to the scan drive output circuit through a pull-down node and is also electrically connected to the light-emitting drive output circuit through a pull-up node; During the data writing period, the first control circuit receives a first clock signal, and adjusts the potential of the pull-down node and the potential of the pull-up node according to the first clock signal, and the light-emitting driving output circuit is in The pull-up node receives a second clock signal under the control of the potential of the pull-up node, and outputs a second reference voltage in the light-emitting signal according to the second clock signal, and the second reference voltage is used to control the pixel unit to stop displaying the image data; The second control circuit is electrically connected to the light-emitting drive output circuit through a pull-up node. During the light-emitting period, the second control circuit receives a third clock signal and adjusts the output circuit according to the third clock signal. the potential of the pull-up node, the light-emitting drive output circuit outputs a first reference voltage in the light-emitting signal under the control of the potential of the pull-up node, and the first reference voltage is used to control the display of the pixel unit the time of the image data. 2. The scanning and light-emitting driving circuit according to claim 1, wherein, The scan driver output circuit receives a pre-start scan signal and a second clock signal under the control of the potential of the pull-down node, and outputs the scan signal according to the pre-start scan signal and the second clock signal. 3 . The scanning and lighting driving circuit according to claim 2 , wherein the second control circuit is further electrically connected to the scanning driving output circuit through the pull-down node; 3 . During the lighting period, the second control circuit receives the third clock signal, and adjusts the potential of the pull-down node according to the third clock signal; During the light-emitting period, the scan drive output circuit stops outputting the scan signal under the control of the potential of the pull-down node. 4. The scanning and light-emitting driving circuit according to claim 3, wherein, When the voltage of the pull-up node is the second potential, the first control circuit controls the voltage of the pull-down node to be the first potential; When the voltage of the pull-up node is at the first potential, the pull-down node is controlled to be at the second potential by a first inverting circuit connected between the pull-up node and the pull-down node. 5. The scanning and lighting driving circuit according to claim 4, wherein the lighting driving output circuit comprises: A light-emitting pull-up output circuit, a control terminal of the light-emitting pull-up output circuit is electrically connected to the pull-up node, an input terminal is electrically connected to the first reference voltage terminal, and the first reference voltage terminal is used to provide the the first reference voltage, the output end of the light-emitting pull-up output circuit is used to output the light-emitting signal, and in the light-emitting time period, under the control of the potential of the pull-up node, the light-emitting pull-up output circuit The output terminal of the output terminal outputs the first reference voltage; A light-emitting pull-down output circuit, a control terminal of the light-emitting pull-down output circuit is electrically connected to the pull-down node, an input terminal is electrically connected to a second reference voltage terminal, and the second reference voltage terminal is used for providing the second reference voltage , during the data writing period, under the control of the potential of the pull-down node, the output terminal of the light-emitting pull-down output circuit outputs the second reference voltage, and the light-emitting signal includes the first reference voltage and the the second reference voltage. 6. The scanning and light-emitting driving circuit according to claim 5, wherein the scanning driving output circuit comprises: a scan pull-up output circuit, the control terminal of the scan pull-up output circuit is electrically connected to the pull-up node, the input terminal is electrically connected to the second reference voltage terminal, and during the light-emitting period, on the Under the control of the potential of the pull-up node, the output end of the scan pull-up output circuit outputs a fourth reference voltage, and the fourth reference voltage is used to control the pixel unit to stop receiving the image data; a scan pull-down output circuit, a control terminal of the scan-pull output circuit is electrically connected to the pull-down node, an input terminal is electrically connected to a second clock terminal to receive the second clock signal, and an output terminal is electrically connected to the scan signal output terminal, during the data writing period, under the control of the potential of the pull-down node, the output terminal of the scan pull-up output circuit outputs a third reference voltage, and the third reference voltage is used to control the pixel a unit to receive the image data; The scan signal includes the third reference voltage and the fourth reference voltage. 7 . The scanning and lighting driving circuit according to claim 6 , wherein the scanning and lighting driving circuit further comprises a pulse width control circuit, and the pulse width control circuit is electrically connected to the lighting driving output circuit, 8 . For controlling the frequency of the light-emitting pull-up output unit to output the first reference voltage and the frequency of the light-emitting pull-down output unit to output the second reference voltage in the light-emitting signal, and the first reference voltage and The frequency of the output of the second reference voltage is the same and the number of times of outputting the first reference voltage in the light-emitting period is greater than 1. 8. The scanning and lighting driving circuit according to claim 7, wherein the pulse width control circuit comprises a first pulse width control circuit and a second pulse width control circuit; The control terminal of the first pulse width control circuit receives a first pulse width signal with a first duty cycle, the input terminal is electrically connected to the first reference voltage terminal, and the output terminal is electrically connected to the light-emitting pull-up output circuit; The first pulse width control circuit is turned on under the control of a first pulse width signal, and in the light-emitting period, when the first pulse width control circuit is turned on, the first reference voltage passes through the first pulse a wide control circuit and output from the output end of the light-emitting pull-up output circuit; The control terminal of the second pulse width control circuit receives a second pulse width signal with a second duty cycle, the input terminal is electrically connected to the second reference voltage terminal, and the output terminal is electrically connected to the light-emitting pull-down output circuit. The second pulse width control circuit is turned on under the control of the second pulse width signal. During the data writing period, when the second pulse width control circuit is turned on, the second reference voltage is passed through the second reference voltage. a pulse width control circuit and output from the output end of the light-emitting pull-down output circuit; The sum of the first duty cycle and the second duty cycle is 1, and the phases of the first pulse width signal and the second pulse width signal are opposite. 9. The scanning and lighting driving circuit according to claim 8, wherein, The first pulse width control circuit includes a first pulse transistor, the gate of the first pulse transistor receives the first pulse control signal, and the source of the first pulse transistor is electrically connected to the first reference voltage terminal, the drain of the first pulse transistor is electrically connected to the input terminal of the light-emitting pull-up output circuit; The second pulse width control circuit includes a second pulse transistor, the gate of the second pulse tube receives the second pulse control signal, and the source of the second pulse transistor is electrically connected to the second reference The voltage terminal, the drain of the second pulse tube is electrically connected to the output terminal of the light-emitting pull-down output circuit. 10 . The scanning and lighting driving circuit according to claim 9 , wherein the scanning and lighting driving circuit further comprises a reset circuit, and the reset circuit is electrically connected between the pull-up node and the pull-down node. 11 . is used to control the potential of the pull-up node during the reset period, so that the light-emitting drive output circuit stops the light-emitting signal, and control the potential of the pull-down node, so that the scan drive output circuit stops outputting scan signal. 11. The scanning and light-emitting driving circuit according to claim 9, wherein, The first control circuit includes a first transistor, a third transistor and a first capacitor; The gate of the first transistor is used for receiving the first clock signal, and the drain of the first transistor is electrically connected to the pull-down node; The source of the third transistor is electrically connected to the second reference voltage terminal to receive the second reference voltage, and the drain of the third transistor is electrically connected to the pull-up node; The first capacitor is electrically connected between the first clock signal terminal and the pull-up node. 12. The scanning and light-emitting driving circuit according to claim 11, wherein, The second control circuit includes a double-gate transistor, wherein both gates of the double-gate transistor are electrically connected to a third clock terminal to receive the third clock signal, and the source of the double-gate transistor is The pole is electrically connected to the first reference voltage terminal, and the drain of the double-gate transistor is electrically connected to the pull-up node. 13. The scanning and lighting driving circuit according to claim 11, wherein, The light-emitting pull-up output circuit includes a fourth transistor, and the light-emitting pull-down output circuit includes a fifth transistor and a second capacitor; The gate of the fourth transistor is electrically connected to the control terminal of the light-emitting pull-up output circuit, the source of the fourth transistor is electrically connected to the input terminal of the light-emitting pull-up output circuit, and the fourth transistor The drain is electrically connected to the output end of the light-emitting pull-up output circuit; The gate of the fifth transistor is electrically connected to the control terminal of the light-emitting pull-down output circuit, the source of the fourth transistor is electrically connected to the input terminal of the light-emitting pull-down output circuit, and the drain of the fifth transistor is electrically connected to the input terminal of the light-emitting pull-down output circuit. the pole is electrically connected to the output end of the light-emitting pull-down output circuit; The second capacitor is electrically connected between the pull-down node and the second reference voltage terminal. 14. The scanning and light-emitting driving circuit according to claim 11, wherein, The first inverter circuit includes a sixth transistor, the gate of the sixth transistor is electrically connected to the pull-up node, the source of the sixth transistor is electrically connected to the second reference voltage terminal, the drain of the sixth transistor is electrically connected to the pull-down node; When the sixth transistor is turned on under the control of the pull-up node, the sixth transistor controls the voltage of the pull-down node to be the same second potential as the second reference voltage. 15. The scanning and light-emitting driving circuit according to claim 11, wherein, The scan pull-up output circuit includes a seventh transistor, and the scan pull-down output circuit includes an eighth transistor, The gate of the seventh transistor is the control end of the scan pull-up output circuit, the source of the seventh transistor is the input end of the scan pull-up output circuit, and the drain of the seventh transistor is the scan-up output circuit. Pull the output of the output circuit; The gate of the eighth transistor is the control end of the scan pull-down output circuit, the source of the eighth transistor is the input end of the scan pull-down output circuit, and the drain of the eighth transistor is the scan pull-down output circuit 's output. 16. The scanning and lighting driving circuit according to claim 10, wherein, The reset circuit includes a tenth transistor and an eleventh transistor; The gate of the tenth transistor is electrically connected to the reset terminal to receive a reset signal, the source of the tenth transistor is electrically connected to the first reference voltage terminal, and the drain of the tenth transistor is electrically connected to the pull-up node; The gate of the eleventh transistor is electrically connected to the reset terminal to receive the reset signal, the source of the eleventh transistor is electrically connected to the second reference voltage terminal, and the eleventh transistor The drain of is electrically connected to the pull-down node. 17. A scanning and light-emitting driving system, comprising a multi-stage cascaded scanning and light-emitting driving circuit as claimed in claim 16, wherein the scanning signal output terminal of the n-1th stage scanning and light-emitting driving circuit is electrically connected The first control circuit of the scanning and light-emitting driving circuit of the nth stage, and the scanning signal output by the scanning and light-emitting driving circuit of the n-1th stage is used as the pre-start scanning signal, and the n is an integer greater than 1; The first control circuit includes a first transistor, a third transistor and a first capacitor; The gate of the first transistor is used to receive the first clock signal, and the source of the first transistor is electrically connected to the scan signal output end of the scan and light-emitting drive circuit of the n-1th stage, so the drain of the first transistor is electrically connected to the pull-down node; The gate of the third transistor is electrically connected to the scan signal output terminal of the scan and light-emitting driving circuit of the n-1th stage, and the source of the third transistor is electrically connected to the second reference voltage terminal to receive the the second reference voltage, the drain of the third transistor is electrically connected to the pull-up node; The first capacitor is electrically connected between the first clock signal terminal and the pull-up node. 18. A display panel, wherein a non-display area of the display panel comprises the scanning and light-emitting driving circuit according to any one of claims 1-17. 19. A scanning and light-emitting driving circuit, which is characterized in that it comprises a light-emitting driving circuit and a pulse width control circuit, the light-emitting driving circuit is used to output a light-emitting signal, and the light-emitting signal is used to control the time when a pixel unit displays image data, The pulse width control circuit is electrically connected to the light-emitting driving circuit, and is used for controlling the frequency of the light-emitting driving circuit outputting the light-emitting signal, wherein the light-emitting driving circuit includes: The first control circuit electrically connects the pull-up output circuit and the pull-down output circuit through the pull-up node, and controls the voltage of the pull-up node according to the received first clock signal during the data writing period in one scan cycle, so that the pull-up node is outputting a first reference voltage when the output circuit is pulled, and the first reference voltage controls the pixel unit to stop displaying image data; The second control circuit is electrically connected to the pull-up output circuit through the pull-up node, and outputs a second reference voltage according to the received second clock signal during the light-emitting period in the scan period, and the second reference voltage is used to control the The pixel unit displays image data, and the light-emitting signal includes the first reference voltage and the second reference voltage; The pulse width control circuit is electrically connected to the light-emitting driving circuit, and is used for controlling the frequency at which the pull-up output circuit outputs the first reference voltage and the frequency at which the pull-down output circuit outputs the second reference voltage, In addition, the output frequency of the first reference voltage and the second reference voltage is the same, and the number of times of outputting the first reference voltage in the light-emitting period is greater than 1. 20. The scanning and lighting driving circuit according to claim 19, wherein the lighting driving circuit comprises a first pulse width control circuit and a second pulse width control circuit, The control terminal of the first pulse width control circuit receives a first pulse width signal with a first duty cycle, the input terminal is electrically connected to the first reference voltage terminal, and the output terminal is electrically connected to the light-emitting driving circuit for outputting The light-emitting pull-up output circuit of the light-emitting signal, the first pulse-width control circuit is turned on according to the first frequency under the control of the first pulse-width signal, and when the first pulse-width control circuit is turned on during the light-emitting period When turned on, the first reference voltage is output to the light-emitting signal output end via the input end, the output end, the output end and the light-emitting pull-up output end circuit of the first pulse width control circuit; The control terminal of the second pulse width control circuit receives a second pulse width signal with a second duty cycle, the input terminal is electrically connected to the second reference voltage terminal, the output terminal is electrically connected to the light-emitting signal output terminal, and the output terminal is electrically connected to the light-emitting signal output terminal. The second pulse width control circuit is turned on according to the second frequency under the control of the second pulse width signal. The input end and the output end of the wide control circuit are output to the light-emitting signal output end; The sum of the first duty cycle and the second duty cycle is 1, and the phases of the first pulse width signal and the second pulse width signal are opposite. 21. The scanning and lighting driving circuit according to claim 20, wherein, The pull-up output circuit includes a fourth transistor, the gate of the fourth transistor is electrically connected to the pull-up node, and the source of the fourth transistor is electrically connected to the first pulse width control circuit, so the drain of the fourth transistor is electrically connected to the light-emitting signal output end; The first control circuit is electrically connected to the light-emitting driving output circuit through a pull-up node, the pull-down output circuit includes a twelfth transistor and a third capacitor, and the third capacitor is electrically connected to the pull-down node and the between the first reference voltage terminals, the first reference voltage terminal provides the first reference voltage; The gate of the twelfth transistor is electrically connected to the pull-down node, the source of the twelfth transistor is electrically connected to the first reference voltage terminal, the second reference voltage terminal provides the second reference voltage, and the The drain of the twelfth transistor is electrically connected to the light-emitting signal output terminal. 22. The scanning and lighting driving circuit according to claim 21, wherein, The first pulse width control circuit includes a first pulse transistor, the gate of the first pulse transistor is electrically connected to the first pulse signal output terminal to receive the first pulse control signal, and the source of the first pulse transistor is electrically connected. is electrically connected to the second reference voltage terminal, and the drain of the first pulse transistor is electrically connected to the drain of the fourth transistor; The second pulse width control circuit includes a second pulse transistor, the gate of the second pulse transistor is electrically connected to the second pulse signal output terminal to receive the second pulse control signal, and the source of the second pulse transistor is electrically connected. is electrically connected to the first reference voltage terminal, and the drain of the second pulse transistor is electrically connected to the light-emitting signal output terminal. 23. A display panel, wherein a non-display area of the display panel comprises the scanning and light-emitting driving circuit according to any one of claims 19-22.

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