CN113013238A - Surrounding field effect transistor of low-dielectric-constant inner spacer layer - Google Patents

Surrounding field effect transistor of low-dielectric-constant inner spacer layer Download PDF

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CN113013238A
CN113013238A CN202110205210.4A CN202110205210A CN113013238A CN 113013238 A CN113013238 A CN 113013238A CN 202110205210 A CN202110205210 A CN 202110205210A CN 113013238 A CN113013238 A CN 113013238A
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stacked structure
gate
metal
field effect
silicon substrate
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翁文寅
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/018—Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates

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  • Junction Field-Effect Transistors (AREA)

Abstract

本发明提供一种低介电常数内间隔层的环绕式场效电晶管，至少包括硅基底、位于硅基底上的栅极；栅极包括：叠层结构以及位于叠层结构上的金属栅；叠层结构由金属层和Si层相互交替堆叠而成；位于金属栅侧壁的侧墙；位于叠层结构侧壁的内侧墙；内侧墙包括依附于叠层结构中的金属层侧壁的SiOCN层；叠层结构中的所述Si层延伸至SiOCN层之间的区域；侧墙的边缘沿所述叠层结构由上至下延伸至所述硅基底上。本发明采用低介电常数材料作为GAAFET的栅极侧墙和内间隔层，有效降低器件的电容，并提高器件的性能。

Figure 202110205210

The invention provides a wraparound field effect transistor with a low dielectric constant inner spacer layer, which at least comprises a silicon substrate and a gate on the silicon substrate; the gate comprises: a stacked structure and a metal gate on the stacked structure ; The stacked structure is formed by alternately stacking metal layers and Si layers; the side wall is located on the side wall of the metal gate; the inner side wall is located on the side wall of the stacked structure; SiOCN layer; the Si layer in the stacked structure extends to the area between the SiOCN layers; the edge of the sidewall extends from top to bottom along the stacked structure to the silicon substrate. The invention adopts low dielectric constant material as the gate sidewall and inner spacer layer of GAAFET, which effectively reduces the capacitance of the device and improves the performance of the device.

Figure 202110205210

Description

Surrounding field effect transistor of low-dielectric-constant inner spacer layer
Technical Field
The invention relates to the technical field of semiconductors, in particular to a surrounding field effect transistor with an inner spacer layer with a low dielectric constant.
Background
For gate-all-around field effect transistors (GAAFETs), the inner spacer layer is usually made of high-k material, such as SiN material, which is often used for gate sidewall and inner spacer layers of GAAFETs in the prior art, and this high-k material may cause the capacitance of GAAFET to increase, thereby further reducing the performance of the device.
Therefore, it is necessary to provide a new structure to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a wraparound field effect transistor with low-k inner spacers, which is used to solve the problem of the prior art that the performance of the device is reduced due to the increase of the capacitance of the device caused by the high-k material used for the inner spacers of the GAAFET.
To achieve the above and other related objects, the present invention provides a wraparound fet with low-k spacers, comprising:
the silicon substrate, locate at grid on the said silicon substrate; the gate includes: the metal gate structure comprises a laminated structure and a metal gate positioned on the laminated structure; the laminated structure is formed by alternately stacking metal layers and Si layers; the side wall is positioned on the side wall of the metal gate; the inner side wall is positioned on the side wall of the laminated structure; the inner sidewall comprises a SiOCN layer attached to the side wall of the metal layer in the laminated structure; the Si layers in the stacked structure extend to regions between the SiOCN layers;
the edge of the side wall extends to the silicon substrate from top to bottom along the laminated structure.
The invention also provides a surrounding field effect transistor of the low dielectric constant inner spacer layer, which is characterized by at least comprising:
the silicon substrate, locate at grid on the said silicon substrate; the gate includes: the metal gate structure comprises a laminated structure and a metal gate positioned on the laminated structure; the laminated structure is formed by alternately stacking metal layers and Si layers; the side wall is positioned on the side wall of the metal gate; the inner side wall is positioned on the side wall of the laminated structure; the inner side wall comprises a SiBCN layer attached to the side wall of the metal layer in the laminated structure; the Si layers in the stacked structure extend to regions between the SiBCN layers;
the edge of the side wall extends to the silicon substrate from top to bottom along the laminated structure.
Preferably, the side wall of the metal gate is SiBCN.
Preferably, the material of the metal gate is tungsten.
Preferably, the material of the metal layer in the stacked structure is tungsten.
Preferably, the silicon substrate further comprises source and drain terminals located on the silicon substrate on two sides of the grid electrode.
As described above, the wraparound fet with the low-k inner spacer layer according to the present invention has the following advantages: the invention adopts the low dielectric constant material as the gate side wall and the inner spacing layer of the GAAFET, thereby effectively reducing the capacitance of the device and improving the performance of the device.
Drawings
FIG. 1 is a schematic diagram of a wrap-around FET without a metal gate fill according to the present invention;
FIG. 2 is a schematic view of a wraparound FET structure with low-k inner spacers according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-2. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
The invention provides a surrounding field effect transistor of an inner spacer layer with low dielectric constant, which at least comprises:
the silicon substrate, locate at grid on the said silicon substrate; the gate includes: the metal gate structure comprises a laminated structure and a metal gate positioned on the laminated structure; the laminated structure is formed by alternately stacking metal layers and Si layers; the side wall is positioned on the side wall of the metal gate; the inner side wall is positioned on the side wall of the laminated structure; the inner sidewall comprises a SiOCN layer attached to the side wall of the metal layer in the laminated structure; the Si layers in the stacked structure extend to regions between the SiOCN layers; the edge of the side wall extends to the silicon substrate from top to bottom along the laminated structure.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a wrap-around fet without a metal gate filling according to the present invention.
As shown in fig. 1, the wraparound fet with low-k inner spacers of the present invention at least comprises: the silicon substrate 01, the grid located on said silicon substrate 01; the gate includes: the metal gate structure comprises a laminated structure and a metal gate positioned on the laminated structure; wherein the metal gate is not shown in fig. 1, and the stacked structure is formed by alternately stacking metal layers and Si layers; fig. 1 does not show the metal layers in the stack; FIG. 2 is a schematic view of a wraparound FET structure with low-k inner spacers according to the present invention. The Si layer 02 in the stacked structure in fig. 2 overlaps the metal layer 03, and on the stacked structure is the metal gate 04.
As shown in fig. 1, the wraparound fet of the low-k inner spacer further includes: the side wall 05 is positioned on the side wall of the metal gate 04; the inner side wall is positioned on the side wall of the laminated structure; the inner sidewall includes a SiOCN layer 08 attached to the metal layer sidewall in the stack; as shown in fig. 1, the Si layer 02 in the stacked structure extends to a region between the SiOCN layers 08; the edge of the side wall extends to the silicon substrate 01 from top to bottom along the laminated structure.
Further, the sidewall 04 of the side wall of the metal gate is SiOCN.
In this embodiment, the metal gate is made of tungsten.
Still further, the material of the metal layer in the stacked structure in this embodiment is tungsten.
The surrounding field effect transistor of the low dielectric constant inner spacer layer further comprises a source drain terminal 06 located on the silicon substrate at two sides of the gate. Further, an interlayer dielectric layer 07 is deposited on the source/drain terminal 06 and the gate in this embodiment.
Example two
The invention provides a surrounding field effect transistor of an inner spacer layer with low dielectric constant, which at least comprises:
the silicon substrate, locate at grid on the said silicon substrate; the gate includes: the metal gate structure comprises a laminated structure and a metal gate positioned on the laminated structure; the laminated structure is formed by alternately stacking metal layers and Si layers; the side wall is positioned on the side wall of the metal gate; the inner side wall is positioned on the side wall of the laminated structure; the inner side wall comprises a SiBCN layer attached to the side wall of the metal layer in the laminated structure; the Si layers in the stacked structure extend to regions between the SiBCN layers; the edge of the side wall extends to the silicon substrate from top to bottom along the laminated structure.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a wrap-around fet without a metal gate filling according to the present invention.
As shown in fig. 1, the wraparound fet with low-k inner spacers of the present invention at least comprises: the silicon substrate 01, the grid located on said silicon substrate 01; the gate includes: the metal gate structure comprises a laminated structure and a metal gate positioned on the laminated structure; wherein the metal gate is not shown in fig. 1, and the stacked structure is formed by alternately stacking metal layers and Si layers; fig. 1 does not show the metal layers in the stack; FIG. 2 is a schematic view of a wraparound FET structure with low-k inner spacers according to the present invention. The Si layer 02 in the stacked structure in fig. 2 overlaps the metal layer 03, and on the stacked structure is the metal gate 04.
As shown in fig. 1, the wraparound fet of the low-k inner spacer further includes: the side wall 05 is positioned on the side wall of the metal gate 04; the inner side wall is positioned on the side wall of the laminated structure; the inner side wall comprises a SiBCN layer attached to the side wall of the metal layer in the laminated structure; as shown in fig. 1, the Si layer 02 in the stacked structure extends to the region between the SiBCN layers; the edge of the side wall extends to the silicon substrate 01 from top to bottom along the laminated structure.
Further, the side wall of the metal gate is SiBCN.
In this embodiment, the metal gate is made of tungsten.
Still further, the material of the metal layer in the stacked structure in this embodiment is tungsten.
The surrounding field effect transistor of the low dielectric constant inner spacer layer further comprises a source drain terminal 06 located on the silicon substrate at two sides of the gate. Further, an interlayer dielectric layer 07 is deposited on the source/drain terminal 06 and the gate in this embodiment.
In summary, the invention uses low dielectric constant material as the gate sidewall and the inner spacer of the GAAFET, so as to effectively reduce the capacitance of the device and improve the performance of the device. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1.一种低介电常数内间隔层的环绕式场效电晶管，其特征在于，至少包括：1. A wraparound field effect transistor of a low dielectric constant inner spacer layer, characterized in that, at least comprising: 硅基底、位于所述硅基底上的栅极；所述栅极包括：叠层结构以及位于所述叠层结构上的金属栅；所述叠层结构由金属层和Si层相互交替堆叠而成；位于所述金属栅侧壁的侧墙；位于所述叠层结构侧壁的内侧墙；所述内侧墙包括依附于所述叠层结构中的所述金属层侧壁的SiOCN层；所述叠层结构中的所述Si层延伸至所述SiOCN层之间的区域；A silicon substrate and a gate on the silicon substrate; the gate comprises: a stacked structure and a metal gate on the stacked structure; the stacked structure is formed by alternately stacking metal layers and Si layers ; The sidewall on the sidewall of the metal grid; the inner sidewall on the sidewall of the stacked structure; the inner sidewall includes a SiOCN layer attached to the sidewall of the metal layer in the stacked structure; the the Si layer in the stacked structure extends to the region between the SiOCN layers; 所述侧墙的边缘沿所述叠层结构由上至下延伸至所述硅基底上。The edge of the spacer extends from top to bottom along the stacked structure onto the silicon substrate. 2.根据权利要求1所述的低介电常数内间隔层的环绕式场效电晶管，其特征在于：所述金属栅侧壁的侧墙为SiOCN。2 . The wraparound field effect transistor with low dielectric constant inner spacer layer according to claim 1 , wherein the sidewalls of the sidewalls of the metal gate are SiOCN. 3 . 3.根据权利要求1所述的低介电常数内间隔层的环绕式场效电晶管，其特征在于：所述金属栅的材料为钨。3 . The wraparound field effect transistor with low dielectric constant inner spacer layer according to claim 1 , wherein the material of the metal gate is tungsten. 4 . 4.根据权利要求1所述的低介电常数内间隔层的环绕式场效电晶管，其特征在于：所述叠层结构中的所述金属层的材料为钨。4 . The wraparound field effect transistor with low dielectric constant inner spacer layer according to claim 1 , wherein the material of the metal layer in the stacked structure is tungsten. 5 . 5.根据权利要求1所述的低介电常数内间隔层的环绕式场效电晶管，其特征在于：还包括位于所述栅极两侧的所述硅基底上的源漏端。5 . The wraparound field effect transistor with low dielectric constant inner spacer layer according to claim 1 , further comprising source and drain terminals on the silicon substrate on both sides of the gate electrode. 6 . 6.一种低介电常数内间隔层的环绕式场效电晶管，其特征在于，至少包括：6. A wraparound field effect transistor with a low dielectric constant inner spacer layer, characterized in that it at least comprises: 硅基底、位于所述硅基底上的栅极；所述栅极包括：叠层结构以及位于所述叠层结构上的金属栅；所述叠层结构由金属层和Si层相互交替堆叠而成；位于所述金属栅侧壁的侧墙；位于所述叠层结构侧壁的内侧墙；所述内侧墙包括依附于所述叠层结构中的所述金属层侧壁的SiBCN层；所述叠层结构中的所述Si层延伸至所述SiBCN层之间的区域；A silicon substrate and a gate on the silicon substrate; the gate comprises: a stacked structure and a metal gate on the stacked structure; the stacked structure is formed by alternately stacking metal layers and Si layers ; Spacers located on the sidewalls of the metal gates; Internal sidewalls located on the sidewalls of the stacked structure; The internal sidewalls include a SiBCN layer attached to the sidewalls of the metal layers in the stacked structure; the the Si layer in the stacked structure extends to the region between the SiBCN layers; 所述侧墙的边缘沿所述叠层结构由上至下延伸至所述硅基底上。The edge of the spacer extends from top to bottom along the stacked structure onto the silicon substrate. 7.根据权利要求6所述的低介电常数内间隔层的环绕式场效电晶管，其特征在于：所述金属栅侧壁的侧墙为SiBCN。7 . The wraparound field effect transistor with low dielectric constant inner spacer layer according to claim 6 , wherein the sidewalls of the sidewalls of the metal gate are SiBCN. 8 . 8.根据权利要求6所述的低介电常数内间隔层的环绕式场效电晶管，其特征在于：所述金属栅的材料为钨。8 . The wraparound field effect transistor with low dielectric constant inner spacer layer according to claim 6 , wherein the material of the metal gate is tungsten. 9 . 9.根据权利要求6所述的低介电常数内间隔层的环绕式场效电晶管，其特征在于：所述叠层结构中的所述金属层的材料为钨。9 . The wraparound field effect transistor with low dielectric constant inner spacer layer according to claim 6 , wherein the material of the metal layer in the stacked structure is tungsten. 10 . 10.根据权利要求6所述的低介电常数内间隔层的环绕式场效电晶管，其特征在于：还包括位于所述栅极两侧的所述硅基底上的源漏端。10 . The wraparound field effect transistor with low dielectric constant inner spacer layer according to claim 6 , further comprising source and drain terminals on the silicon substrate on both sides of the gate electrode. 11 .
CN202110205210.4A 2021-02-24 2021-02-24 Surrounding field effect transistor of low-dielectric-constant inner spacer layer Pending CN113013238A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108573925A (en) * 2017-03-10 2018-09-25 三星电子株式会社 Semiconductor devices and method for manufacturing it
US20200083352A1 (en) * 2018-09-06 2020-03-12 Globalfoundries Inc. Gate-all-around field effect transistors with air-gap inner spacers and methods

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108573925A (en) * 2017-03-10 2018-09-25 三星电子株式会社 Semiconductor devices and method for manufacturing it
US20200083352A1 (en) * 2018-09-06 2020-03-12 Globalfoundries Inc. Gate-all-around field effect transistors with air-gap inner spacers and methods

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Application publication date: 20210622