CN112614787A

CN112614787A - Packaging method for chip packaging

Info

Publication number: CN112614787A
Application number: CN202011617859.9A
Authority: CN
Inventors: 谭小春
Original assignee: Hefei Silicon Microelectronics Technology Co ltd
Current assignee: Hefei Silicon Microelectronics Technology Co ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-04-06
Anticipated expiration: 2040-12-31
Also published as: CN112614787B

Abstract

The invention provides a packaging method of chip packaging, which comprises the steps of carrying out primary Bump on parasitic capacitance on a chip on a wafer to form a first metal Bump, carrying out secondary Bump on the first metal Bump to form a second metal Bump, wherein an annular recess is formed between the first metal Bump and the second metal Bump, and carrying out subsequent conventional chip packaging operation flow on the chip with the first metal Bump and the second metal Bump. First metal salient points and second metal salient points are formed through the first Bump and the second Bump, annular depressions are formed between the first metal salient points and the second metal salient points, the first metal salient points and the second metal salient points can be well combined with a plastic package body during plastic package, the plastic package body can be buckled by the annular depressions, the contact area between the plastic package body and the annular depressions is increased, the bonding degree is increased, the first metal salient points, the second metal salient points and the plastic package body are not prone to being separated during grinding, the probability of separation between the first metal salient points and parasitic capacitors is also reduced, and the reliability of a chip is improved.

Description

Packaging method for chip packaging

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a packaging method for chip packaging.

Background

With the development of electronic products, semiconductor technology has been widely used to manufacture memory, Central Processing Unit (CPU), Liquid Crystal Display (LCD), Light Emitting Diode (LED), laser diode, and other devices or chip sets.

Since electronic components such as semiconductor components, micro-electromechanical components (MEMS) or optoelectronic components have minute and fine circuits and structures, in order to prevent dust, acid-base substances, moisture, oxygen, etc. from contaminating or eroding the electronic components, thereby affecting their reliability and life, it is necessary to provide the electronic components with related functions such as electrical energy creation, signal transmission, heat dissipation, protection and support, etc. by packaging technology.

The semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a functional requirement to obtain an independent chip. The packaging process comprises the following steps: a wafer from a wafer previous process is cut into small chips (Die) through a scribing process, then the cut chips are pasted on small islands of corresponding substrate (Lead frame) frames through glue, and bonding pads (Bond pads) of the chips are connected to corresponding pins (Lead) of the substrate through superfine metal (gold tin copper aluminum) wires or conductive resin to form a required circuit; and then packaging and protecting the independent wafer by using a plastic shell, carrying out a series of operations after plastic packaging, carrying out finished product testing after packaging, generally carrying out procedures such as inspection, Test, packaging and the like, and finally warehousing and shipping.

In the field of chip packaging, before a chip is packaged, Bump processing needs to be performed on the chip on a wafer, namely, a metal Bump is arranged on a parasitic capacitor of the chip, and then subsequent packaging operation is performed, but the existing Bump processing is that a metal Bump is directly arranged on the parasitic capacitor of the chip on the wafer, after plastic packaging, the metal Bump is easily separated from the chip due to the influence of the subsequent process, and particularly generated in the grinding process of a plastic packaging body, so that the reliability of the chip is reduced, when the size control of the metal Bump and the adhesion degree between the metal Bump and the chip need to be considered, different problems need to be solved, for example, when the density of parasitic capacitors on the chip is high, short circuit is easy to occur when RDL rewiring is formed, when the parasitic capacitors on the chip are low, the base surface between the metal Bump and the RDL rewiring is small, the adhesion is reduced, the circuit is easy to break, and the like, so that the difficulty requirement of the Bump process is greatly increased, and a solution for the phenomenon needs to be provided urgently.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides a packaging method for chip packaging.

In order to solve the problems, the technical scheme adopted by the invention is as follows:

a packaging method of chip packaging comprises the steps of conducting primary Bump on parasitic capacitance on a chip on a wafer to form a first metal Bump, conducting secondary Bump on the first metal Bump to form a second metal Bump, forming an annular recess between the first metal Bump and the second metal Bump, and conducting subsequent conventional chip packaging operation flow on the chip with the first metal Bump and the second metal Bump.

Furthermore, the parasitic capacitance on the chip is completely covered by the first metal salient point, and the cohesiveness is improved.

Furthermore, the first metal bump and the second metal bump are positioned on the same axis, and the axis is vertical to the surface formed by the wafer on which the chip is positioned.

Further, in the secondary Bump, the size of the second metal Bump is designed to be the same as, larger than or smaller than that of the first metal Bump.

Furthermore, on the same wafer, a primary Bump and a secondary Bump are performed on the same parasitic capacitor in sequence, and then a primary Bump and a secondary Bump operation of the next parasitic capacitor are performed.

Furthermore, on the same wafer, after performing Bump on all parasitic capacitors on the wafer once, performing Bump operation twice.

Compared with the prior art, the invention has the following beneficial effects: first metal salient points and second metal salient points are formed through the first Bump and the second Bump, annular depressions are formed between the first metal salient points and the second metal salient points, the first metal salient points and the second metal salient points can be well combined with a plastic package body during plastic package, the plastic package body can be buckled by the annular depressions, the contact area between the plastic package body and the annular depressions is increased, the bonding degree is increased, the first metal salient points, the second metal salient points and the plastic package body are not prone to being separated during grinding, the probability of separation between the first metal salient points and parasitic capacitors is also reduced, and the reliability of a chip is improved.

When the parasitic capacitance on the chip to be packaged is very tight, the first metal Bump is tightly attached to the parasitic capacitance and completely covered, the connection effectiveness between the first metal Bump and the parasitic capacitance is ensured, then the size of the second metal Bump is reduced, the distance between the adjacent second metal bumps is increased, when RDL (radio frequency link) rewiring is carried out, the phenomenon of short circuit of the adjacent second metal bumps can be effectively avoided, the reliability of the chip is increased, and the yield of products is improved;

in order to ensure the high efficiency of high-speed signals of a chip, the parasitic capacitance on a packaged chip is generally required to be designed to be very small, when the parasitic capacitance is very small, the first metal Bump covering the chip is very small, the size of the second metal Bump generated by secondary Bump is enlarged, so that the contact area between the second metal Bump and RDL rewiring is increased, the connection effectiveness can be ensured, the second metal Bump is not easy to break, the phenomenon of breaking the chip is avoided, the reliability of the chip is increased, and the yield of products is improved.

Drawings

Fig. 1 is a schematic structural diagram of a first metal bump, a second metal bump and a chip according to a first embodiment;

FIG. 2 is a schematic diagram of a chip package according to an embodiment;

fig. 3 is a schematic structural diagram of the first metal bump, the second metal bump and the chip according to the second embodiment;

FIG. 4 is a diagram illustrating a chip package according to a second embodiment;

fig. 5 is a schematic structural diagram of the first metal bump, the second metal bump, and the chip in the third embodiment;

fig. 6 is a schematic structural diagram of a chip package according to a third embodiment.

Detailed Description

The present invention will now be described in connection with particular embodiments, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar components or components having the same or similar functionality throughout.

The directional phrases used in this disclosure include, for example: upper, lower, left, right, front, rear, inner, outer, front, rear, side, etc. are directions with reference to the drawings only, and the embodiments described below by referring to the drawings and directional terms used are exemplary only for explaining the present invention, and are not to be construed as limiting the present invention. In addition, the present invention provides examples of various specific processes and materials that one of ordinary skill in the art would recognize for other processes and/or uses of other materials.

The first embodiment is as follows:

referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of a first metal bump, a second metal bump and a chip according to a first embodiment; fig. 2 is a schematic structural diagram of a chip package according to an embodiment.

A packaging method of chip packaging is to perform Bump on a parasitic capacitor 11 on a chip 10 on a wafer a once to form a first metal Bump 20, wherein the parasitic capacitor 11 on the chip 10 is completely covered by the first metal Bump 20 to increase the cohesiveness.

Performing secondary Bump on the first metal Bump 20 to form a second metal Bump 30, wherein the first metal Bump 20 and the second metal Bump 30 are located on the same axis, and the axis is perpendicular to the surface formed by the wafer a where the chip 10 is located, so that operation and setting of process parameters are facilitated, and production efficiency is improved.

Annular sunken b has between first metal bump 20 and the second metal bump 30, and first metal bump 20 is the same with second metal bump 30's size, in same space size, design annular sunken b can increase the connection face between first metal bump 20 and the second metal bump 30 and the plastic-sealed material, as shown in fig. 2, thereby increase its steadiness and cohesiveness, when preventing to grind in the later stage, lead to breaking away from between first metal bump 20 and the second metal bump 30 and the plastic-sealed material, also reduce their probability that leads to disconnection between first metal bump 20 and the chip 10 because of the external force of grinding, thereby improve the reliability of chip, improve the product yield.

The first metal bump 20 and the second metal bump 30 are designed to have the same size, so that the production efficiency is improved, and the defective products are reduced.

For different wafer characteristics and different metals as raw materials of the primary Bump and the secondary Bump, the raw materials of the primary Bump and the secondary Bump may be the same or different, and on the same wafer a, the primary Bump and the secondary Bump are performed successively for the same parasitic capacitor 11, and then the primary Bump and the secondary Bump operation of the next parasitic capacitor 11 are performed, or after the primary Bump is performed on all the parasitic capacitors 11 on the wafer a, the secondary Bump operation is performed again.

The chip 10 with the first metal bumps 20 and the second metal bumps 30 is subjected to a subsequent chip conventional packaging operation flow, such as flip-chip packaging, fan-out packaging and the like.

Example two:

please refer to fig. 3 and fig. 4, wherein fig. 3 is a schematic structural diagram of the first metal bump, the second metal bump and the chip according to the second embodiment; fig. 4 is a schematic structural diagram of a chip package according to a second embodiment.

The operation of this embodiment is the same as that of the first embodiment, and the only difference is as follows: during secondary Bump, the size of the second metal Bump 30 is designed to be smaller than that of the first metal Bump 20, when the parasitic capacitor 11 on the chip 10 to be packaged is very tight, as shown in fig. 4, the first metal Bump 20 is tightly attached to the parasitic capacitor 11 and completely covered, so that the connection effectiveness between the first metal Bump 20 and the parasitic capacitor 11 is ensured, then the size of the second metal Bump 30 is reduced, the distance between adjacent second metal bumps 30 is increased, when RDL is rewired, the phenomenon that the adjacent second metal bumps 30 are short-circuited can be effectively avoided, the reliability of the chip 10 is increased, and the product yield is improved.

Example three:

please refer to fig. 5 and fig. 6, wherein fig. 5 is a schematic structural diagram of the first metal bump, the second metal bump and the chip according to the third embodiment; fig. 6 is a schematic structural diagram of a chip package according to a third embodiment.

The operation of this embodiment is the same as that of the first embodiment, and the only difference is as follows: in the case of secondary Bump, the size of the second metal Bump 30 is designed to be larger than that of the first metal Bump 20, in order to ensure high-speed signal efficiency of the chip 10, the parasitic capacitor 11 on the packaged chip 10 generally needs to be designed to be very small, and when the parasitic capacitor 11 is very small, the first metal Bump 20 covering the parasitic capacitor is very small.

Compared with the prior art, the invention has the following beneficial effects:

first metal salient points and second metal salient points are formed through the first Bump and the second Bump, annular depressions are formed between the first metal salient points and the second metal salient points, the first metal salient points and the second metal salient points can be well combined with a plastic package body during plastic package, the plastic package body can be buckled by the annular depressions, the contact area between the plastic package body and the annular depressions is increased, the bonding degree is increased, the first metal salient points, the second metal salient points and the plastic package body are not prone to being separated during grinding, the probability of separation between the first metal salient points and parasitic capacitors is also reduced, and the reliability of a chip is improved.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. A packaging method of chip packaging is characterized in that primary Bump is carried out on a parasitic capacitor (11) on a chip (10) on a wafer (a) to form a first metal Bump (20), secondary Bump is carried out on the first metal Bump (20) to form a second metal Bump (30), an annular recess (b) is formed between the first metal Bump (20) and the second metal Bump (30), and the chip (10) with the first metal Bump (20) and the second metal Bump (30) is subjected to subsequent conventional chip packaging operation procedures.

2. The packaging method of the chip package according to claim 1, wherein the first metal bump (20) completely covers the parasitic capacitor (11) on the chip (10) to increase adhesion.

3. The method of claim 1, wherein the first metal bump (20) and the second metal bump (30) are located on a same axis, and the axis is perpendicular to a plane formed by a wafer (a) on which the chip (10) is located.

4. The method for packaging a chip package according to claim 1, wherein the size of the second metal Bump (30) is designed to be the same as the size of the first metal Bump (20), or larger than the size of the first metal Bump (20), or smaller than the size of the first metal Bump (20) at the time of the second Bump.

5. The method of claim 1, wherein the first Bump and the second Bump are performed on the same wafer (a) sequentially for the same parasitic capacitor (11), and then the first Bump and the second Bump are performed for the next parasitic capacitor (11).

6. The method of claim 1, wherein the Bump operation is performed on the same wafer (a) after performing a Bump operation on all parasitic capacitors (11) on the wafer (a).