CN112332667B - Current detection circuit of current mode buck-boost converter - Google Patents

Current detection circuit of current mode buck-boost converter Download PDF

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CN112332667B
CN112332667B CN202011171347.4A CN202011171347A CN112332667B CN 112332667 B CN112332667 B CN 112332667B CN 202011171347 A CN202011171347 A CN 202011171347A CN 112332667 B CN112332667 B CN 112332667B
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resistor
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CN112332667A (en
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奚冬杰
徐晴昊
李现坤
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CETC 58 Research Institute
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/20—Modifications of basic electric elements for use in electric measuring instruments; Structural combinations of such elements with such instruments
    • G01R1/203—Resistors used for electric measuring, e.g. decade resistors standards, resistors for comparators, series resistors, shunts
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/10—Measuring sum, difference or ratio
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

本发明公开一种电流模升降压变换器电流检测电路，属于模拟集成电路领域。在每个周期内，当电感电流峰值达到设定上限时，设置于浮动电源轨的脉宽调制比较器PWM输出无需经过电平位移模块延迟可直接关闭高侧功率管；利用高侧功率管的导通电阻进行电流采样，提升采样速度。本发明相比于传统峰值电流模控制的Buck‑Boost，能够实现电感电流的快速和高精度检测，且对高侧功率管的控制具有更高的稳定性，非常适合于高频工作条件的峰值电流模Buck‑Boost转换器。

Figure 202011171347

The invention discloses a current detection circuit of a current mode buck-boost converter, which belongs to the field of analog integrated circuits. In each cycle, when the peak value of the inductor current reaches the set upper limit, the PWM output of the pulse width modulation comparator set on the floating power rail can directly turn off the high-side power tube without going through the delay of the level shift module; The on-resistance performs current sampling to improve the sampling speed. Compared with the Buck-Boost controlled by the traditional peak current mode, the invention can realize the fast and high-precision detection of the inductor current, and has higher stability for the control of the high-side power tube, which is very suitable for the peak value of the high-frequency working condition. Current Mode Buck‑Boost Converters.

Figure 202011171347

Description

Current detection circuit of current mode buck-boost converter
Technical Field
The invention relates to the technical field of analog integrated circuits, in particular to a current detection circuit of a current mode buck-boost converter.
Background
The rapid development of modern electronic industry puts higher requirements on the performance of power management chips, and direct current-direct current converters such as Buck-Boost and the like are widely applied to electronic product design due to lower energy conversion loss. Currently, the Buck-Boost has feedback control modes such as ripple hysteresis, current mode and voltage mode. The current mode feedback control mode has the advantages of self-inductance current detection, quick transient response, capability of simplifying a loop compensation structure and the like, and becomes a preferred control mode in the application of Buck-Boost chips.
A typical peak current mode control Buck-Boost circuit architecture is shown in fig. 1. Error amplifier EA will output VOUTSampling the resulting feedback voltage VFBAnd a reference voltage VREFAmplifying the difference value to output a determined inductance current ILControl signal V of peak valueC. The current sampling circuit obtains the inductive current ILAfter the transient information is converted into and ILProportional voltage VSENSE. Slope compensation signal VslopeAnd VSENSEThe superposed signals are transmitted to a PWM positive terminal of a pulse width modulation comparator and can be used as a duty ratio>And the stability of the circuit is ensured when the voltage is 50 percent. The working frequency of the chip is determined by a clock signal CLK, in each period, when the rising edge of the CLK comes, the Q end of the output of the RS trigger is set to be 1, the PWM of the comparator outputs low level, and the power tube MHIs turned on and MLOff, inductor current ILStarting to rise; when the inductive current ILWhen rising to the set value, Vslope+VSENSE>VCWhen the comparator PWM outputs high level, the Q end signal of the RS trigger is cleared, and the power tube MHIs turned off and MLOn, inductor current ILAnd begins to fall. Finally, when the circuit is in steady state operation, the output VOUT-is:
Figure BDA0002747394700000011
the design difficulty of the peak current mode control mode in Buck-Boost specific application lies in realizing a high-performance current detection circuit, and the requirements are to shorten sampling delay as much as possible and improve the accuracy of current information obtained by sampling. Current detection schemes such as power tube on-resistance, SENSE resistance and DCR sampling in the prior art respectively have the problems of low precision, large power loss, requirement of extra external pins and the like, and limit the application occasions of chips. In addition, when the power output stage is switched between states in each clock cycle, the current sampling information precision and the loop control state are affected by the change of high voltage and large current, and the risks of causing loop misoperation and chip damage exist.
Disclosure of Invention
The invention aims to provide a current detection circuit of a current mode buck-boost converter, which aims to solve the problems in the background technology.
In order to solve the above technical problem, the present invention provides a current detection circuit for a current-mode buck-boost converter, which includes a diode D1 and a power tube MHPower tube MLAnd driveL module, drive H module, electric capacity COCapacitor C1, inductor L, error amplifier EA, and resistor RSETLoad RLResistance RslopeMOS transistor MN1MOS transistor MNH1The power tube grid source differential pressure detection module, the PWM comparator, the RS trigger 1, the RS trigger 2, the levelDown module and the levelUP module;
diode D1 positive terminal chip low voltage power supply VDD_LowThe negative end of the floating power supply rail is connected with the positive end Boost of the floating power supply rail; the upper end of the capacitor C1 is connected with the positive terminal Boost, and the lower end is connected with the SW node; power tube MHDrain terminal connected with VINThe grid end is connected with the output end of the driving H module, and the source end is connected with the positive end Boost; power tube MLThe drain terminal is connected with the SW node, the gate terminal is connected with the output end of the driving L module, and the source terminal is connected with the VOUT-; capacitor COUpper end connected with VOUTThe lower end is connected with GND; load RLUpper end connected with VOUTThe lower end is connected with GND; the upper end of the inductor L is connected with the SW node, and the lower end of the inductor L is connected with GND; reference current source IREFUpper end connected with VDD_LowThe lower end of the error amplifier is connected with the positive end of an error amplifier EA; resistance RSETThe upper end is connected with the positive end of the error amplifier EA, and the lower end is connected with the VOUT-; the negative end of the error amplifier EA is connected with a reference voltage source VREFThe output end is connected with the peak current limit setting voltage VC；
MOS transistor MN1Drain terminal connected with slope current source IslopeLower end, gate end is connected with VCAnd source terminal connection resistor RslopeAn upper end; resistance RslopeLower end is connected with VOUT-; ramp current source IslopeUpper end connected with VDD_Low(ii) a MOS transistor MNH1Drain terminal connected with VINThe grid end is connected with a first output end EN _ SENSE of a grid-source voltage difference detection module of the power tube, and the source end is connected with an MOS tube MN1A drain terminal;
first input end V of power tube grid-source differential pressure detection moduleG(MH)Connect MHThe gate end and the second output end EN _ COMP are connected with the enable end of the PWM comparator; the positive end of the PWM comparator is connected with MNH1The output end of the level Down module is connected with the input end of the level Down module; the output end of the levelDown module is connected with the R end of the RS trigger 2; the S end of the RS trigger 2 is connected with a clock signal CLK, and the Q end is connected with the input end of the driving L module; l output end of driving moduleConnect MLA gate terminal; the input end of the levelUP module is connected with a clock signal CLK, and the output end of the levelUP module is connected with the S end of the RS trigger 1; the R end of the RS trigger 1 is connected with the output end of the PWM comparator, and the Q end of the RS trigger is connected with the input end of the driving H module; the output end of the drive H module is connected with a power tube MHAnd a gate terminal.
Optionally, the power tube gate-source voltage difference detection module includes NMOS tubes MN 1-MN 5, PMOS tubes MP 1-MP 4, inverters INV 1-INV 3, resistors R1-R4, and a power tube MHCapacitors C1 and C2, NAND gate NAND1, NOR gate NOR1, schmitt trigger SMIT1 and schmitt trigger SMIT 2;
the drain end of the NMOS tube MN1 is connected with the lower end of a resistor R1, the gate end is connected with the upper end of a resistor R2, and the source end is connected with an SW node; the drain terminal of the NMOS tube MN2 is connected with VbiasThe grid end is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN1, and the source end is connected with the upper end of a resistor R2; the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN3 is connected with the drain end of a PMOS (P-channel metal oxide semiconductor) tube MP2, the gate end is connected with the output end of an inverter INV3, and the source end is connected with an SW node; the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN4 is connected with the lower end of a resistor R4, the gate end is connected with the output end of a Schmitt trigger SMIT1, and the source end is connected with an SW node; the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN5 is connected with the drain end of a PMOS (P-channel metal oxide semiconductor) tube MP4, the gate end is connected with the output end of a NOR gate NOR1, and the source end is connected with an SW node;
the drain terminal of the PMOS tube MP1 is connected with the gate terminal thereof, the gate terminal is connected with the gate terminal of the PMOS tube MP2, and the source terminal is connected with the VBOOST(ii) a The drain end of the PMOS tube MP2 is connected with the drain end of the NMOS tube MN3, the gate end of the PMOS tube MP1 is connected with the gate end of the PMOS tube MP 5, and the source end of the PMOS tube MP2 is connected with the drain end of the NMOS tube MN 5; the drain terminal of the PMOS transistor MP3 is connected with the upper end of a resistor R3, the gate terminal is connected with the gate terminal of an NMOS transistor MN4, and the source terminal is connected with a voltageBOOST(ii) a The drain terminal of the PMOS tube MP4 is connected with the drain terminal of the NMOS tube MN5, the gate terminal is connected with the output terminal of the NAND gate NAND1, and the source terminal is connected with VBOOST；
The upper end of the resistor R1 is connected with GCThe lower end of the signal is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN 1; the upper end of the resistor R2 is connected with the source end of an NMOS tube MN2, and the lower end is connected with a SW node; the upper end of the resistor R3 is connected with the drain end of the PMOS tube MP3, and the lower end is connected with the upper end of the resistor R4; the upper end of the resistor R4 is connected with the upper end of the capacitor C2, and the lower end is connected with the upper end of an NMOS tube MN 4;
the upper end of the capacitor C1 is connected with the upper end of the resistor R1, and the lower end of the capacitor C1 is connected with the lower end of the resistor R1; the upper end of the capacitor C2 is connected with the upper end of the resistor R4, and the lower end of the capacitor C2 is connected with the SW node;
the input end of the inverter INV1 is connected with the output end of the NOR gate NOR1, and the output end of the inverter INV1 is connected with the second input end of the NAND gate NAND 1; inverter INVThe 2 input end is connected with the output end of the NAND gate 1, and the output end of the inverter INV2 is connected with the first input end of the NOR gate NOR 1; the input end of the inverter INV3 is connected with GCThe output end of the signal is connected with the grid end of an NMOS tube MN 3;
the first input terminal G of the NAND gate 1CThe second input end of the signal is connected with the output end of the inverter INV1, and the output end of the signal is connected with the grid end of the PMOS tube MP 4; the first input end of the NOR gate NOR1 is connected with the output end of the inverter INV2, and the second input end is connected with the output end GCThe output end of the signal is connected with the input end of the inverter INV 1;
the input end of the Schmitt trigger SMIT1 is connected with the drain end of an NMOS tube MN3, and the output end is connected with the gate end of a PMOS tube MP 3; the output end of the Schmitt trigger SMIT2 is connected with the upper end of the capacitor C2, and the output end is connected with EN _ CMOP;
power tube MHDrain terminal connected with VINThe grid end is connected with the drain end of the NMOS pipe MN5, and the source end is connected with the SW node.
The current detection circuit of the current mode buck-boost converter provided by the invention has the following beneficial effects:
(1) in each period, when the peak value of the inductive current reaches the set upper limit, the PWM output of the PWM comparator arranged on the floating power rail can directly close the high-side power tube M without being delayed by a level shift moduleHThe response speed of the circuit is improved;
(2) on-resistance R using high side power tubedson(H)Current sampling is carried out, the sampling speed is improved, and a comparison reference point of the information obtained by sampling is set through a mirror image tube matched with the power tube, so that the condition that R is caused by parameter drift of the power tube is avoideddson(H)Changing to finally solve the problem that the sampling gain is not fixed;
(3) the grid source differential pressure detection module of the power tube can be based on MHThe grid-source differential pressure state dynamically sets current detection delay to ensure that the circuit has a shielding function on noise generated in the switching process of the power level interference source;
(4) compared with the conventional peak current mode-controlled Buck-Boost converter, the peak current mode-controlled Buck-Boost converter can realize the rapid and high-precision detection of the inductive current, has higher stability for controlling the high-side power tube, and is very suitable for the peak current mode Buck-Boost converter under the high-frequency working condition.
Drawings
FIG. 1 is a schematic diagram of a typical peak current mode control Buck-Boost circuit architecture;
fig. 2 is a schematic diagram of a current detection circuit of the current-mode buck-boost converter provided by the present invention;
FIG. 3 is a schematic diagram of the Miller plateau effect when the high side power transistor is switched from the OFF state to the ON state;
fig. 4 is a schematic circuit diagram of a power tube gate-source voltage difference detection module.
Detailed Description
The current detection circuit of the current-mode buck-boost converter according to the present invention is further described in detail with reference to the accompanying drawings and the specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a current detection circuit of a current-mode buck-boost converter, and the specific system architecture of the current detection circuit is shown in figure 2, and the current detection circuit comprises a diode D1 and a power tube MHPower tube MLDrive L module, drive H module and capacitor COCapacitor C1, inductor L, error amplifier EA, and resistor RSETLoad RLResistance RslopeMOS transistor MN1The power tube grid source differential pressure detection module, the PWM comparator, the RS trigger 1, the RS trigger 2, the levelDown module and the levelUP module;
diode D1 positive terminal chip low voltage power supply VDD_LowThe negative end of the floating power supply rail is connected with the positive end Boost of the floating power supply rail; the upper end of the capacitor C1 is connected with the positive terminal Boost, and the lower end is connected with the SW node; power tube MHDrain terminal connected with VINThe grid end is connected with the output end of the driving H module, and the source end is connected with the positive end Boost; power tube MLThe drain terminal is connected with the SW node, the gate terminal is connected with the output end of the driving L module, and the source terminal is connected with the VOUT-; capacitor COUpper end connected with VOUTThe lower end is connected with GND; load RLUpper end connected with VOUT-, lower end connectedGND; the upper end of the inductor L is connected with the SW node, and the lower end of the inductor L is connected with GND; reference current source IREFUpper end connected with VDD_LowThe lower end of the error amplifier is connected with the positive end of an error amplifier EA; resistance RSETThe upper end is connected with the positive end of the error amplifier EA, and the lower end is connected with the VOUT-; the negative end of the error amplifier EA is connected with a reference voltage source VREFThe output end is connected with the peak current limit setting voltage VC(ii) a MOS transistor MN1Drain terminal connected with slope current source IslopeThe lower end and the grid end are connected with a peak current limiting voltage VCAnd source terminal connection resistor RslopeAn upper end; resistance RslopeLower end is connected with VOUT-; ramp current source IslopeUpper end connected with VDD_Low(ii) a MOS transistor MNH1Drain terminal connection voltage VINThe grid end is connected with a first output end EN _ SENSE of a grid-source voltage difference detection module of the power tube, and the source end is connected with an MOS tube MN1A drain terminal; first input end V of power tube grid-source differential pressure detection moduleG(MH)Connect MHThe gate end and the second output end EN _ COMP are connected with the enable end of the PWM comparator; the positive end of the PWM comparator is connected with MNH1The output end of the level Down module is connected with the input end of the level Down module; the output end of the levelDown module is connected with the R end of the RS trigger 2; the S end of the RS trigger 2 is connected with a clock signal CLK, and the Q end is connected with the input end of the driving L module; the output end of the driving module L is connected with MLA gate terminal; the input end of the levelUP module is connected with a clock signal CLK, and the output end of the levelUP module is connected with the S end of the RS trigger 1; the R end of the RS trigger 1 is connected with the output end of the PWM comparator, and the Q end of the RS trigger is connected with the input end of the driving H module; the output end of the drive H module is connected with MHAnd a gate terminal.
The power tube gate-source differential pressure detection module in fig. 2 is used as a key module, can detect the state of the power tube gate-source differential pressure, dynamically sets the time delay of the detection circuit, and avoids the false operation of a loop circuit caused by voltage and current noise generated by the miller platform effect. The specific implementation of the power tube gate-source voltage difference detection module is shown in fig. 4, and comprises NMOS tubes MN 1-MN 5, PMOS tubes MP 1-MP 4, inverters INV 1-INV 3, resistors R1-R4, and a power tube MHCapacitors C1 and C2, NAND gate NAND1, NOR gate NOR1, schmitt trigger SMIT1 and schmitt trigger SMIT 2;
the drain end of the NMOS tube MN1 is connected with the lower end of a resistor R1, the gate end is connected with the upper end of a resistor R2, and the source end is connected with an SW node; NMOS tube MN2 drain terminal connected to bias voltage VbiasThe grid end is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN1, and the source end is connected with the upper end of a resistor R2; the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN3 is connected with the drain end of a PMOS (P-channel metal oxide semiconductor) tube MP2, the gate end is connected with the output end of an inverter INV3, and the source end is connected with an SW node; the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN4 is connected with the lower end of a resistor R4, the gate end is connected with the output end of a Schmitt trigger SMIT1, and the source end is connected with an SW node; the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN5 is connected with the drain end of a PMOS (P-channel metal oxide semiconductor) tube MP4, the gate end is connected with the output end of a NOR gate NOR1, and the source end is connected with an SW node;
the drain terminal of the PMOS tube MP1 is connected with the gate terminal thereof, the gate terminal is connected with the gate terminal of the PMOS tube MP2, and the source terminal is connected with the VBOOST(ii) a The drain end of the PMOS tube MP2 is connected with the drain end of the NMOS tube MN3, the gate end of the PMOS tube MP1 is connected with the gate end of the PMOS tube MP 5, and the source end of the PMOS tube MP2 is connected with the drain end of the NMOS tube MN 5; the drain terminal of the PMOS transistor MP3 is connected with the upper end of a resistor R3, the gate terminal is connected with the gate terminal of an NMOS transistor MN4, and the source terminal is connected with a voltageBOOST(ii) a The drain terminal of the PMOS tube MP4 is connected with the drain terminal of the NMOS tube MN5, the gate terminal is connected with the output terminal of the NAND gate NAND1, and the source terminal is connected with VBOOST；
The upper end of the resistor R1 is connected with GCThe lower end of the signal is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN 1; the upper end of the resistor R2 is connected with the source end of an NMOS tube MN2, and the lower end is connected with a SW node; the upper end of the resistor R3 is connected with the drain end of the PMOS tube MP3, and the lower end is connected with the upper end of the resistor R4; the upper end of the resistor R4 is connected with the upper end of the capacitor C2, and the lower end is connected with the upper end of an NMOS tube MN 4;
the upper end of the capacitor C1 is connected with the upper end of the resistor R1, and the lower end of the capacitor C1 is connected with the lower end of the resistor R1; the upper end of the capacitor C2 is connected with the upper end of the resistor R4, and the lower end of the capacitor C2 is connected with the SW node;
the input end of the inverter INV1 is connected with the output end of the NOR gate NOR1, and the output end of the inverter INV1 is connected with the second input end of the NAND gate NAND 1; the input end of the inverter INV2 is connected with the output end of the NAND gate 1, and the output end of the inverter INV2 is connected with the first input end of the NOR gate NOR 1; the input end of the inverter INV3 is connected with GCThe output end of the signal is connected with the grid end of an NMOS tube MN 3;
the first input terminal G of the NAND gate 1CThe second input end of the signal is connected with the output end of the inverter INV1, and the output end of the signal is connected with the grid end of the PMOS tube MP 4; the first input end of the NOR gate NOR1 is connected with the output end of the inverter INV2, and the second input end is connected with the output end GCThe output end of the signal is connected with the input end of the inverter INV 1;
the input end of the Schmitt trigger SMIT1 is connected with the drain end of an NMOS tube MN3, and the output end is connected with the gate end of a PMOS tube MP 3; the output end of the Schmitt trigger SMIT2 is connected with the upper end of the capacitor C2, and the output end is connected with EN _ CMOP;
power tube MHDrain terminal connection voltage VINThe grid end is connected with the drain end of the NMOS pipe MN5, and the source end is connected with the SW node.
The working principle of the invention is as follows:
regarding the PWM comparator: the error amplifier EA output of FIG. 2 produces a peak current limit voltage VCThrough MOS transistor MN1After being converted into current, the current is compensated with a slopeslopeIn MOS transistor MN1The drain end of the MOS transistor M is subjected to subtraction operation and finally is subjected to MOS transistor MNH1(gate terminal signal phase and MHSame) source terminal generates current detection comparison reference voltage information.
At the beginning of each cycle, the clock signal CLK generates a high level pulse, the Q terminal of the RS flip-flop 1 is set to 1, GCAfter the signal drives the H module to enhance the driving capability, the power tube M is startedHInductance current ILAnd starts to rise. At the end of each cycle, the inductor current ILHas risen to a voltage V limited by the peak currentCAt the determined peak value, the PWM comparator outputs high level, and the power tube M is quickly turned off by setting 0 to the Q end output of the trigger 1HInductance current ILAnd begins to fall.
Compared with the PWM comparator in the conventional peak current mode control Buck-Boost converter working at VOUT-and VDD_LowUnlike low voltage power supplies, in the present invention the PWM comparator operates on a high voltage floating supply rail between the SW node and the positive terminal Boost. When the inductive current ILWhen the output signal of the PWM comparator rises to a set peak value, the output signal of the PWM comparator is transmitted to a floating power rail without passing through a levelUp module (namely a level shift module) and then the power tube M is closedH. The method can avoid extra level shift delay, improve the response speed of the system and is more suitable for high-frequency application.
And (3) matching mirror tube sampling about a power tube: in the invention, the power tube M is adoptedHMatched MOS tube MNH1And finishing current sampling.
MHAs a high side power tube, using its on-resistance Rdson(H)Direct current to inductor current ILTo carry out miningSampling the obtained information VPWM-applied to the negative terminal of the PWM comparator. The sampling mode does not need to introduce additional high-voltage devices and feedback control loops, can reduce circuit damage and improve sampling speed, and is suitable for high-frequency application.
VPWM-＝VIN-Rdson(H)×IL(1)
Current detection comparison reference voltage VPWM+ applied to positive end of PWM comparator and composed of MOS transistor MNH1Peak current limit setting voltage VCAnd a ramp current IslopeAnd (4) jointly determining.
Figure BDA0002747394700000081
R in the formula (2)dson(NH1)Is a MOS transistor MNH1On-resistance, Vth(N1)Is a MOS transistor MN1A threshold voltage.
Figure BDA0002747394700000082
In the formula (2) ILpeakFor the inductor current I in each cycleLA peak value is set.
Figure BDA0002747394700000083
In the formula (4) (W/L)HAnd (W/L)NH1Are MOS transistors M respectivelyHAnd MOS transistor MNH1Width to length ratio.
As can be seen from the equation (4), by setting the sampled information comparison reference point by the mirror image tube matched with the power tube, I in each period is finally obtainedLpeakThe size of the MOS transistor is only equal to that of the MOS transistor MHAnd MOS transistor MNH1The ratio of the dimensions is relevant. Avoid the drift of power tube parameters caused by process variation to cause Rdson(H)Varying, the final sampling gain is not fixed, so that ILpeakDeviation from the set value.
Regarding power tube grid source voltage difference detection: high side power tubeMHThe Miller platform effect exists in the starting process, the generated noise can influence the sampling precision and the normal work of the circuit, the linear idealized approximation is carried out on the actions of each stage during the starting process, the detailed schematic analysis is shown in figure 3, and figure 3 shows that the high power measuring tube MHThe miller platform effect schematic diagram in the switching process from the closed state to the open state has larger voltage and current mutation, which affects the current detection precision and the system loop stability and easily causes the loop to generate false operation.
Period t 0: after the rising edge of CLK comes, G is delayed by t0 through a levelUP module and an RS trigger 1CSignal-high, high-side power tube MHPreparing to start;
period t 1: high side power tube MHThe gate-source voltage difference is charged to the threshold voltage, and the high-side power tube MHJust starting;
period t 2: inductive current ILIs larger than the high side power tube MHLeakage current, high side power transistor MHThe gate-source voltage difference continues to rise in the saturation state;
period t 3: high side power tube MHLeakage current greater than inductor current ILHigh side power tube MHIn the linear state, the parasitic capacitance of the SW node starts to be charged. Drive H module to high side power tube MHCharging the gate-drain parasitic capacitance, high side power transistor MHThe grid-source voltage difference is kept constant;
period t 4: SW node voltage has risen to VINDriving H module to drive high side power tube MHCharging to V by gate-source voltage differenceBoost-VSWThereafter the power stage produces less noise (dV/dt, dI/dt) with no large voltage and current variations.
For high side power tube MHIn the starting process, because the noise problem is generated by the Miller platform effect, the invention introduces a power tube grid source pressure difference detection module to shield the time period from t0 to t4 so as to wait for a high-side power tube MHAfter the circuit is completely opened, the detection and comparison are carried out when the grid-source voltage difference is large, the influence of noise on sampling precision and the false triggering of a loop circuit are prevented, and the specific circuit is realized as shown in an attached figure 4.
When signal GCAt high time, the high side power tube MHAnd starting to open. The bias current module which is formed by MN1, MN2, MP1 and R2 and is independent of the power supply voltage can generate the bias voltage VbiasIt can provide bias current for PWM comparator and prevent high side power tube MHThe PWM comparator starts to operate when the gate-source voltage difference does not rise high enough. Wherein R1 is a current limiting resistor, and C1 can be used for controlling signal GCWhen a rollover occurs, an acceleration bias point is established. The NMOS transistor MN1 has a large width-to-length ratio in design, and thus has a gate-source voltage difference and a threshold voltage (V)th(MN1)) Approach, generate a bias current IbiasComprises the following steps:
Figure BDA0002747394700000091
signal GCWhen high, MN3 is turned off. With the high side power tube MHOpening, the gate-source voltage difference gradually increases when it reaches Vbias+|Vth(MP2)When | the MP2 pipe is opened. Vth(MP2)Is the MP2 tube threshold voltage. After being shaped by a Schmitt trigger SMIT1, the current sampling enables EN _ SENSE to jump high, and controls the MOS transistor M in the figure 2NH1Conducting to provide a current detection comparison reference potential (V) for the positive terminal of the PWM comparator in FIG. 2PWM+)。
After this time is delayed by tDelayThereafter, the PWM comparator output enable EN _ COMP is toggled low and the PWM comparator starts to operate. When the inductive current ILWhen the PWM comparator is turned over again after rising to the set peak value, the signal GCIs rapidly pulled down, bias current IbiasAnd a high side power tube MHIs turned off, and MN3 is turned on in fig. 4, M in fig. 2 can be quickly changed by EN _ SENSE and EN _ COMPNH1And the PWM comparator is turned off.
tDelay＝ln0.5×R4×C2(6)
Reasonably setting input flip level and resistance R of Schmitt trigger SMIT24And a capacitor C2Parameter, namely, the delay t can be realizedDelayAny adjustment eventually ensures that the PWM comparator does not operate during the period t0 to t4 shown in fig. 3.
Reasonably setting bias voltage VbiasCan ensure the high-side power tube MHAnd before the grid-source voltage difference does not rise to the set value, the PWM comparator does not work.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (2)

1.一种电流模升降压变换器电流检测电路，其特征在于，包括二极管D1、功率管MH、功率管ML、驱动L模块、驱动H模块、电容CO、电容C1、电感L、误差放大器EA、电阻RSET、负载RL、电阻Rslope、MOS管MN1、MOS管MNH1、功率管栅源压差检测模块、PWM比较器、RS触发器1、RS触发器2、Level Down模块和Level UP模块；1. a current mode buck-boost converter current detection circuit is characterized in that, comprising diode D1, power tube MH, power tube ML , drive L module, drive H module, capacitor C O , capacitor C1, inductance L , error amplifier EA, resistor R SET , load R L , resistor R slope , MOS transistor M N1 , MOS transistor M NH1 , power transistor gate-source voltage difference detection module, PWM comparator, RS flip-flop 1, RS flip-flop 2, Level Down module and Level UP module; 二极管D1正端接芯片内低压电源VDD_Low，负端接浮动电源轨的正端Boost；电容C1上端接正端Boost，下端接SW节点；功率管MH漏端接VIN，栅端接驱动H模块输出端，源端接SW节点；功率管ML漏端接SW节点，栅端接驱动L模块输出端，源端接VOUT-；电容CO上端接VOUT-，下端接GND；负载RL上端接VOUT-，下端接GND；电感L上端接SW节点，下端接GND；参考电流源IREF上端接VDD_Low，下端接误差放大器EA正端；电阻RSET上端接误差放大器EA正端，下端接VOUT-；误差放大器EA负端接参考电压源VREF，输出端接峰值电流限设定电压VC；The positive terminal of the diode D1 is connected to the low-voltage power supply V DD_Low in the chip, and the negative terminal is connected to the positive terminal Boost of the floating power rail; the upper terminal of the capacitor C1 is connected to the positive terminal Boost, and the lower terminal is connected to the SW node; the drain terminal of the power tube MH is connected to V IN , and the gate terminal is connected to the driver The output end of the H module, the source end is connected to the SW node; the drain end of the power tube ML is connected to the SW node, the gate end is connected to the output end of the driver L module, the source end is connected to V OUT -; the upper end of the capacitor C O is connected to V OUT -, and the lower end is connected to GND; The upper end of the load RL is connected to V OUT - and the lower end is connected to GND; the upper end of the inductor L is connected to the SW node and the lower end is connected to GND; the upper end of the reference current source I REF is connected to V DD_Low , and the lower end is connected to the positive end of the error amplifier EA; the upper end of the resistor R SET is connected to the error amplifier EA Positive terminal, the lower terminal is connected to V OUT -; the negative terminal of the error amplifier EA is connected to the reference voltage source V REF , and the output terminal is connected to the peak current limit setting voltage V C ; MOS管MN1漏端接斜坡电流源Islope下端，栅端接VC，源端接电阻Rslope上端；电阻Rslope下端接VOUT-；斜坡电流源Islope上端接VDD_Low；MOS管MNH1漏端接VIN，栅端接功率管栅源压差检测模块的第一输出端EN_SENSE，源端接MOS管MN1漏端；The drain end of MOS transistor M N1 is connected to the lower end of the slope current source I slope , the gate end is connected to V C , and the source end is connected to the upper end of the resistor R slope ; the lower end of the resistor R slope is connected to V OUT -; the upper end of the slope current source I slope is connected to V DD_Low ; MOS transistor M The drain terminal of NH1 is connected to V IN , the gate terminal is connected to the first output terminal EN_SENSE of the gate-source voltage difference detection module of the power transistor, and the source terminal is connected to the drain terminal of the MOS transistor M N1 ; 功率管栅源压差检测模块的第一输入端VG(MH)接MH栅端，第二输出端EN_COMP接PWM比较器使能端；PWM比较器正端接MNH1源端，负端接SW节点，输出端接Level Down模块输入端；Level Down模块输出端接RS触发器2的R端；RS触发器2的S端接时钟信号CLK，
Figure DEST_PATH_FDA0002747394690000011
端接驱动L模块输入端；驱动模块L输出端接ML栅端；Level UP模块输入端接时钟信号CLK，输出端接RS触发器1的S端；RS触发器1的R端接PWM比较器输出端，Q端接驱动H模块输入端；驱动H模块输出端接功率管MH栅端。The first input terminal V G(MH) of the power tube gate-source voltage difference detection module is connected to the M H gate terminal, and the second output terminal EN_COMP is connected to the PWM comparator enable terminal; the positive terminal of the PWM comparator is connected to the M NH1 source terminal, and the negative terminal is connected to the M NH1 source terminal. It is connected to the SW node, and the output end is connected to the input end of the Level Down module; the output end of the Level Down module is connected to the R end of the RS flip-flop 2; the S end of the RS flip-flop 2 is connected to the clock signal CLK,
Figure DEST_PATH_FDA0002747394690000011
The terminal is connected to the input terminal of the driver L module; the output terminal of the driver module L is connected to the M L gate terminal; the input terminal of the Level UP module is connected to the clock signal CLK, and the output terminal is connected to the S terminal of the RS flip-flop 1; the R terminal of the RS flip-flop 1 is connected to the PWM comparison The Q terminal is connected to the input terminal of the driver H module; the output terminal of the driver H module is connected to the M H gate terminal of the power tube. 2.如权利要求1所述的电流模升降压变换器电流检测电路，其特征在于，所述功率管栅源压差检测模块包括NMOS管MN1~MN5、PMOS管MP1~MP4、反相器INV1~INV3、电阻R1~R4、功率管MH、电容C1和C2、与非门NAND1、或非门NOR1、施密特触发器SMIT1和施密特触发器SMIT2；2. The current-mode buck-boost converter current detection circuit according to claim 1, wherein the power transistor gate-source voltage difference detection module comprises NMOS transistors MN1-MN5, PMOS transistors MP1-MP4, an inverter INV1~INV3, resistors R1~R4, power tube MH, capacitors C1 and C2, NAND gate NAND1, NOR gate NOR1, Schmitt trigger SMIT1 and Schmitt trigger SMIT2; NMOS管MN1漏端接电阻R1下端，栅端接电阻R2上端，源端接SW节点；NMOS管MN2漏端接Vbias，栅端接NMOS管MN1漏端，源端接电阻R2上端；NMOS管MN3漏端接PMOS管MP2漏端，栅端接反向器INV3的输出端，源端接SW节点；NMOS管MN4漏端接电阻R4下端，栅端接施密特触发器SMIT1的输出端，源端接SW节点；NMOS管MN5漏端接PMOS管MP4漏端，栅端接或非门NOR1的输出端，源端接SW节点；The drain terminal of NMOS transistor MN1 is connected to the lower end of resistor R1, the gate terminal is connected to the upper end of resistor R2, and the source terminal is connected to SW node; the drain terminal of NMOS transistor MN2 is connected to V bias , the gate terminal is connected to the drain terminal of NMOS transistor MN1, and the source terminal is connected to the upper end of resistor R2; NMOS transistor The drain terminal of MN3 is connected to the drain terminal of the PMOS transistor MP2, the gate terminal is connected to the output terminal of the inverter INV3, and the source terminal is connected to the SW node; the drain terminal of the NMOS transistor MN4 is connected to the lower terminal of the resistor R4, and the gate terminal is connected to the output terminal of the Schmitt trigger SMIT1. The source terminal is connected to the SW node; the drain terminal of the NMOS transistor MN5 is connected to the drain terminal of the PMOS transistor MP4, the gate terminal is connected to the output terminal of the NOR gate NOR1, and the source terminal is connected to the SW node; PMOS管MP1漏端接其自身栅端，栅端接PMOS管MP2栅端，源端接VBOOST；PMOS管MP2漏端接NMOS管MN3漏端，栅端接PMOS管MP1栅端，源端接NMOS管MN5漏端；PMOS管MP3漏端接电阻R3上端，栅端接NMOS管MN4栅端，源端接VBOOST；PMOS管MP4漏端接NMOS管MN5漏端，栅端接与非门NAND1的输出端，源端接VBOOST；The drain terminal of the PMOS transistor MP1 is connected to its own gate terminal, the gate terminal is connected to the gate terminal of the PMOS transistor MP2, and the source terminal is connected to V BOOST ; the drain terminal of the PMOS transistor MP2 is connected to the drain terminal of the NMOS transistor MN3, the gate terminal is connected to the gate terminal of the PMOS transistor MP1, and the source terminal is connected to The drain terminal of NMOS transistor MN5; the drain terminal of the PMOS transistor MP3 is connected to the upper end of the resistor R3, the gate terminal is connected to the gate terminal of the NMOS transistor MN4, and the source terminal is connected to V BOOST ; the drain terminal of the PMOS transistor MP4 is connected to the drain terminal of the NMOS transistor MN5, and the gate terminal is connected to the NAND gate NAND1 The output terminal, the source terminal is connected to V BOOST ; 电阻R1上端接GC信号，下端接NMOS管MN1漏端；电阻R2上端接NMOS管MN2源端，下端接SW节点；电阻R3上端接PMOS管MP3漏端，下端接电阻R4上端；电阻R4上端接电容C2上端，下端接NMOS管MN4上端；The upper end of the resistor R1 is connected to the G C signal, and the lower end is connected to the drain end of the NMOS transistor MN1; the upper end of the resistor R2 is connected to the source end of the NMOS transistor MN2, and the lower end is connected to the SW node; the upper end of the resistor R3 is connected to the drain end of the PMOS transistor MP3, and the lower end is connected to the upper end of the resistor R4; the upper end of the resistor R4 Connect the upper end of the capacitor C2, and the lower end is connected to the upper end of the NMOS tube MN4; 电容C1上端接电阻R1上端，下端接电阻R1下端；电容C2上端接电阻R4上端，下端接SW节点；The upper end of the capacitor C1 is connected to the upper end of the resistor R1, and the lower end is connected to the lower end of the resistor R1; the upper end of the capacitor C2 is connected to the upper end of the resistor R4, and the lower end is connected to the SW node; 反向器INV1输入端接或非门NOR1输出端，反向器INV1输出端接与非门NAND1的第二输入端；反向器INV2输入端接与非门NAND1输出端，反向器INV2输出端接或非门NOR1的第一输入端；反向器INV3输入端接GC信号，输出端接NMOS管MN3栅端；The input terminal of the inverter INV1 is connected to the output terminal of the NOR gate NOR1, the output terminal of the inverter INV1 is connected to the second input terminal of the NAND gate NAND1; the input terminal of the inverter INV2 is connected to the output terminal of the NAND gate NAND1, and the output terminal of the inverter INV2 is output The first input end of the NOR gate NOR1 is terminated; the input end of the inverter INV3 is connected to the G C signal, and the output end is connected to the gate end of the NMOS transistor MN3; 与非门NAND1的第一输入端接GC信号，第二输入端接反向器INV1输出端，输出端接PMOS管MP4栅端；或非门NOR1的第一输入端接反向器INV2输出端，第二输入端接GC信号，输出端接反向器INV1输入端；The first input end of the NAND gate NAND1 is connected to the G C signal, the second input end is connected to the output end of the inverter INV1, and the output end is connected to the gate end of the PMOS transistor MP4; the first input end of the NOR gate NOR1 is connected to the output end of the inverter INV2 terminal, the second input terminal is connected to the G C signal, and the output terminal is connected to the input terminal of the inverter INV1; 施密特触发器SMIT1的输入端接NMOS管MN3漏端，输出端接PMOS管MP3栅端；施密特触发器SMIT2的输出端接电容C2上端，输出端接EN_CMOP；The input terminal of Schmitt trigger SMIT1 is connected to the drain terminal of NMOS transistor MN3, and the output terminal is connected to the gate terminal of PMOS transistor MP3; the output terminal of Schmitt trigger SMIT2 is connected to the upper terminal of capacitor C2, and the output terminal is connected to EN_CMOP; 功率管MH漏端接VIN，栅端接NMOS管MN5漏端，源端接SW节点。The drain terminal of the power transistor MH is connected to V IN , the gate terminal is connected to the drain terminal of the NMOS transistor MN5 , and the source terminal is connected to the SW node.
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