CN112017962B - Semiconductor structure and method for forming the same - Google Patents
Semiconductor structure and method for forming the same Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
- H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
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Abstract
一种半导体结构及其形成方法，形成方法包括：提供基底；在基底上形成栅极结构，栅极结构下方的基底用于作为沟道区；在栅极结构两侧的基底中形成沟槽；在沟槽底部靠近沟道区的位置处以及沟道区下方的基底中形成掺杂区，掺杂区中含有第二型离子，第二型离子与第一型晶体管的掺杂离子类型不同；形成掺杂区后，在沟槽中形成源漏掺杂层。本发明实施例掺杂区使得源漏掺杂层中的掺杂离子不易向沟道区下方扩散，从而源漏掺杂层中源极和漏极保持较远的间隔，且在半导体结构工作时，掺杂区使得源漏掺杂层的耗尽层不易扩展，从而使得源漏掺杂层中漏极引入的势垒不易降低以及亚阈值摆幅不易提高，进而降低短沟道效应，提高了半导体结构的电学性能。
A semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a gate structure on the substrate, the substrate below the gate structure being used as a channel region; forming grooves in the substrate on both sides of the gate structure; forming a doping region at a position near the channel region at the bottom of the groove and in the substrate below the channel region, the doping region containing second-type ions, the second-type ions being different from the doping ion type of the first-type transistor; after forming the doping region, forming a source-drain doping layer in the groove. The doping region of the embodiment of the present invention makes it difficult for the doping ions in the source-drain doping layer to diffuse below the channel region, so that the source and drain in the source-drain doping layer are kept at a relatively far interval, and when the semiconductor structure is working, the doping region makes it difficult for the depletion layer of the source-drain doping layer to expand, so that the potential barrier introduced by the drain in the source-drain doping layer is difficult to decrease and the subthreshold swing is difficult to increase, thereby reducing the short channel effect and improving the electrical performance of the semiconductor structure.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short channel effect (SCE-CHANNEL EFFECTS) is more likely to occur.
Accordingly, to better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, compared with a planar MOSFET, the gate structure has stronger control capability on a channel, can well inhibit short channel effect, and has better compatibility with the existing integrated circuit manufacturing compared with other devices.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and optimizes the electrical performance of the semiconductor structure.
In order to solve the problems, the embodiment of the invention provides a method for forming a semiconductor structure, which is used for forming a first type transistor, and comprises the steps of providing a substrate, forming a gate structure on the substrate, forming grooves in the substrate at two sides of the gate structure, forming a doped region at the position, close to the channel region, of the bottom of the groove and in the substrate below the channel region, wherein the doped region contains second type ions, the types of the second type ions are different from those of the first type transistor, and forming a source-drain doped layer in the groove after the doped region is formed.
Optionally, a second type ion is doped in the trench at a position close to the gate structure by adopting an ion implantation mode, so as to form a doped region.
Optionally, when the semiconductor structure is used for forming NMOS, the process parameters of the second type ion implantation comprise one or more of boron, gallium and indium, the implantation energy is 0.5Kev to 1.5Kev, the implantation dosage of the second type ion is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, the implantation direction is 5 degrees to 25 degrees relative to the normal line of the substrate, when the semiconductor structure is used for forming PMOS, the process parameters of the second type ion implantation comprise one or more of phosphorus, arsenic and antimony, the implantation energy is 1Kev to 3Kev, the implantation dosage of the second type ion is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, and the implantation direction is 5 degrees to 25 degrees relative to the normal line of the substrate.
Optionally, the step of forming the doped region further comprises doping C and F.
Optionally, doping C and F in the trench at a position close to the gate structure by adopting an ion implantation mode to form a doped region.
Optionally, the process parameters of doping C in the doped region comprise implantation energy of 1Kev to 3Kev, implantation dose of 1E14 atoms per square centimeter to 5E14 atoms per square centimeter, and an included angle between the implantation direction and the normal of the substrate is 5 degrees to 25 degrees, and the process parameters of doping F in the doped region comprise implantation energy of 2Kev to 4Kev, implantation dose of 3E14 atoms per square centimeter to 1E15 atoms per square centimeter, and an included angle between the implantation direction and the normal of the substrate is 5 degrees to 25 degrees.
Optionally, after the doped region is formed, annealing treatment is performed on the doped region before forming the source-drain doped layer.
Optionally, the annealing treatment comprises a first annealing process and a second annealing process, wherein the temperature of the second annealing process is higher than that of the first annealing process, the first annealing process is used for repairing lattice defects, and the second annealing process is used for activating ions.
Alternatively, the process parameters of the first annealing process include an annealing temperature of 400 ℃ to 600 ℃ and an annealing time of 10 minutes to 30 minutes.
Optionally, a spike anneal or a laser anneal is used to perform the second anneal process.
Optionally, the substrate comprises a substrate and a fin portion located on the substrate, the step of forming the groove comprises the steps of forming the groove in the fin portion on two sides of the gate structure, and the step of forming the doped region is formed in the fin portion at the position, close to the channel region, of the bottom of the groove and below the channel region.
Optionally, in the step of forming the doped region, a distance between the top surface of the doped region and the top surface of the fin is greater than one fourth of the height of the fin and less than or equal to one half of the height of the fin.
Optionally, when the semiconductor structure is used for forming NMOS, the material of the source-drain doped layer comprises one or more of Si, siP and SiC, and when the semiconductor structure is used for forming PMOS, the material of the source-drain doped layer comprises one or two of Si and SiGe.
Correspondingly, the embodiment of the invention also provides a semiconductor structure which is a first type transistor and comprises a substrate, a grid structure, a source-drain doped layer, a channel region, a doped region and a doped region, wherein the grid structure is positioned on the substrate, the source-drain doped layer is positioned in the substrate at two sides of the grid structure, the channel region is positioned in the substrate below the grid structure and between the source-drain doped layers, the doped region is positioned in the substrate below the channel region, the bottom of the source-drain doped layer is close to the substrate of the grid structure, and the doped region contains second type ions which are different from the doped ion types of the first type transistor.
Alternatively, when the first type transistor is NMOS, the second type ion comprises one or more of boron, gallium and indium, the second type ion concentration is 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter, when the first type transistor is PMOS, the second type ion comprises one or more of phosphorus, arsenic and antimony, and the second type ion concentration is 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter.
Optionally, the doped region is further doped with C and F.
Optionally, the doping concentration of C is 1E19 atoms per cubic centimeter to 5E19 atoms per cubic centimeter, and the doping concentration of F is 3E19 atoms per cubic centimeter to 1E20 atoms per cubic centimeter.
Optionally, the substrate comprises a substrate and a fin portion located on the substrate, the source-drain doped layer is located in the fin portion on two sides of the gate structure, the doped region is located in the fin portion below the gate structure, and the fin portion at the bottom of the source-drain doped layer and the fin portion close to the gate structure.
Optionally, the distance between the top surface of the doped region and the top surface of the fin portion is greater than one fourth of the height of the fin portion and less than or equal to one half of the height of the fin portion.
Optionally, when the semiconductor structure is NMOS, the material of the source-drain doped layer comprises one or more of Si, siP and SiC, and when the semiconductor structure is PMOS, the material of the source-drain doped layer comprises one or two of Si and SiGe.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention forms a grid structure on the substrate, wherein the substrate below the grid structure is used as a channel region, a groove is formed in the substrate at two sides of the grid structure, a doped region is formed at the position of the bottom of the groove close to the channel region and in the substrate below the channel region, the doped region contains second type ions, the types of the second type ions are different from those of the doped ions of the first type transistor, and after the doped region is formed, a source-drain doped layer is formed in the groove. Compared with the situation that a doped region is not formed, the doped region enables doped ions in the source-drain doped layer not to diffuse towards the lower portion of the channel region easily, so that a source electrode and a drain electrode in the source-drain doped layer keep a far distance, and when the semiconductor structure works, the doped region enables a depletion layer of the source-drain doped layer not to expand easily, so that potential barriers introduced by the drain electrode in the source-drain doped layer are not lowered easily, subthreshold swing (Subthreshold swing) is not raised easily, short channel effect is reduced, and electrical performance of the semiconductor structure is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
Fig. 2 to 6 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1, a schematic structural diagram of a semiconductor structure is shown.
Referring to fig. 1, the semiconductor structure comprises a substrate 1 and a fin 2 positioned on the substrate 1, a gate structure 3 crossing the fin 2, wherein the gate structure 3 covers partial top wall and partial side wall of the fin 2, and source-drain doped regions 4 are formed in the fin 2 at two sides of the gate structure 3.
Along with the development of the semiconductor manufacturing process, the width of the gate structure 3 is smaller and smaller in the extending direction perpendicular to the gate structure 3, so that the distance between the source and drain doped regions 4 at two sides of the gate structure 3 is smaller and smaller, and when the semiconductor structure works, the distance between the channel is smaller and smaller, the depletion layer of the source and drain doped regions 4 is easy to expand, so that the potential barrier introduced by the drain in the source and drain doped regions 4 is easy to reduce, the subthreshold swing is easy to improve, the short channel effect is serious, and the electrical performance of the semiconductor structure is poor.
In order to solve the technical problems, the embodiment of the invention provides a method for forming a semiconductor structure, which is used for forming a first type transistor, and comprises the steps of providing a substrate, forming a gate structure on the substrate, forming grooves in the substrate at two sides of the gate structure, forming a doped region at the position, close to the channel region, of the bottom of the groove and in the substrate below the channel region, wherein the doped region contains second type ions, the types of the second type ions are different from those of the first type transistor, and forming a source-drain doped layer in the groove after the doped region is formed.
The embodiment of the invention forms a grid structure on the substrate, wherein the substrate below the grid structure is used as a channel region, a groove is formed in the substrate at two sides of the grid structure, a doped region is formed at the position of the bottom of the groove close to the channel region and in the substrate below the channel region, the doped region contains second type ions, the types of the second type ions are different from those of the doped ions of the first type transistor, and after the doped region is formed, a source-drain doped layer is formed in the groove. Compared with the situation that the doped region is not formed, the doped region enables doped ions in the source-drain doped layer not to diffuse towards the lower portion of the channel region easily, so that a source electrode and a drain electrode in the source-drain doped layer keep a far distance, and when the semiconductor structure works, the doped region enables a depletion layer of the source-drain doped layer not to expand easily, so that potential barriers introduced by the drain electrode in the source-drain doped layer are not lowered easily and subthreshold swing is not improved easily, short channel effect is reduced, and electrical performance of the semiconductor structure is improved.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 2 to 6 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
A substrate (not shown) is provided.
The substrate provides a process platform for a subsequently formed semiconductor structure, the subsequently formed semiconductor structure is a first type transistor, the first type transistor comprises a source-drain doped layer, and first type ions are doped in the source-drain doped layer.
In this embodiment, taking a fin field effect transistor (FinFET) as an example of a semiconductor structure, the base includes a substrate 100 and a fin 101 on the substrate 100. In other embodiments, the semiconductor structure formed may also be a planar structure.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
The fin 101 is used to subsequently provide a channel region of the fin field effect transistor.
In this embodiment, the fin 101 and the substrate 100 are obtained by etching the same semiconductor layer. In other embodiments, the fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
Therefore, in this embodiment, the material of the fin 101 is the same as the material of the substrate 100, and the material of the fin 101 is silicon. In other embodiments, the material of the fin may be a semiconductor material suitable for forming the fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin may be different from the material of the substrate.
As shown in fig. 3, a gate structure 102 is formed on the substrate, the substrate under the gate structure 102 serving as a channel region 107.
The channel region 107 acts as a channel during operation of the semiconductor structure. The gate structure 102 is used to turn on or off the channel when the semiconductor structure is in operation.
Specifically, the gate structure 102 spans across the fin 101, and the gate structure 102 covers a portion of a top wall and a portion of a sidewall of the fin 101. The region of the fin 101 covered by the gate structure 102 in the fin 101 serves as a channel region 107.
In this embodiment, the gate structure 102 is a stacked structure. Specifically, the gate structure 102 includes a gate oxide 1021 and a gate layer 1022 on the gate oxide 1021. In other embodiments, the gate structure may also be a single layer structure, i.e., the gate structure includes only a gate layer.
In this embodiment, the gate oxide layer 1021 is made of silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the gate oxide 1021.
In this embodiment, the gate layer 1022 is polysilicon. In other embodiments, the material of the gate layer may also be amorphous carbon.
The step of forming the gate structure 102 includes forming a gate oxide material layer (not shown) conformally covering the fin 101, forming a gate material layer (not shown) on the gate oxide material layer, wherein a top surface of the gate material layer is higher than a top surface of the fin 101, forming a mask layer 103 on the gate material layer, and etching the gate oxide material layer and the gate material layer with the mask layer 103 as a mask, and the remaining gate oxide material layer and the remaining gate material layer as the gate structure 102.
The method for forming a semiconductor structure further includes forming a sidewall layer 108 on a sidewall of the gate structure 102 after forming the gate structure 102.
The sidewall layer 108 protects the gate structure 102 during a subsequent trench formation process in the substrate on both sides of the gate structure 102.
Referring to fig. 4, a trench 104 is formed in the substrate on both sides of the gate structure 102.
The trench 104 provides space for the subsequent formation of source-drain doped layers.
Specifically, the trench 104 is formed in the fin 101 at two sides of the gate structure 102.
In this embodiment, the trench 104 is formed by a dry etching process. The dry etching process is an anisotropic etching process, has good etching profile controllability, is beneficial to reducing damage to other film structures, and enables the quality of the formed groove 104 to be high, and the removal efficiency of the fin 101 material in the dry etching process enables the formation rate of the groove 104 to be high.
In other embodiments, the trench may also be formed using a wet etch process. The wet etching process is isotropic etching, has higher etching rate, and is simple to operate and low in process cost.
Referring to fig. 5, a doped region 105 is formed in the substrate at the bottom of the trench 104 near the channel region 107 and below the channel region 107, and the doped region 105 contains second type ions, which are different from the type of the doping ions of the first type transistor.
In this embodiment, the doped ion types of the second type ion and the first type transistor are different, which means that the doped ion types of the second type ion and the source-drain doped layer formed in the trench 104 are different, so that the doped ion in the source-drain doped layer is not easy to diffuse to the lower part of the channel region 107, so that the source electrode and the drain electrode in the source-drain doped layer keep a longer interval, and when the semiconductor structure works, the doped region 105 makes the depletion layer of the source-drain doped layer not easy to expand, so that the potential barrier introduced by the drain electrode in the source-drain doped layer is not easy to be reduced, the subthreshold swing is not easy to be improved, the short channel effect is reduced, and the electrical performance of the semiconductor structure is improved.
Specifically, the doped region 105 is formed in the fin 101 at a position near the channel region 107 at the bottom of the trench 104 and below the channel region 107.
In this embodiment, the second type ions are doped in the trench 104 at a position close to the gate structure 102 by using an ion implantation method, so as to form a doped region 105.
Specifically, after the second type ions are implanted, the second type ions are diffused in a direction perpendicular to the extending direction of the gate structure 102 to form the doped region 105.
It should be noted that, in the direction parallel to the surface normal of the substrate 100, the top surface of the doped region 105 is not too close to the top surface of the fin 101. If the distance is too short, the gate structure 102 is likely to cover the doped region 105 too much, and carriers in the channel are likely to scatter when the semiconductor structure is in operation, resulting in a low carrier migration rate. If the distance is too far, in the extending direction perpendicular to the gate structure 102, the doped ions in the subsequently formed source-drain doped layer are not easy to be blocked from diffusing to the lower part of the channel region 107 by the doped region 105, so that the source electrode and the drain electrode in the source-drain doped layer are not easy to keep a far distance, and when the semiconductor structure works, the effect of inhibiting the expansion of the depletion layer of the source-drain doped layer by the doped region 105 is not obvious, thereby leading to the obvious reduction of the potential barrier introduced by the drain electrode in the source-drain doped layer and the obvious improvement of the subthreshold swing, further leading to the serious short channel effect, and being unfavorable for improving the electrical performance of the semiconductor structure. In this embodiment, in the step of forming the doped region 105, a distance between the top surface of the doped region 105 and the top surface of the fin 101 is greater than one fourth of the height of the fin 101 and less than or equal to one half of the height of the fin 101.
In this embodiment, when the first-type transistor is an NMOS, the second-type ions include one or more of boron, gallium, and indium.
It should be noted that the implantation dose of the second type ion should not be too large or too small. If the implantation dose of the second type ion is too large, the concentration of the second type ion in the formed doped region 105 is easily excessive, the second type ion is easily diffused into the channel region 107, and when the semiconductor structure works, carriers in the channel are easily scattered, so that the migration rate of the carriers is not high. If the implantation dose of the second type ion is too small, the concentration of the second type ion in the doped region 105 is easily caused to be too small, resulting in poor formation quality of the doped region 105, the doped region 105 is not easy to block the doped ions in the subsequently formed source-drain doped layer from diffusing to the lower side of the channel region 107, so that the source electrode and the drain electrode in the source-drain doped layer are not easy to keep a longer interval, and in the working process of the semiconductor structure, the effect of the doped region 105 for inhibiting the expansion of the depletion layer of the source-drain doped layer is not obvious, so that the potential barrier introduced by the drain electrode in the source-drain doped layer is obviously reduced, the subthreshold swing is obviously improved, and further the short channel effect is serious, which is unfavorable for improving the electrical performance of the semiconductor structure. In this embodiment, the implantation dose of the second type ion is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter.
The implantation energy of the second type ion should not be too large or too small. If the implantation energy of the second type ions is too large, in the process of forming the doped region 105, the lattice damage of the fin 101 of the channel region 107 is larger, when the semiconductor structure works, the carrier migration rate in the channel is not high, and if the implantation energy is too large, the formed doped region 105 is easily far away from the channel region 107, and when the semiconductor structure works, the effect of the doped region 105 for inhibiting the expansion of the depletion layer of the source-drain doped layer 106 is not obvious, thereby the potential barrier introduced by the drain in the source-drain doped layer is obviously reduced, the subthreshold swing is obviously improved, and further the short channel effect is serious, which is unfavorable for improving the electrical performance of the semiconductor structure. If the implantation energy of the second type ion is too small, the second type ion is easily located on the surface of the trench 104, and thus the second type doping concentration in the doped region 105 below the channel region 107 is too low, and when the semiconductor structure works, the effect that the doped region 105 makes the depletion layer of the source-drain doped layer not easily spread is not obvious, so that the potential barrier introduced by the drain in the source-drain doped layer is obviously reduced, the subthreshold swing is obviously improved, and further the short channel effect is serious, which is unfavorable for improving the electrical performance of the semiconductor structure. In this embodiment, the implantation energy is 0.5Kev to 1.5Kev.
It should be noted that, the included angle between the implantation direction of the second type ion and the normal line of the base is not too large, specifically, the included angle between the implantation direction of the second type ion and the normal line of the substrate 100 is not too large. If the included angle is too large, too many second type ions are likely to enter the channel region 107, and when the semiconductor structure works, a problem of carrier scattering is likely to occur in the channel, so that the migration rate of carriers is not high. If the included angle is too small, it is easy to cause that the second type ions are not easy to diffuse below the channel region 107, the doped ions in the subsequently formed source-drain doped layer are easy to diffuse below the channel region 107, the doped region 105 is not easy to cause that the source electrode and the drain electrode in the source-drain doped layer keep a far distance, and when the semiconductor structure works, the effect of the doped region 105 for inhibiting the expansion of the depletion layer of the source-drain doped layer 106 is not obvious, thereby causing that the potential barrier introduced by the drain electrode in the source-drain doped layer is obviously reduced and the subthreshold swing is obviously improved, further causing that the short channel effect is serious and being unfavorable for improving the electrical property of the semiconductor structure. In this embodiment, the included angle between the implantation direction of the second type ion and the normal line of the substrate 100 is 5 degrees to 25 degrees.
In other embodiments, when the semiconductor structure is used for forming a PMOS, the process parameters of the second type ion implantation include that the second type ion comprises one or more of phosphorus, arsenic and antimony, the implantation energy is 1Kev to 3Kev, the implantation dosage of the second type ion is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, and the included angle between the implantation direction and the normal line of the substrate is 5 degrees to 25 degrees.
The method of forming the semiconductor structure further includes forming the doped region 105 further includes doping C and F after doping the second type ions.
Lattice defects can be generated in the process of forming the doped region 105, the C ions can be formed at lattice defects, so that the doped ions in the source-drain doped layer are not easy to diffuse in the extending direction perpendicular to the gate structure 102, and when the semiconductor structure works, the doped region 105 enables the depletion layer of the source-drain doped layer not to be easy to expand, so that the potential barrier introduced by the drain in the source-drain doped layer is not easy to be reduced and the subthreshold swing is not easy to be improved, further the short channel effect is reduced, and the electrical performance of the semiconductor structure is improved.
In this embodiment, the trench 104 is doped with C ions at a position close to the gate structure 102 by ion implantation.
It should be noted that, the angle between the C ion implantation direction and the normal line of the base should not be too large or too small, specifically, the angle between the C ion implantation direction and the normal line of the substrate 100. If the included angle is too large, excessive C ions are likely to enter the channel region 107, and the migration rate of carriers is not high when the semiconductor structure is in operation. If the included angle is too small, too much C ions are easily injected into the bottom of the trench 104, too little C ions are located on the sidewall of the trench 104, so that too little C ions are diffused into the bottom of the channel region 107, the formation quality of the doped region 105 is poor, the doped region 105 is not easy to block the doped ions in the subsequently formed source-drain doped layer from diffusing to the lower part of the channel region 107, so that the distance between the source and the drain in the source-drain doped layer is relatively close, and the effect of the doped region 105 for inhibiting the expansion of the depletion layer of the source-drain doped layer 106 is not obvious when the semiconductor structure works, thereby obviously reducing the potential barrier introduced by the drain in the source-drain doped layer and obviously improving the subthreshold swing, further causing serious short channel effect and being unfavorable for improving the electrical performance of the semiconductor structure. In this embodiment, the included angle between the implantation direction of the C ion and the normal line of the substrate is 5 degrees to 25 degrees.
The implantation energy of the C ion should not be too large or too small. If the implantation energy of the C ions is too large, in the process of forming the doped region 105, the lattice damage of the fin 101 of the channel region 107 is large, the subsequent annealing process is difficult to repair, when the semiconductor structure works, the carrier migration rate in the channel is not high, and if the implantation energy is too large, the C ions are easy to enter the channel region 107 through the gate structure 102, when the semiconductor structure works, the carrier migration rate is easy to be not high, so that the electrical performance of the semiconductor structure is not good. If the implantation energy of the C ions is too small, the C ions are easily translocated on the surface of the trench 104, so that the doping concentration of the C ions below the channel region 107 is too low, and when the semiconductor structure works, the doped region 105 is not easy to block the doped ions in the source-drain doped layer from diffusing to the lower side of the channel region 107, so that the distance between the source and the drain in the source-drain doped layer is relatively short, and when the semiconductor structure works, the depletion layer of the source-drain doped layer is easy to expand, so that the potential barrier introduced by the drain in the source-drain doped layer is significantly reduced, the subthreshold swing is significantly improved, and further the short channel effect is relatively serious, which is unfavorable for improving the electrical performance of the semiconductor structure. In this embodiment, the implantation energy of the C ion is 1Kev to 3Kev.
It should be noted that the implantation dose of C ions should not be too large or too small. If the implantation dose of the C ion is too large, the doping concentration of the C ion is too large, which may cause diffusion of the C ion into the channel region 107, and when the semiconductor is in operation, the migration rate of carriers is not high, and the leakage current of the junction (junction) formed by the subsequently formed source-drain doped layer and the doped region 105 is also easily increased. If the implantation dose of the C ion is too small, the doping concentration of the C ion in the doped region 105 is easy to be too small, the doped ion in the subsequently formed source-drain doped layer is not easy to be blocked by the doped region 105 to diffuse to the lower part of the channel region 107, so that the distance between the source and the drain in the source-drain doped layer is relatively short, and therefore, when the semiconductor structure works, the effect of inhibiting the expansion of the depletion layer of the source-drain doped layer 106 by the doped region 105 is not obvious, thereby, the potential barrier introduced by the drain in the source-drain doped layer is obviously reduced, the subthreshold swing is obviously improved, and further, the short channel effect is relatively serious, which is unfavorable for improving the electrical performance of the semiconductor structure. In this embodiment, the implantation dose of C ions is 1E14 atoms per square centimeter to 5E14 atoms per square centimeter.
The F ions also occupy lattice defects generated in the process of forming the doped region 105, block the doped ions in the source-drain doped layer, and diffuse in the direction perpendicular to the extending direction of the gate structure 102, so that when the semiconductor structure works, the doped region 105 makes the depletion layer of the source-drain doped layer not easy to expand, so that the potential barrier introduced by the drain in the source-drain doped layer is not easy to be reduced and the subthreshold swing is not easy to be improved, thereby reducing the short channel effect and improving the electrical performance of the semiconductor structure.
It should be noted that, the angle between the F ion implantation direction and the normal of the substrate should not be too large or too small. In this embodiment, the angle between the F ion implantation direction and the normal of the substrate is 5 degrees to 25 degrees. Specifically, reference is made to the description of the implantation direction of the C ion, and the description thereof will not be repeated here.
The implantation energy of the F ion should not be too large or too small. In this embodiment, the implantation energy of the F ion is 2Kev to 4Kev. Specifically, reference is made to the description of the implantation energy of the C ion, and the description thereof will not be repeated here.
It should be noted that the implantation dose of the F ion should not be too large or too small. In this embodiment, the implantation dose of ions is 3E14 atoms per square centimeter to 1E15 atoms per square centimeter. Specifically, reference is made to the description of the implantation dose of the C ion, and the description is not repeated here.
In addition, in the semiconductor process, hydrogen ions are the most common impurities, and F ions are doped to replace the hydrogen ions so as to form stable silicon-fluorine bonds, so that interface trap charges are not easy to form, the stability of an interface structure is enhanced, the negative bias temperature instability effect of a semiconductor device is improved to the greatest extent, and the service life of the semiconductor device is prolonged.
In other embodiments, the method for forming the semiconductor structure may further include doping C and F first and doping a second type ion later.
The method for forming the semiconductor structure further comprises annealing the doped region 105 before forming the source-drain doped layer after forming the doped region 105.
The annealing treatment comprises a first annealing process and a second annealing process, wherein the temperature of the second annealing process is higher than that of the first annealing process, the first annealing process is used for repairing lattice defects, and the second annealing process is used for activating ions.
The process of ion implantation may damage the crystal lattice of the fin 101 under the channel region 107, and the first annealing process is used to repair the lattice defect, so that C, F and the second type ions in the doped region 105 are not easy to generate transient enhanced Diffusion (TRANSIENT ENHANCED Diffusion, TED) in the formed lattice defect, so that the doped ions are not easy to diffuse into the channel region 107, and thus the migration rate of carriers is not easy to be affected.
It should be noted that the annealing temperature of the first annealing process should not be too high or too low. If the annealing temperature is too high, lattice defects generated in the ion implantation process cannot be well repaired, and doped ions are easily diffused into the channel region 107 through the lattice defects, so that carriers in the channel are easily scattered when the semiconductor structure works. If the annealing temperature is too low, the rate of repairing the lattice defects is too slow, the process time is too long, and the process defects are difficult to control. In this embodiment, the annealing temperature of the first annealing process is 400 ℃ to 600 ℃.
The annealing time should not be too long or too short. If the annealing time is too long, the thermal budget and the process cost are easily increased, and the dopant ions are easily diffused into the channel region 107, so that the migration rate of carriers is reduced and the leakage current of the junction (junction) formed by the source-drain doped layer and the doped region 105 formed later is increased when the semiconductor structure is operated. If the annealing time is too short, lattice defects generated during ion implantation are not completely repaired, which is easy to cause doped ions in the doped region 105 to diffuse into the channel region 107, and when the semiconductor structure works, the carrier migration rate in the channel is not high. In this embodiment, the annealing time is 10 minutes to 30 minutes.
In this embodiment, spike annealing or laser annealing is used to perform the second annealing process. The peak annealing process and the laser annealing process are annealing processes commonly used in the semiconductor field, and are beneficial to improving process compatibility.
The temperature of the second annealing process is higher, so that the doped ions in the doped region 105 can be activated, and because the time of the second annealing process is short, the doped ions in the doped region 105 are not easy to diffuse into the fin portion 101 below the gate structure 102, so that the electric field strength below the gate structure 102 is not easy to be too strong when the subsequent semiconductor structure works, and the gate structure 102 is not easy to be damaged.
It should be noted that the second annealing process can also play a role in repairing lattice defects.
Referring to fig. 6, after the doped region 105 is formed, a source-drain doped layer 106 is formed in the trench 104 (as shown in fig. 4).
During operation of the semiconductor structure, the source-drain doped layer 106 provides stress to the channel, so that the migration rate of carriers is higher.
In this embodiment, when the semiconductor structure is used to form an NMOS (NEGATIVE CHANNEL METAL Oxide Semiconductor), the material of the source-drain doped layer 106 includes one or more of Si, siP, and SiC. Specifically, the source-drain doped layer 106 is doped with N-type ions, the N-type ions replace the positions of silicon atoms in the crystal lattice, and the more N-type ions are doped, the higher the concentration of the multimers and the stronger the conductivity. The N-type ions are phosphorus, arsenic or antimony.
In other embodiments, when the semiconductor structure is used to form PMOS (Positive CHANNEL METAL Oxide Semiconductor), the material of the source-drain doped layer includes one or both of Si and SiGe. Specifically, the source-drain doped layer is doped with P-type ions, the P-type ions replace the positions of silicon atoms in the crystal lattice, the more the doped P-type ions are, the higher the concentration of the polyprots is, and the higher the conductivity is. The P-type ions are boron, gallium or indium.
The step of forming the source-drain doped layer 106 includes epitaxially growing an epitaxial layer in the trench 104, performing in-situ doping during the epitaxial layer growth, and forming the source-drain doped layer 106 in the trench 104. In other embodiments, an epitaxial layer is formed in the trench by an epitaxial growth process, and the epitaxial layer is ion doped to form the source/drain doped layer 106.
In this embodiment, a selective epitaxial growth is used to form an epitaxial layer in the trench 104. The thin film obtained by the selective epitaxial growth method has high purity and few defects, and is favorable for improving the formation quality of an epitaxial layer, thereby being favorable for optimizing the electrical property of a semiconductor structure. In other embodiments, the epitaxial layer may also be formed using a chemical vapor deposition (Chemical Vapor Deposition, CVD) or the like process.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 6, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure is a first-type transistor and comprises a substrate, a gate structure 102, a source-drain doped layer 106, a channel region 107, a doped region 105 and a doped region 105, wherein the gate structure 102 is arranged on the substrate, the source-drain doped layer 106 is arranged in the substrate at two sides of the gate structure 102, the channel region 107 is arranged in the substrate below the gate structure 102, the channel region 107 is arranged between the source-drain doped layers 106, the doped region 105 is arranged in the substrate below the channel region 107, the bottom of the source-drain doped layer 106 is close to the substrate of the gate structure 102, and the doped region 105 contains second-type ions which are different from the doped ions of the first-type transistor.
The doped region 105 in the embodiment of the present invention contains a second type of ion, where the second type of ion is different from the type of doped ion of the first type transistor, which means that the second type of ion is different from the type of doped ion in the source/drain doped layer 106. The doped region 105 makes the doped ions in the source-drain doped layer 106 not easy to diffuse to the lower side of the channel region 107, so that the source electrode and the drain electrode in the source-drain doped layer 106 keep a far distance, and when the semiconductor structure works, the doped region 105 makes the depletion layer of the source-drain doped layer 106 not easy to expand, so that the potential barrier introduced by the drain electrode in the source-drain doped layer 106 is not easy to be reduced and the subthreshold swing is not easy to be improved, thereby reducing the short channel effect and improving the electrical performance of the semiconductor structure.
The substrate provides a process platform for forming a semiconductor structure, the semiconductor structure is a first type transistor, the first type transistor comprises a source-drain doped layer 106, and first type ions are doped in the source-drain doped layer 106.
In this embodiment, the semiconductor structure is taken as an example of a fin field effect transistor, and the base includes a substrate 100 and a fin portion 101 located on the substrate 100. In other embodiments, the semiconductor structure formed may also be a planar structure.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the fin 101 and the substrate 100 are obtained by etching the same semiconductor layer. In other embodiments, the fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
Therefore, in this embodiment, the material of the fin 101 is the same as the material of the substrate 100, and the material of the fin 101 is silicon. In other embodiments, the material of the fin may be a semiconductor material suitable for forming the fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin may be different from the material of the substrate.
The gate structure 102 is used to turn on or off the channel when the semiconductor structure is in operation.
Specifically, the gate structure 102 spans across the fin 101, and the gate structure 102 covers a portion of a top wall and a portion of a sidewall of the fin 101.
In this embodiment, the gate structure 102 is a stacked structure. Specifically, the gate structure 102 includes a gate oxide 1021 and a gate layer 1022 on the gate oxide 1021. In other embodiments, the gate structure may also be a single layer structure, i.e., the gate structure includes only a gate layer.
In this embodiment, the gate oxide layer 1021 is made of silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the gate oxide 1021.
In this embodiment, the gate layer 1022 is polysilicon. In other embodiments, the material of the gate layer may also be amorphous carbon.
The semiconductor structure further includes a sidewall layer 108 on sidewalls of the gate structure 102.
A source/drain doped layer 106 is formed in the recess 104 (as shown in fig. 5), and the sidewall layer 108 protects the gate structure 102 during the formation of the recess 104.
A channel region 107 is located in the fin 101 under the gate structure 102, and the channel region 107 is located between the source-drain doped layers 106. The channel region 107 acts as a channel during operation of the semiconductor structure.
During operation of the semiconductor structure, the source-drain doped layer 106 provides stress to the channel, so that the migration rate of carriers is higher.
Specifically, the source-drain doped layer 106 is located in the fin 101 at two sides of the gate structure 102.
In this embodiment, when the semiconductor structure is an NMOS, the material of the source-drain doped layer 106 includes one or more of Si, siP, and SiC. Specifically, the source-drain doped layer 106 is further doped with N-type ions, the N-type ions replace the positions of silicon atoms in the crystal lattice, and the more N-type ions are doped, the higher the concentration of the multimer is, and the stronger the conductivity is. The N-type ions are phosphorus, arsenic or antimony.
In other embodiments, when the semiconductor structure is a PMOS, the material of the source-drain doped layer includes one or both of Si and SiGe. Specifically, the source-drain doped layer is doped with P-type ions, the P-type ions replace the positions of silicon atoms in the crystal lattice, the more the doped P-type ions are, the higher the concentration of the polyprots is, and the higher the conductivity is. The P-type ions are boron, gallium or indium.
In this embodiment, when the first-type transistor is an NMOS, the second-type ions include one or more of boron, gallium, and indium.
The concentration of the second type ion is not too high or too low. If the concentration of the second type ions is too high, the second type ions are easy to diffuse into the channel region 107, and when the semiconductor structure works, carriers in the channel are easy to scatter, so that the migration rate of the carriers is not high. If the concentration of the second type ions is too low, resulting in poor formation quality of the doped region 105, the doped region 105 is not easy to block the doped ions in the source-drain doped layer 106 from diffusing to the lower side of the channel region 107, so that the source and the drain in the source-drain doped layer 106 are not easy to keep a far distance, and when the semiconductor structure works, the effect of the doped region 105 for inhibiting the expansion of the depletion layer of the source-drain doped layer 106 is not obvious, so that the potential barrier introduced by the drain in the source-drain doped layer 106 is obviously reduced and the subthreshold swing is obviously improved, further the short channel effect is serious, and the electric performance of the semiconductor structure is unfavorable to be improved. In this example, the concentration of the second type ion is 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter.
In other embodiments, when the first type transistor is a PMOS, the second type ion comprises one or more of phosphorus, arsenic, and antimony, and the second type ion concentration is 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter.
In this embodiment, the doped region is further doped with C and F.
Lattice defects can be generated in the process of forming the doped region 105, the C ions are located at lattice defects, so that the doped ions in the source-drain doped layer 106 are not easy to diffuse in the extending direction perpendicular to the gate structure 102, and when the semiconductor structure works, the doped region 105 enables the depletion layer of the source-drain doped layer 106 not to be easy to expand, so that potential barriers introduced by a drain in the source-drain doped layer 106 are not easy to be reduced and subthreshold swing is not easy to be improved, short channel effect is further reduced, and electrical performance of the semiconductor structure is improved.
The doping concentration of the C ion should not be too large or too small. If the doping concentration of the C ions is too large, the C ions are likely to diffuse into the channel region 107, resulting in a low carrier migration rate during the semiconductor operation, and also resulting in an increased leakage current at the junction formed by the source-drain doped layer 106 and the doped region 105. If the doping concentration of the C ions is too small, the doped region 105 is not easy to block the doped ions in the source-drain doped layer 106 from diffusing below the channel region 107, resulting in a closer distance between the source and the drain in the source-drain doped layer 106, so that when the semiconductor structure works, the effect of the doped region 105 for inhibiting the expansion of the depletion layer of the source-drain doped layer 106 is not obvious, thereby resulting in a significant reduction of the potential barrier introduced by the drain in the source-drain doped layer 106 and a significant increase of the subthreshold swing, and further resulting in a serious short channel effect, which is unfavorable for improving the electrical performance of the semiconductor structure. In this example, the doping concentration of the C ion is 1E19 atoms per cubic centimeter to 5E19 atoms per cubic centimeter.
It should be noted that the doping concentration of F should not be too large or too small. In this example, the doping concentration of F is 3E19 atoms per cubic centimeter to 1E20 atoms per cubic centimeter. Specifically, the description of the doping concentration of the doped C ion is not repeated here.
In addition, in the semiconductor process, hydrogen ions are the most common impurities, and F ions are doped to replace the hydrogen ions so as to form stable silicon-fluorine bonds, so that interface trap charges are not easy to form, the stability of an interface structure is enhanced, the negative bias temperature instability effect of a semiconductor device is improved to the greatest extent, and the service life of the semiconductor device is prolonged.
The doped region 105 is located in the fin 101 below the channel region 107, and the bottom of the source drain doped layer 106 is located in the fin 101 close to the gate structure 102.
It should be noted that, in the direction parallel to the surface normal of the substrate 100, the top surface of the doped region 105 is not too close to the top surface of the fin 101. If the distance is too short, the gate structure 102 is likely to cover the doped region 105 too much, and carriers in the channel are likely to scatter when the semiconductor structure is in operation, resulting in a low carrier migration rate. If the distance is too far, in the extending direction perpendicular to the gate structure 102, the doped ions in the source-drain doped layer 106 are not easy to be blocked from diffusing to the lower side of the channel region 107 by the doped region 105, so that the source electrode and the drain electrode in the source-drain doped layer 106 are not easy to keep a far distance, and when the semiconductor structure works, the effect of inhibiting the expansion of the depletion layer of the source-drain doped layer 106 by the doped region 105 is not obvious, thereby leading to the obvious reduction of the potential barrier introduced by the drain electrode in the source-drain doped layer 106 and the obvious improvement of the subthreshold swing, further leading to the serious short channel effect, and being unfavorable for improving the electrical performance of the semiconductor structure. In this embodiment, the distance between the top surface of the doped region 105 and the top surface of the fin 101 is greater than one fourth of the height of the fin 101 and less than or equal to one half of the height of the fin 101.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and the scope of the embodiments of the invention should be pointed out in the appended claims.
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