CN111613704B - A kind of patterned sapphire substrate for high-brightness deep ultraviolet LED and preparation method thereof - Google Patents
A kind of patterned sapphire substrate for high-brightness deep ultraviolet LED and preparation method thereof Download PDFInfo
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- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
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- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
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- H—ELECTRICITY
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- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/815—Bodies having stress relaxation structures, e.g. buffer layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
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Abstract
本发明公开了一种高亮度深紫外LED用图形化蓝宝石衬底及其制备方法。该蓝宝石衬底，包括蓝宝石晶片，所述蓝宝石晶片包括晶片C面，在晶片C面上分布有刻蚀孔，所述刻蚀孔包括底部沉孔和扩孔，所述晶片C面及扩孔的表面沉积有一层AlN/AlGaN薄膜，所述底部沉孔内设置有纳米级图形或DBR反射层。该高亮度深紫外LED用图形化蓝宝石衬底的制备方法依次为涂胶、纳米压印，刻蚀，沉积AlN/AlGaN薄膜，涂胶，曝光、显影，刻蚀，涂胶，曝光、显影，沉积纳米晶粒或沉积DBR反射层等工序。通过本发明获得的图形化蓝宝石衬底结构，能够显著提高蓝宝石晶片的深紫外光折射率，进而大幅度提高LED器件的光提取率，最终提高UVC LED的亮度,该图形化衬底技术可广泛应用于UVC LED制造领域。
The invention discloses a patterned sapphire substrate for high-brightness deep ultraviolet LED and a preparation method thereof. The sapphire substrate includes a sapphire wafer. The sapphire wafer includes a C-surface of the wafer. Etching holes are distributed on the C-surface of the wafer. The etching holes include a bottom counterbore and a reaming hole. A layer of AlN/AlGaN thin film is deposited on the surface of the bottom sink hole, and a nanoscale pattern or a DBR reflective layer is arranged in the bottom sink hole. The preparation method of the patterned sapphire substrate for the high-brightness deep ultraviolet LED comprises the steps of gluing, nano-imprinting, etching, depositing an AlN/AlGaN thin film, gluing, exposing, developing, etching, gluing, exposing, developing, Processes such as depositing nanocrystalline grains or depositing DBR reflective layers. The patterned sapphire substrate structure obtained by the invention can significantly improve the deep ultraviolet light refractive index of the sapphire wafer, thereby greatly improving the light extraction rate of the LED device, and finally improving the brightness of the UVC LED. The patterned substrate technology can be widely used. Applied in the field of UVC LED manufacturing.
Description
Technical Field
The invention relates to the field of LED substrate manufacturing, in particular to a graphical sapphire substrate for a high-brightness deep Ultraviolet (UVC) LED and a preparation method thereof.
Background
Ultraviolet LEDs generally refer to LEDs having a central wavelength of light emission of 400nm or less, and are referred to as near ultraviolet LEDs when the light emission wavelength is more than 380nm, and deep Ultraviolet (UVC) LEDs when the light emission wavelength is shorter than 300 nm. Deep ultraviolet light emitting diodes (UVC LEDs) have a very wide range of applications, such as water purification, air purification, disinfection, medical treatment, etc., and have the advantages of low cost, small size, long service life, low power consumption, etc., compared to conventional UVC light sources. The market scale of the UVC LED is huge, but the UVC LED has low luminous efficiency and small market occupation due to a plurality of technical difficulties in the prior art. Among them, the processing technology and method of sapphire substrate are important factors affecting the luminous efficiency of UVC LEDs. The existing UVC LED adopts a sapphire wafer as a base material, and patterns are not processed on the sapphire wafer, so that the discovery that the sapphire wafer has low light extraction efficiency, and a nitride film directly epitaxially grown on the sapphire wafer has high dislocation density and lattice mismatch degree, thereby seriously influencing the luminous efficiency and the service life of the UVC LED.
Disclosure of Invention
The invention aims to provide a graphical sapphire substrate for a high-brightness deep ultraviolet LED and a preparation method thereof, and solves the problem that the light extraction efficiency of the existing sapphire wafer for the deep ultraviolet LED is low.
The technical scheme adopted by the invention for solving the technical problems is as follows: a graphical sapphire substrate for a high-brightness deep ultraviolet LED comprises a sapphire wafer, wherein the sapphire wafer comprises a wafer C surface used for forming graphics, etching holes are uniformly distributed in the wafer C surface and comprise bottom counter bores and counterbores which are located above the bottom counter bores and have the hole diameters larger than the bottom counter bores, AlN/AlGaN films are deposited on the wafer C surface and the counterbores, and nanoscale graphics or DBR reflecting layers are arranged in the bottom counter bores.
Preferably, the AlN/AlGaN thin film has a thickness of 20 to 3000nm, and the DBR reflective layer has a thickness of 50 to 300 nm.
Furthermore, the bottom counter bore and the hole expansion are both conical round or square holes with wide upper parts and narrow lower parts, the depth of the bottom counter bore is 200-500 nm, the minimum aperture is 300nm, and the maximum aperture is 600 nm; the depth of the hole expansion is 200-500 nm, the minimum aperture is 700nm, and the maximum aperture is 1000 nm.
Preferably, said DBThe material of the R reflecting layer is TiO2And SiO2Structure of TiO2And SiO2The two materials are periodically arranged in an overlapping manner in the form of ABAB.
The invention also discloses a preparation method of the graphical sapphire substrate for the high-brightness deep ultraviolet LED, which comprises the following steps:
(1) firstly, selecting a sapphire wafer with a smooth surface, and cleaning to remove impurities on the surface;
(2) coating a photoresist coating on the upper surface of the sapphire wafer, and forming a group of photoresist hole structures on the sapphire wafer by a nanoimprint technology;
(3) etching the upper surface of the sapphire wafer by means of inductively coupled plasma etching, so as to form a group of etching holes in the sapphire wafer, wherein the etching holes comprise bottom counter bores and counterbores which are positioned above the bottom counter bores and have the hole diameter larger than the bottom counter bores;
(4) cleaning and removing the residual photoresist on the upper surface of the sapphire wafer by using an SPM solution;
(5) depositing an AlN/AlGaN film on the upper surface of the sapphire wafer and the inner surface of the etching hole by using a metal organic compound chemical vapor deposition method;
(6) coating a layer of negative photoresist on the sapphire wafer on which the AlN/AlGaN film is deposited, and then removing the negative photoresist above the counter bore at the bottom through exposure and development;
(7) removing the AlN/AlGaN film in the bottom counter bore by adopting inductive coupling plasma etching;
(8) removing the residual negative photoresist on the surface of the sapphire wafer by using an SPM solution;
(9) coating a layer of negative photoresist on the sapphire wafer and the etching hole, and then removing the negative photoresist above the bottom counter bore through exposure and development;
(10) depositing nanometer crystal grains on the surface of the developed sapphire wafer by using a chemical vapor deposition method;
(11) forming a nano-scale pattern in the bottom counter bore by inductive coupling plasma etching;
(12) and removing the residual negative photoresist on the surface of the sapphire wafer by using an SPM solution.
The invention also discloses another preparation method of the graphical sapphire substrate for the high-brightness deep ultraviolet LED, which comprises the following steps:
(1) firstly, selecting a sapphire wafer with a smooth surface, and cleaning to remove impurities on the surface;
(2) coating a photoresist coating on the upper surface of the sapphire wafer, and forming a group of photoresist hole structures on the sapphire wafer by a nanoimprint technology;
(3) etching the upper surface of the sapphire wafer by means of inductively coupled plasma etching, so as to form a group of etching holes in the sapphire wafer, wherein the etching holes comprise bottom counter bores and counterbores which are positioned above the bottom counter bores and have the hole diameter larger than the bottom counter bores;
(4) cleaning and removing the residual photoresist on the upper surface of the sapphire wafer by using an SPM solution;
(5) depositing an AlN/AlGaN film on the upper surface of the sapphire wafer and the inner surface of the etching hole by using a metal organic compound chemical vapor deposition method;
(6) coating a layer of negative photoresist on the sapphire wafer on which the AlN/AlGaN film is deposited, and then removing the negative photoresist above the counter bore at the bottom through exposure and development;
(7) removing the AlN/AlGaN film in the bottom counter bore by adopting inductive coupling plasma etching;
(8) removing the residual negativity on the surface of the sapphire wafer by using an SPM solution;
(9) coating a layer of negative photoresist on the sapphire wafer and the etching hole, and then removing the negative photoresist above the bottom counter bore through exposure and development;
(10) depositing DBR reflecting layers on the surface of the developed sapphire wafer and in the bottom counter bore by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method;
(11) and removing the residual negative photoresist on the surface of the sapphire wafer by using an SPM solution to obtain the patterned sapphire substrate.
In order to improve the cleanliness of the sapphire wafer, the sapphire wafer in the step (1) is firstly scrubbed by acetone for 5-10 minutes, and thenThen concentrated H at 90 ℃2SO4And H2O2Cleaning for 10-15 minutes in a mixed solution with a volume ratio of 3: 1-5: 2, cleaning for 8-10 minutes by using 80 ℃ deionized water, finally cleaning for 5-10 minutes by using 25 ℃ deionized water, and then spin-drying for 3-10 minutes at a high speed.
In order to form the etching hole structure in the step 3 conveniently, the thickness of the photoresist coating in the step (2) is 0.3-1 μm, and the angle beta between the side wall and the bottom of the imprinted photoresist hole structure is 100-110 degrees.
Preferably, the step (3) is inductively coupled plasma etching, the power of the upper electrode of the etching machine is 100-3Flow rate of 10-150sccm, CHF3The flow rate is 0-20sccm, the etching temperature is 20-60 ℃, the helium pressure is 1-10mTorr, and the etching time is 300-2000S.
Preferably, the AlN/AlGaN thin film in the step (5) has a thickness of 20 to 3000 nm.
Preferably, the film thickness of the negative photoresist in the steps (6) and (9) is 0.5-2 μm, and the exposure time is 50-300 ms.
Preferably, the nano-scale grain material deposited on the surface of the sapphire wafer in the step (10) is one or a mixture of several metals of Au, Ag, Ni, Co, Fe, Cu, Pt, Pd and Al.
The invention has the beneficial effects that: compared with a non-patterned sapphire wafer structure, the patterned sapphire substrate structure obtained by the invention can reduce the dislocation density of a thin film material. Meanwhile, the light extraction rate of the sapphire wafer can be obviously improved through the special structure and the periodic distribution of the etching holes, and the light extraction rate can be improved by more than 10 percent, so that the brightness of the UVC LED is improved; the etching hole is provided with a bottom counter bore and a hole expansion, a micro nano-scale structure is formed in the bottom counter bore, light can be emitted after being reflected for multiple times in the nano-scale structure, the probability of light refracting into air is increased in the chip stage, and the light extraction efficiency is further increased; or a DBR reflecting layer is arranged in the counter bore at the bottom, and because the reflectivity of the DBR reflecting layer can reach more than 99 percent, the incident light is basically reflected back to the light-emitting layer when passing through the DBR reflecting layer, the light extraction efficiency can also be increased, and the brightness of the UVC LED is improved. The AlN/AlGaN film is deposited on the C surface of the sapphire wafer and the inner surface of the counterbore and can be used as a buffer layer to reduce the lattice mismatch between the sapphire substrate and the epitaxial film, so that the epitaxial growth is facilitated, the yield of an epitaxial wafer is greatly improved, and the quality and the service life of the UVC LED are improved. The invention will be explained in more detail below with reference to the drawings and examples.
Drawings
FIG. 1 is a process flow diagram of example 1 of the present invention.
FIG. 2 is a cross-sectional view of a sapphire wafer having a photoresist coating applied to the surface thereof in accordance with the present invention.
FIG. 3 is a cross-sectional view of a set of photoresist holes formed in the surface of a sapphire wafer in accordance with the present invention.
FIG. 4 is a cross-sectional view of an inductively coupled plasma etch used to form an etch hole in a sapphire wafer in accordance with the present invention.
Fig. 5 is a cross-sectional view of the sapphire wafer of fig. 4 after being cleaned by the SPM solution.
FIG. 6 is a cross-sectional view of an AlN/AlGaN film formed on a sapphire wafer according to the present invention.
FIG. 7 is a cross-sectional view of the present invention forming a negative photoresist coating on the surface of an AlN/AlGaN thin film.
Fig. 8 is a cross-sectional view of a set of negative photoresist holes formed in the sapphire wafer of fig. 7.
FIG. 9 is a cross-sectional view of a sapphire wafer with the AlN/AlGaN film removed from the bottom of the via.
Fig. 10 is a cross-sectional view of the sapphire wafer of fig. 9 after removal of the negative photoresist.
Fig. 11 is a cross-sectional view of a negative photoresist coating formed on the sapphire wafer of fig. 10.
Fig. 12 is a cross-sectional view of a set of negative photoresist holes formed in the sapphire wafer of fig. 11.
FIG. 13 is a cross-sectional view of the negative photoresist holes and the photoresist surface deposited with nanoscale grains of the present invention obtained in FIG. 12.
FIG. 14 is a schematic cross-sectional view of the negative photoresist hole of FIG. 13 and a negative photoresist surface after etching in accordance with the present invention.
Fig. 15 is a sectional view of a sapphire substrate obtained by the present invention.
Fig. 16 is a partial enlarged view of a in fig. 15.
FIG. 17 is an SEM image of an etched hole in a sapphire wafer of the present invention.
FIG. 18 is a process flow diagram of example 2 of the present invention.
FIG. 19 is a cross-sectional view of the invention depositing a DBR reflective layer in a bottom counterbore and negative photoresist surface of a sapphire wafer.
Fig. 20 is a cross-sectional view of a patterned sapphire substrate of the present invention.
Detailed Description
Further, the thickness of the AlN/AlGaN film 6 is 20-3000 nm, the bottom counter bore 401 and the counterbore 402 are both conical round or square holes with wide top and narrow bottom, the depth of the bottom counter bore 401 is 200-500 nm, the minimum aperture is 300nm, and the maximum aperture is 600 nm; the depth of the counterbore 402 is 200-500 nm, the minimum aperture is 700nm, and the maximum aperture is 1000 nm.
A preparation method of a graphical sapphire substrate for a high-brightness deep ultraviolet LED is used for preparing the graphical sapphire substrate for the high-brightness deep ultraviolet LED, and the process flow is shown in figure 1, and comprises the steps of cleaning, gluing, nanoimprint, etching, cleaning, AlN/AlGaN film deposition, gluing, exposure, development, etching, cleaning, gluing, exposure, development, nanocrystal grain deposition, etching and cleaning.
The preparation method comprises the following steps:
(1) the cleaning is carried out, and the cleaning is carried out,firstly, providing a sapphire wafer 1 with a flat surface, brushing the sapphire wafer for 5-10 minutes by acetone, and then carrying out concentrated H at 90 DEG C2SO4And H2O2Cleaning for 10-15 minutes in a mixed solution with a volume ratio of 3: 1-5: 2, cleaning for 8-10 minutes by using 80 ℃ deionized water, finally cleaning for 5-10 minutes by using 25 ℃ deionized water, and then spin-drying for 3-10 minutes at a high speed.
(2) Gluing and nanoimprinting, and coating a photoresist coating layer 2 on the upper surface of the sapphire wafer 1, namely the surface C of the sapphire wafer, by using a glue spreader, wherein the thickness of the coating layer is 0.3-1 mu m, as shown in figure 2; a patterned hard template is prepared and then the pattern on the hard template is replicated on a sapphire wafer 1 coated with photoresist 2 using the currently most established uv nanoimprint technology, forming a set of photoresist hole structures 3, as shown in fig. 3. The angle beta between the side wall and the bottom of the photoresist hole structure is 100-110 degrees.
(3) Etching, wherein the upper surface of the sapphire wafer is etched by means of inductive coupling plasma etching, and during etching, the parameters of an etching machine are as follows: the power of the upper electrode is 100-2000W, the power of the lower electrode is 100-1500W, BCL3Flow rate of 10-150sccm, CHF3The flow rate is 0-20sccm, the etching temperature is 20-60 ℃, and the helium pressure is 1-10mTorr, and the etching time is 300-2000 s. The corner of the photoresist hole structure 3 gradually appears along with gradual reduction of photoresist in the etching process, the prototype of the counterbore 401 starts to appear, then etching is continued for a period of time, and after the etching is finished, part of the photoresist 2 remains on the sapphire wafer 1, as shown in fig. 4, so as to obtain a group of etching holes 4, wherein the etching holes 4 comprise bottom counterbores 401 and counterbores 402 which are located above the bottom counterbores 401 and have a diameter larger than that of the bottom counterbores 401.
(4) Cleaning, removing residual photoresist on the surface of the sapphire wafer by using SPM solution, wherein the SPM solution is H2SO4、H2O2Wherein the ratio of sulfuric acid to hydrogen peroxide is 3: 1-5: 2, cleaning for 15-30 minutes by SPM solution, cleaning for 5-15 minutes by deionized water, and spin-drying for 5-15 minutes to obtain a wafer C surface 101 and etching holes 4 shown in FIG. 5, wherein the SEM image is shown in FIG. 5Shown at 16.
(5) And depositing an AlN/AlGaN film, and depositing an AlN/AlGaN film 6 on the surfaces of the sapphire wafer 1 and the etching holes 4 by using a Metal Organic Chemical Vapor Deposition (MOCVD) method, as shown in FIG. 6, wherein the thickness of the film is 20-3000 nm.
(6) Coating glue, exposing and developing, coating a layer of negative photoresist 7 on the AlN/AlGaN film 6 by using a glue coating machine, wherein the film thickness is 0.5-2 mu m as shown in figure 7, then completely aligning with the sapphire wafer and realizing positioning by using a mask plate or a photoetching plate, and exposing and developing the negative photoresist 7 above the counter bore at the bottom. Exposing for 50-300 ms, and finally developing to obtain the hole 701 and the negative photoresist 702 shown in fig. 8, wherein a bottom counter bore 401 is arranged below the hole 701, and a counter bore 402 and a wafer C surface 101 are arranged below the negative photoresist 702.
(7) Etching, namely, etching and removing the AlN/AlGaN thin film 6 and a part of the negative photoresist 702 in the bottom counter bore 401 by using an inductively coupled plasma etching technology, and ending the etching after the AlN/AlGaN thin film 6 in the bottom counter bore 401 is etched and removed, as shown in fig. 9, so as to obtain the bottom counter bore 401 without the AlN/AlGaN thin film 6 on the surface and a part of the negative photoresist 703.
(8) Cleaning, and removing part of residual negative photoresist 703 by using an SPM solution, wherein the ratio of sulfuric acid to hydrogen peroxide is 3: 1-5: 2, a bare bottom counterbore 401 and counterbore 402 with AlN/AlGaN film 6 on the surface and wafer C face 101 are obtained, as shown in fig. 10.
(9) Coating a layer of negative photoresist 8 on the surface of the sapphire wafer obtained in the step 8, as shown in fig. 11, wherein the film thickness is 0.5-2 μm, then using a mask plate or a photoetching plate to completely align and position the sapphire wafer, and exposing and developing the negative photoresist 7 above the counter bore at the bottom. Exposing for 50-300 ms, and finally developing to obtain a hole 801 and a negative photoresist 802 shown in fig. 12, wherein a bottom counter bore 401 is arranged below the hole 801, and a counter bore 402 and a wafer C surface 101 are arranged below the negative photoresist 802.
(10) Depositing nano-scale grains, and depositing nano-scale grains 9 on the surface of the bottom counter bore 401 and the negative photoresist 802 by using a CVD (chemical vapor deposition) technology, wherein the grains 9 are metal particles of one or a mixture of more of Au, Ag, Ni, Co, Fe, Cu, Pt, Pd and Al, as shown in FIG. 13.
(11) Etching, namely etching the upper surface of the sapphire wafer by means of inductive coupling plasma etching, forming a nano-scale pattern 10 on the surfaces of the negative photoresist 802 and the bottom counter bore 401, wherein the nano-scale pattern 10 can greatly improve the brightness of a UVC LED chip prepared by the patterned sapphire substrate;
(12) and finally, removing the residual negative photoresist 802 on the surface of the wafer by using an SPM solution to obtain the graphical sapphire substrate for the high-brightness deep ultraviolet LED, as shown in FIG. 15, namely, an etching hole structure with a hole expansion 402 and a bottom counter bore 401 is provided, wherein a layer of 20-3000 nmAl N/AlGaN film 6 with the thickness of 20-3000 nmAl is arranged above the hole expansion 402 and the C surface 101 of the wafer, and a nanoscale pattern 10 is arranged on the surface of the bottom counter bore 401. Fig. 16 is a partially enlarged view of the region a shown in fig. 15.
Example 2: a high-quality deep ultraviolet LED is with graphical sapphire substrate, for the base material of preparation UVC LED, as shown in fig. 20, including sapphire wafer 1, sapphire wafer 1 includes wafer C face 101 that is used for forming the patterning, evenly distributed has etch hole 4 on wafer C face 101, etch hole 4 includes bottom counter bore 401 and is located bottom counter bore 401 top and the reaming 402 that the aperture is greater than bottom counter bore 401, sapphire wafer C face 101 and the surface of reaming 402 deposit has one deck AlN/AlGaN film 6, be provided with DBR reflecting layer 11 in the bottom counter bore 401. The bottom counter bore 401 and the counterbore 402 are both conical round or square holes with wide upper parts and narrow lower parts, the depth of the bottom counter bore 401 is 200-500 nm, the minimum aperture is 300nm, and the maximum aperture is 600 nm; the depth of the counterbore 402 is 200-500 nm, the minimum aperture is 700nm, and the maximum aperture is 1000 nm.
The AlN/AlGaN film 6 has a thickness of 20 to 3000nm, and the DBR reflective layer 11 has a thickness of 50 to 300 nm. The DBR reflecting layer 11 is made of TiO2 and SiO2, and has a TiO structure2And SiO2The two materials are periodically arranged in an overlapping manner in the form of ABAB.
A preparation method of a high-quality graphical sapphire substrate for a UVC LED is used for preparing the high-quality graphical sapphire substrate for the UVC LED, and the process flow is shown in figure 18.
The preparation method comprises the following steps:
(1) cleaning, namely firstly providing a sapphire wafer 1 with a flat surface, brushing the sapphire wafer for 5-10 minutes by acetone, and then carrying out concentrated H at 90 DEG C2SO4And H2O2Cleaning for 10-15 minutes in a mixed solution with a volume ratio of 3: 1-5: 2, cleaning for 8-10 minutes by using 80 ℃ deionized water, finally cleaning for 5-10 minutes by using 25 ℃ deionized water, and then spin-drying for 3-10 minutes at a high speed.
(2) Gluing and nanoimprinting, and coating a photoresist coating layer 2 on the upper surface of the sapphire wafer 1, namely the surface C of the sapphire wafer, by using a glue spreader, wherein the thickness of the coating layer is 0.3-1 mu m, as shown in figure 2; a patterned hard template is prepared and then the pattern on the hard template is replicated on a sapphire wafer 1 coated with photoresist 2 using the currently most established uv nanoimprint technology, forming a set of photoresist hole structures 3, as shown in fig. 3. The angle beta between the side wall and the bottom of the photoresist hole structure is 100-110 degrees.
(3) Etching, wherein the upper surface of the sapphire wafer is etched by means of inductive coupling plasma etching, and during etching, the parameters of an etching machine are as follows: the power of the upper electrode is 100-2000W, the power of the lower electrode is 100-1500W, BCL3Flow rate of 10-150sccm, CHF3The flow rate is 0-20sccm, the etching temperature is 20-60 ℃, and the helium pressure is 1-10mTorr, and the etching time is 300-2000 s. The photoresist hole structure 3 is gradually reduced along with the photoresist 2 in the etching process, the corner gradually appears, the prototype of the counterbore 401 starts to appear, then etching is continued for a period of time, and after the etching is finished, part of the photoresist 2 remains on the sapphire wafer 1, as shown in fig. 4, so that a group of etching holes 4 are obtained, wherein the etching holes 4 comprise bottom counterbores 401 and counterbores 402 which are located above the bottom counterbores 401 and have the hole diameter larger than that of the bottom counterbores 401.
(4) Cleaning and benefitingRemoving residual photoresist on the surface of the sapphire wafer by using an SPM solution, wherein the SPM solution is H2SO4、H2O2Wherein the ratio of sulfuric acid to hydrogen peroxide is 3: 1-5: 2, cleaning for 15-30 minutes by SPM solution, cleaning for 5-15 minutes by deionized water, and spin-drying for 5-15 minutes to obtain a wafer C surface 101 and etching holes 4 shown in FIG. 5, wherein the SEM picture is shown in FIG. 17.
(5) And depositing an AlN/AlGaN film, and depositing an AlN/AlGaN film 6 on the surfaces of the sapphire wafer 1 and the etching holes 4 by using a Metal Organic Chemical Vapor Deposition (MOCVD) method, as shown in FIG. 6, wherein the thickness of the film is 20-3000 nm.
(6) Coating glue, exposing and developing, coating a layer of negative photoresist 7 on the AlN/AlGaN film 6 by using a glue coating machine, wherein the film thickness is 0.5-2 mu m as shown in figure 7, then completely aligning with the sapphire wafer and realizing positioning by using a mask plate or a photoetching plate, and exposing and developing the negative photoresist 7 above the counter bore at the bottom. Exposing for 50-300 ms, and finally developing to obtain the hole 701 and the negative photoresist 702 shown in fig. 8, wherein a bottom counter bore 401 is arranged below the hole 701, and a counter bore 402 and a wafer C surface 101 are arranged below the negative photoresist 702.
(7) Etching, namely, etching and removing the AlN/AlGaN film 6 and a part of the negative photoresist 702 in the bottom counter bore 401 by adopting an inductive coupling plasma etching technology, and ending the etching after the AlN/AlGaN film 6 in the bottom counter bore 401 is etched and removed, as shown in FIG. 9, so as to obtain the bottom counter bore 401 without the AlN/AlGaN film 6 on the surface and a part of the residual negativity 703.
(8) Cleaning, and removing part of residual negative photoresist 703 by using an SPM solution, wherein the ratio of sulfuric acid to hydrogen peroxide is 3: 1-5: 2, a bare bottom counterbore 401 and counterbore 402 with AlN/AlGaN film 6 on the surface and wafer C face 101 are obtained, as shown in fig. 10.
(9) Coating a layer of negative photoresist 8 on the surface of the sapphire wafer obtained in the step 8, as shown in fig. 11, wherein the film thickness is 0.5-2 μm, then using a mask plate or a photoetching plate to completely align and position the sapphire wafer, and exposing and developing the negative photoresist 7 above the counter bore at the bottom. Exposing for 50-300 ms, and finally developing to obtain a hole 801 and a negative photoresist 802 shown in fig. 12, wherein a bottom counter bore 401 is arranged below the hole 801, and a counter bore 402 and a wafer C surface 101 are arranged below the negative photoresist 802.
(10) Depositing a DBR reflective layer, and depositing the DBR reflective layer 11 on the bottom counter bore 401 and the surface of the negative photoresist 802 by Plasma Enhanced Chemical Vapor Deposition (PECVD), although not limited to this deposition method, electron beam evaporation, magnetron sputtering, etc. may also be used, and the DBR reflective layer 11 uses two materials of TiO2 and SiO2, and has a structure of TiO2And SiO2The two materials are periodically stacked and overlapped in an ABAB mode, and the thickness of the DBR reflecting layer 11 is 50-300 nm, as shown in figure 19.
(11) Cleaning, and finally removing the residual negative photoresist 802 on the surface of the wafer by using an SPM solution to obtain a high-quality patterned sapphire substrate for UVC LEDs, as shown in FIG. 20, namely, an etching hole structure with a hole expansion 402 and a bottom counterbore 401, wherein a layer of AlGaN/AlGaN film 6 with a thickness of 20-3000 nmAl is arranged above the hole expansion 402 and the C surface 101 of the wafer, and the surface of the bottom counterbore 401 is provided with a DBR reflecting layer 11.
The invention is described above with reference to the accompanying drawings. It is to be understood that the specific implementations of the invention are not limited in this respect. Various insubstantial improvements are made by adopting the method conception and the technical scheme of the invention; the present invention is not limited to the above embodiments, and can be modified in various ways.
Claims (11)
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