CN111522643B - Multi-queue scheduling method and device based on FPGA, computer equipment and storage medium - Google Patents
Multi-queue scheduling method and device based on FPGA, computer equipment and storage medium Download PDFInfo
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Abstract
The application provides a multi-queue scheduling method and device based on an FPGA, computer equipment and a storage medium. Wherein the method comprises the following steps: storing cells of a plurality of channels into a plurality of queues in a buffer space one by one; when one cell is stored in one queue, determining the queue as a queue to be scheduled; and scheduling sequentially by using the read pointer of each queue to be scheduled according to the time difference of the cell stored in the queue. Therefore, the fairness scheduling functionality can be ensured, and resources occupied by the FPGA when the multi-queue is scheduled can be effectively reduced.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method and apparatus for scheduling multiple queues based on FPGA, a computer device, and a storage medium.
Background
Multi-queue scheduling can be classified into prioritized scheduling and non-prioritized scheduling. Priority scheduling is carried out, namely the scheduling sequence is determined according to the priority of each queue; there is no priority scheduling, and there is no priority division among queues, and fair scheduling is usually required for each queue to ensure fairness of scheduling. In the related art, when there are multiple queues without priority on the FPGA to be scheduled, an independent FIFO (First Input First Output, first in first out) memory is used to buffer the cells of each queue, and the cells of each queue are scheduled in a preemptive scheduling manner, so that the cells of each queue are uniformly scheduled out. While preemptive scheduling can ensure fairness of scheduling and has high scheduling performance, the preemptive scheduling increases complexity of codes and occupies more resources.
Disclosure of Invention
In order to overcome the problems in the related art, the application provides a multi-queue scheduling method, a multi-queue scheduling device, a multi-queue scheduling computer device and a multi-queue scheduling storage medium based on an FPGA.
According to a first aspect of an embodiment of the present application, there is provided an FPGA-based multi-queue scheduling method, the method including:
storing cells of a plurality of channels into a plurality of queues in a buffer space one by one;
When one cell is stored in one queue, determining the queue as a queue to be scheduled;
And scheduling sequentially by using the read pointer of each queue to be scheduled according to the time difference of the cell stored in the queue.
According to a second aspect of an embodiment of the present application, there is provided an FPGA-based multi-queue scheduling apparatus, the apparatus including:
a storage module configured to store cells of a plurality of channels one by one into a plurality of queues in one buffer space;
A determining module configured to determine, when a cell is stored in a queue, that the queue is a queue to be scheduled;
And the scheduling module is configured to schedule by utilizing the read pointer of each queue to be scheduled in turn according to the time difference of the cell stored in the queue.
According to a third aspect of embodiments of the present application, there is provided a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of:
storing cells of a plurality of channels into a plurality of queues in a buffer space one by one;
When one cell is stored in one queue, determining the queue as a queue to be scheduled;
And scheduling sequentially by using the read pointer of each queue to be scheduled according to the time difference of the cell stored in the queue.
According to a fourth aspect of embodiments of the present application, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of:
storing cells of a plurality of channels into a plurality of queues in a buffer space one by one;
When one cell is stored in one queue, determining the queue as a queue to be scheduled;
And scheduling sequentially by using the read pointer of each queue to be scheduled according to the time difference of the cell stored in the queue.
The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:
In the technical scheme, the received cells of a plurality of channels are stored into a plurality of queues in a cache space of the FPGA one by one. As long as a queue is determined to be a queue to be scheduled, scheduling is performed using the read pointer of the queue, and a cell of the queue is called. When the cells are input into the corresponding queues one by one, the queues can be determined to be the queues to be scheduled successively. After one queue completes one-time scheduling, other queues in the queues to be scheduled are selected for scheduling, and the scheduling is performed by pushing the other queues, so that the scheduling of a plurality of queues is completed. The technical scheme completes the scheduling of a plurality of queues in one buffer space, and sequentially schedules one cell of each queue. Therefore, the fairness scheduling functionality can be ensured, and resources occupied by the FPGA when the multi-queue is scheduled can be effectively reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a flow chart of a multi-queue scheduling method based on FPGA according to an exemplary embodiment of the present application.
Fig. 2 is an application schematic diagram of a multi-queue scheduling method based on FPGA according to an exemplary embodiment of the present application.
Fig. 3 is an application schematic diagram of a multi-queue scheduling method based on FPGA according to an exemplary embodiment of the present application.
Fig. 4 is a schematic structural diagram of an FPGA-based multi-queue scheduling apparatus according to an exemplary embodiment of the present application.
Fig. 5 is a schematic structural diagram of a computer device according to an exemplary embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" depending on the context.
The following describes in detail the method, the device, the computer equipment and the storage medium for scheduling multiple queues based on the FPGA according to the present application with reference to the accompanying drawings. The features of the examples and embodiments described below may be combined with each other without conflict.
The application provides a multi-queue scheduling method based on an FPGA. Fig. 1 is a flow chart of a multi-queue scheduling method based on FPGA according to an exemplary embodiment of the present application. As shown in fig. 1, the FPGA-based multi-queue scheduling method includes the following steps 101 to 103:
step 101, storing the cells of multiple channels into multiple queues in a buffer space one by one.
In this step, the FPGA may receive multi-channel cells from the external device, the cells of the multiple channels may be input to the FPGA through the serial interface, the FPGA may call RAM (Random Access Memory ) resources, input the cells one by one into one buffer space, and distribute the cells to multiple queues in the buffer space. The plurality of channels correspond to the plurality of queues, and a plurality of cells can be included in one channel, so that the plurality of cells in the channel are stored in the same queue one by one. In one example, if a larger cache space is required, a Block RAM (random access memory) resource may be invoked. In another example, if less cache space is needed, distributed RAM resources may be called.
Step 102, when a cell is stored in a queue, determining the queue as a queue to be scheduled.
In this step, when a cell is stored in a queue, the queue may be considered to have a scheduling requirement, i.e. the queue may be determined to be the queue to be scheduled. It should be appreciated that when a queue has no cell input storage, then the queue has no scheduling requirements.
It should be noted that a queue may include a write pointer and a read pointer, and when a cell is stored in the buffer space, writing and reading are performed by means of the read-write pointer. When a cell is stored in a queue, adding 1 to the write pointer of the queue; when a cell calls out a queue, the read pointer of the queue is incremented by 1.
It will be appreciated that the memory space of each queue may be limited, and that when a stored cell arrives at the memory space of the queue, the value of the write pointer will reach a maximum value, and that due to the dynamic scheduling of the queue, if one cell is called out, a memory space will also be released, a subsequent cell will continue to be stored in the queue, and when the value of the write pointer is added to the corresponding maximum value of the memory space of the queue, the next stored cell will return to the starting value. For example, a queue may store a maximum of 7 cells, the value of the write pointer is 1 when the queue stores the first cell, the value of the write pointer is 7 when the queue stores the 7 cells, the queue may continue to store cells if the subsequent queue schedules to retrieve at least one cell, and the value of the write pointer of the queue returns to the starting value, i.e., the value of the write pointer is 1, when the 8 th cell stores the queue. It will be appreciated that the dynamic change of the value of the read pointer is similar to that of the write pointer and will not be described in detail here.
And 103, scheduling sequentially by using the read pointer of each queue to be scheduled according to the time difference of the cell stored in the queue.
In this step, when a queue is determined as a queue to be scheduled, scheduling of the queue may be triggered, and cells in the queue are fetched and output by using the obtained read pointer of the queue, so as to complete one-time scheduling of the queue. Since cells can be simultaneously and continuously input in the buffer space in the scheduling process of one queue, when other queues have cells stored, the cells can be determined as the queues to be scheduled. When one queue completes one scheduling, there are multiple queues to be scheduled, and to ensure fair scheduling, other queues that have not been scheduled may be scheduled. If there are multiple queues to be scheduled, the sequence of each queue to be scheduled can be determined according to the time difference of the cells stored in the queues, and then the next queue to be scheduled is determined and scheduled according to the sequence.
In the multi-queue scheduling method based on the FPGA of this embodiment, the received cells of the multiple channels are stored one by one into multiple queues in one buffer space of the FPGA. As long as a queue is determined to be a queue to be scheduled, scheduling is performed using the read pointer of the queue, and a cell of the queue is called. When the cells are input into the corresponding queues one by one, the queues can be determined to be the queues to be scheduled successively. After one queue completes one-time scheduling, other queues in the queues to be scheduled are selected for scheduling, and the scheduling is performed by pushing the other queues, so that the scheduling of a plurality of queues is completed. The technical scheme completes the scheduling of a plurality of queues in one buffer space, and sequentially schedules one cell of each queue. Therefore, the fairness scheduling functionality can be ensured, and resources occupied by the FPGA when the multi-queue is scheduled can be effectively reduced.
In an exemplary embodiment of the present application, when an information element is stored in a queue, the step of determining that the queue is scheduled as a queue to be scheduled includes: when one cell is stored in one queue, updating the queue state identifier of the queue into a non-empty state; and determining the queue to be a queue to be scheduled based on the non-empty state.
In this embodiment, the queue status identifier may describe the empty-full status of a queue, i.e. whether there are cells in the queue that need to be scheduled. And determining whether the queue has scheduling requirements or not by judging the queue state identification of the queue, and determining whether the queue is a queue to be scheduled or not. In one example, a queue status identification may be described as0, 1, e.g., when the queue is in an empty state, the queue status identification is 0; when the queue is in a non-empty state, the queue state is identified as 1.
The empty and full state of a queue can be controlled by the write pointer and the read pointer of the queue, and when the values of the read pointer and the write pointer are equal, the queue is in the empty state; when the value of the read pointer is less than the value of the write pointer, the queue is in a non-empty state.
To more clearly understand the one-time scheduling process, in an exemplary embodiment of the present application, the process of scheduling each queue to be scheduled may include the steps of:
1) Reading a read pointer and a write pointer of a current queue to be scheduled based on the queue number of the queue to be scheduled;
2) Determining whether the queue to be scheduled is in a non-empty state or not based on the read pointer and the write pointer of the queue to be scheduled;
3) And if so, calling and outputting one cell in the queue to be scheduled through the read pointer of the queue to be scheduled.
In this embodiment, the read pointer and the write pointer of the corresponding queue may be read according to the queue number of the queue to be scheduled, and whether the queue to be scheduled is in a non-empty state is determined again by the values of the read pointer and the write pointer, so as to ensure that the situation of scheduling wheel empty does not occur. If the queue to be scheduled is in a non-empty state, a cell is fetched by the read pointer of the queue and is output to complete one-time scheduling.
In an exemplary embodiment of the present application, if the read pointer and the write pointer of the queue to be scheduled are equal, i.e. the queue to be scheduled is in an empty state, no scheduling output is performed.
In order to avoid the situation that when the queue is scheduled subsequently, the queue is empty, so that the queue is empty, in an exemplary embodiment of the present application, after updating the read pointer of the queue to be scheduled, the method further includes: and determining whether to update the queue state identification of the queue to be scheduled based on the current write pointer and the updated read pointer of the queue to be scheduled. Therefore, the state of the queue can be updated so as to determine whether the queue is a queue to be scheduled according to the latest state of the queue, scheduling round-robin is avoided, time can be saved, and resource occupation can be reduced.
It will be appreciated that there will be some scheduling overhead due to the delay in updating the state of the queues, however, as throughput increases, a large number of cells will be accumulated due to previous overhead, and the number of overhead will be gradually reduced for each queue to cache a portion of cells, even without overhead.
In an exemplary embodiment of the present application, after obtaining the current write pointer and the updated read pointer of the queue to be scheduled, the method further includes: and when the difference between the current write pointer and the updated read pointer is smaller than the set difference, sending a reminding signal, wherein the reminding signal is used for reminding a queue to be in a state close to full so as to adjust the sequence of sending cells by a plurality of channels. Thus, the situation of the queue to be fully stored can be fed back to the external equipment, the external equipment can decide the output of each queue after acquiring the information, and the situation that the storage space is released to cause blockage by the queue which is still queuing the cell in the buffer space and is in a state of being fully stored can be avoided.
In order to more clearly understand the technical solution of the present application, fig. 2 is an application schematic diagram of an FPGA-based multi-queue scheduling method according to an exemplary embodiment of the present application. As shown in fig. 2, the FPGA-based multi-queue scheduling method of the present application may be applied to multi-channel scheduling of DMA (Direct Memory Access ), where the CPU stores cells of multiple channels in multiple queues respectively, sends the cells to the FPGA through PCIE (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, high-speed serial computer expansion bus standard) interface, stores the cells in multiple queues in a buffer space, and then sequentially schedules the multiple queues by the DMA, and outputs the cells of each queue.
When there is a situation that the number of queues is large, directly scheduling each queue occupies more RAM resources of the FPGA, in an exemplary embodiment of the present application, the queues may be grouped, one queue in each group may be scheduled, and each group may be scheduled in turn, so as to ensure fairness. And each packet completes one-time scheduling, the position of the current scheduling is recorded, namely, the queue which completes one-time scheduling is recorded, and when the next round of scheduling is completed for the packet, the next-time scheduling queue can be determined to be other queues except the scheduled queue according to the recorded position of the last scheduling.
Fig. 3 is an application schematic diagram of a multi-queue scheduling method based on FPGA according to an exemplary embodiment of the present application. As shown in fig. 3, there are 16 queues to be scheduled, in this embodiment, the queue status line is divided into 4-bit groups by using the 6-input characteristic of the LUT (Look-Up Table), and each group records the last scheduled position by using 2 bits, so that the use of the LUT can be saved, the maximum scheduling performance is ensured, and a register can be inserted between the cascade of the multiple levels of LUTs to improve the scheduling timing.
The application also provides a multi-queue scheduling device based on the FPGA. Fig. 4 is a schematic structural diagram of an FPGA-based multi-queue scheduling apparatus according to an exemplary embodiment of the present application. As shown in fig. 4, the apparatus 40 includes:
a storage module 410 configured to store cells of a plurality of channels one by one into a plurality of queues in a buffer space;
a determining module 420 configured to determine, when a cell is stored in a queue, that the queue is a queue to be scheduled;
the scheduling module 430 is configured to schedule in turn using the read pointer of each queue to be scheduled according to the time difference of the cells stored in the queue.
In an exemplary embodiment of the present application, the determining module includes:
a first updating sub-module configured to update a queue status identifier of a queue to a non-empty status when a cell is stored in the queue;
A first determination submodule configured to determine the queue to be a queue to be scheduled based on the non-empty state.
In an exemplary embodiment of the application, the first update sub-module is further configured to increment the write pointer of a queue by 1 when a cell is stored to the queue.
In an exemplary embodiment of the present application, the scheduling module includes:
A reading submodule configured to read a read pointer and a write pointer of a current queue to be scheduled based on a queue number of the queue to be scheduled;
A second determination submodule configured to determine whether the queue to be scheduled is in a non-empty state based on a read pointer and a write pointer of the queue to be scheduled;
and the scheduling sub-module is configured to call and output one cell in the queue to be scheduled through the read pointer of the queue to be scheduled if the cell is.
In an exemplary embodiment of the present application, the scheduling module further includes:
And the second updating sub-module is configured to increment the read pointer of the queue to be scheduled by 1 after the cell of the queue to be scheduled is fetched and output.
In an exemplary embodiment of the present application, the scheduling module further includes:
and the third updating sub-module is configured to determine whether to update the queue state identification of the queue to be scheduled based on the current write pointer and the updated read pointer of the queue to be scheduled after updating the read pointer of the queue to be scheduled.
In an exemplary embodiment of the present application, the scheduling module further includes:
And the sending module is configured to send a reminding signal after the current write pointer and the updated read pointer of the queue to be scheduled are acquired, and the reminding signal is used for reminding that one queue is in a state close to full so as to adjust the sequence of sending cells of a plurality of channels when the difference between the current write pointer and the updated read pointer is smaller than a set difference.
The implementation process of the functions and roles of each module in the above device is specifically shown in the implementation process of the corresponding steps in the above method, and will not be described herein again.
For the device embodiments, reference is made to the description of the method embodiments for the relevant points, since they essentially correspond to the method embodiments. The apparatus embodiments described above are merely illustrative, wherein the modules illustrated as separate components may or may not be physically separate, and the components shown as modules may or may not be physical, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purposes of the present application. Those of ordinary skill in the art will understand and implement the present application without undue burden.
The application also provides computer equipment. Fig. 5 is a schematic structural diagram of a computer device according to an exemplary embodiment of the present application. As shown in fig. 5, the computer device 50 includes a memory, a processor, and a computer program stored on the memory and executable on the processor, which when executed by the processor performs the steps of:
storing cells of a plurality of channels into a plurality of queues in a buffer space one by one;
When one cell is stored in one queue, determining the queue as a queue to be scheduled;
And scheduling sequentially by using the read pointer of each queue to be scheduled according to the time difference of the cell stored in the queue.
The present application also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of:
storing cells of a plurality of channels into a plurality of queues in a buffer space one by one;
When one cell is stored in one queue, determining the queue as a queue to be scheduled;
And scheduling sequentially by using the read pointer of each queue to be scheduled according to the time difference of the cell stored in the queue.
Embodiments of the application may take the form of a computer program product embodied on one or more readable media (including, but not limited to, magnetic disk storage, CD-ROM, optical storage, etc.) having program code embodied therein. Computer-usable readable media include both permanent and non-permanent, removable and non-removable media, and information storage may be implemented by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer readable media include, but are not limited to: phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Disks (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, may be used to store information that may be accessed by the computing device.
The foregoing describes certain embodiments of the present application. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be regarded as the scope of the present application.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.
Claims (9)
1. An FPGA-based multi-queue scheduling method, the method comprising:
storing the cells sent by the channels into a plurality of queues in a buffer space one by one;
When one cell is stored in one queue, determining the queue as a queue to be scheduled;
scheduling sequentially by using the read pointer of each queue to be scheduled according to the time difference of the cell stored in the queue;
Updating a read pointer of any one of the queues to be scheduled after any one of the cells in the queues to be scheduled is scheduled and output; and sending a reminding signal when the difference between the current write pointer and the updated read pointer of any queue to be scheduled is smaller than a set difference, wherein the reminding signal is used for reminding the any queue to be scheduled to be in a state close to full so as to adjust the sequence of sending cells by the channels.
2. The FPGA-based multi-queue scheduling method of claim 1, wherein when one cell is stored in one queue, determining that the queue is scheduled as a queue to be scheduled comprises:
When one cell is stored in one queue, updating the queue state identifier of the queue into a non-empty state;
and determining the queue to be a queue to be scheduled based on the non-empty state.
3. The FPGA-based multi-queue scheduling method of claim 2, further comprising, when one cell is stored to one queue:
the write pointer of the queue is incremented by 1.
4. The FPGA-based multi-queue scheduling method of claim 3, wherein the step of scheduling each queue to be scheduled comprises:
reading a read pointer and a write pointer of a current queue to be scheduled based on the queue number of the queue to be scheduled;
Determining whether the queue to be scheduled is in a non-empty state or not based on the read pointer and the write pointer of the queue to be scheduled;
And if so, calling and outputting one cell in the queue to be scheduled through the read pointer of the queue to be scheduled.
5. The FPGA-based multi-queue scheduling method of claim 4, wherein updating the read pointer of any one of the queues to be scheduled further comprises:
and adding 1 to the read pointer of any queue to be scheduled.
6. The FPGA-based multi-queue scheduling method of claim 5, further comprising, after updating the read pointer of the queue to be scheduled:
and determining whether to update the queue state identification of the queue to be scheduled based on the current write pointer and the updated read pointer of the queue to be scheduled.
7. An FPGA-based multi-queue scheduling apparatus, the apparatus comprising:
the storage module is configured to store cells sent by a plurality of channels into a plurality of queues in a buffer space one by one;
A determining module configured to determine, when a cell is stored in a queue, that the queue is a queue to be scheduled;
the scheduling module is configured to schedule sequentially by using the read pointer of each queue to be scheduled according to the time difference of the cell stored in the queue;
An adjustment module configured to update a read pointer of any one of the queues to be scheduled after scheduling and outputting any one of the cells in the queue to be scheduled; and sending a reminding signal when the difference between the current write pointer and the updated read pointer of any queue to be scheduled is smaller than a set difference, wherein the reminding signal is used for reminding the any queue to be scheduled to be in a state close to full so as to adjust the sequence of sending cells by the channels.
8. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the FPGA-based multi-queue scheduling method of any one of claims 1 to 6 when the program is executed by the processor.
9. A computer readable storage medium having stored thereon a computer program, characterized in that the program when executed by a processor implements the steps of the FPGA-based multi-queue scheduling method of any one of claims 1 to 6.
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| CN112559041B (en) * | 2020-12-07 | 2022-06-07 | 山东航天电子技术研究所 | A Compatible Processing Method for Direct Commands on the Ground and Autonomous Commands on the Satellite |
| WO2023000188A1 (en) * | 2021-07-21 | 2023-01-26 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN114245469B (en) * | 2022-02-23 | 2022-06-03 | 南京风启科技有限公司 | Multi-stage scheduling method supporting multiple time periods |
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| CN117834556B (en) * | 2023-12-15 | 2025-11-07 | 南京金阵微电子技术有限公司 | Multi-queue organization and scheduling method, system, storage medium and electronic equipment |
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